This thesis describes the design and implementation of a Linux-based, Web-oriented operating system called Awesom-O, designed with a focus on short boot time and small disk footprint. Among other techniques for lowering boot time, a semi-automatic method for generating a Linux kernel of minimal size for a given platform is developed, making use of an interpreter for the Linux kernel’s configuration language, Kconfig. The boot process of the finished system is analyzed to identify limiting factors in lowering its boot time further, and techniques for overcoming these are suggested. Excluding the initial BIOS stage of the boot process, the boot time of the finished system—up until it is idling inside the web browser interface waiting for user input—is 3.8 seconds (2.1 seconds to a shell prompt, 1.7 seconds in the kernel) on an Acer Travelmate 8200 laptop with an Intel Core Duo CPU at 2.0 GHz and a Momentus 5400.2 SATA (ST9120821AS) hard drive; 2.4 seconds (1.6 seconds to a shell prompt, 1.1 seconds in the kernel) on a Celsius M460 workstation with an Intel Core 2 Quad CPU at 2.5 GHz and a Barracuda 7200.11 SATA hard drive (ST3500320AS); 4.6 and 4.0 seconds respectively for the same systems when booting from a USB 2.0 device (a ChipsBank CBM2080 USB 2.0 stick); and 12.6 seconds on the BeagleBoard (8 seconds in the bootloader—an obvious area for future improvement). The Web functionality in Awesom-O is implemented atop the Opera Linux Devices SDK: a software framework for integrating web browser functionality in small Linux-based systems.

Weed control is nowadays a hi-tech discipline. Inter-row weed control is very sophisticated whereas the intra-row weed control lacks a lot. The aim of this pro ject is to implement an embedded system of an autonomous vision based intra-row weeding robot. Weed and crops can be distinguished due to several attributes like colour, shape and context fea- tures. Using an emebedded system has several advantages. The embedded system is specialized on video processing and is designed to withstand the needs of outdoor use. This embedded system is already able to distinguish between weed and crops. The per- formance of the hardware is very good whereas the software still needs some optimizations.

In communication systems, the need for high bandwidth interconnects and efficient distribution of large amount of data is very essential. This thesis work addresses all-optical packet switching issues in the field of reconfigurable optical interconnection networks for high performance embedded systems. The recent research conducted at the Halmstad University, on high performance embedded systems, focuses on the optical interconnection techniques to achieve ultra high throughputs and reconfigurability at the system level. Recent research in the field of optical interconnection networks for applications like switches and routers for data and telecommunication industry and parallel computing architectures for embedded signal processing use optical to electrical conversion to switch packets. This conversion scales down the enormous bandwidth capacity of the optical communication channels to electronic processing rates. To maintain the high throughputs all over the interconnection networks, the optical packets need to be maintained in optical state and switched to different part of the interconnection network. To achieve this goal, all-optical packet switching architectures are studied. The study is concluded with a positive outlook towards alloptical switching technologies, and it will play a very important role in the near future in the field of optical communication, telecommunication and embedded systems.

Energetic particle (alpha particle, cosmic neutron, etc.) induced single event data upset or soft error has emerged as a key reliability concern in SRAMs in sub-100 nanometre technologies. Low operating voltage, small node capacitance, high packing density, and lack of error masking mechanisms are primarily responsible for the soft error susceptibility of SRAMs. In addition, since SRAM occupies the majority of die area in system-on-chips (SoCs) and microprocessors, different leakage reduction techniques, such as, supply voltage reduction, gated grounding, etc., are applied to SRAMs in order to limit the overall chip leakage. These leakage reduction techniques exponentially increase the soft error rate in SRAMs. The soft error rate is further accentuated by process variations, which are prominent in scaled-down technologies. In this research, we address these concerns and propose techniques to characterize and mitigate soft errors in nanoscale SRAMs. We develop a comprehensive analytical model of the critical charge, which is a key to assessing the soft error susceptibility of SRAMs. The model is based on the dynamic behaviour of the cell and a simple decoupling technique for the non-linearly coupled storage nodes. The model describes the critical charge in terms of NMOS and PMOS transistor parameters, cell supply voltage, and noise current parameters. Consequently, it enables characterizing the spread of critical charge due to process induced variations in these parameters and to manufacturing defects, such as, resistive contacts or vias. In addition, the model can estimate the improvement in critical charge when MIM capacitors are added to the cell in order to improve the soft error robustness. The model is validated by SPICE simulations (90nm CMOS) and radiation test. The critical charge calculated by the model is in good agreement with SPICE simulations with a maximum discrepancy of less than 5%. The soft error rate estimated by the model for low voltage (sub 0.8 V) operations is within 10% of the soft error rate measured in the radiation test. Therefore, the model can serve as a reliable alternative to time consuming SPICE simulations for optimizing the critical charge and hence the soft error rate at the design stage. In order to limit the soft error rate further, we propose an area-efficient multiword based error correction code (MECC) scheme. The MECC scheme combines four 32 bit data words to form a composite 128 bit ECC word and uses an optimized 4-input transmission-gate XOR logic. Thus MECC significantly reduces the area overhead for check-bit storage and the delay penalty for error correction. In addition, MECC interleaves two composite words in a row for limiting cosmic neutron induced multi-bit errors. The ground potentials of the composite words are controlled to minimize leakage power without compromising the read data stability. However, use of composite words involves a unique write operation where one data word is written while other three data words are read to update the check-bits. A power efficient word line signaling technique is developed to facilitate the write operation. A 64 kb SRAM macro with MECC is designed and fabricated in a commercial 90nm CMOS technology. Measurement results show that the SRAM consumes 534 μW at 100 MHz with a data latency of 3.3 ns for a single bit error correction. This translates into 82% per-bit energy saving and 8x speed improvement over recently reported multiword ECC schemes. Accelerated neutron radiation test carried out at TRIUMF in Vancouver confirms that the proposed MECC scheme can correct up to 85% of soft errors.

Cardiologists can gain useful insight into a patient's condition when they are able to correlate the patent's symptoms and activities. For this purpose, a Holter Monitor is often used - a portable electrocardiogram (ECG) recorder worn by the patient for a period of 24-72 hours. Preferably, the monitor is not cumbersome to the patient and thus it should be designed to be as small and light as possible; however, the storage requirements for such a long signal are very large and can significantly increase the recorder's size and cost, and so signal compression is often employed. At the same time, the decompressed signal must contain enough detail for the cardiologist to be able to identify irregularities. "Lossy" compressors may obscure such details, where a "lossless" compressor preserves the signal exactly as captured.<p>The purpose of this thesis is to develop a platform upon which a Holter Monitor can be built, including a hardware-assisted lossless compression method in order to avoid the signal quality penalties of a lossy algorithm. <p>The objective of this thesis is to develop and implement a low-complexity lossless ECG encoding algorithm capable of at least a 2:1 compression ratio in an embedded system for use in a Holter Monitor. <p>Different lossless compression techniques were evaluated in terms of coding efficiency as well as suitability for ECG waveform application, random access within the signal and complexity of the decoding operation. For the reduction of the physical circuit size, a System On a Programmable Chip (SOPC) design was utilized. <p>A coder based on a library of linear predictors and Rice coding was chosen and found to give a compression ratio of at least 2:1 and as high as 3:1 on real-world signals tested while having a low decoder complexity and fast random access to arbitrary parts of the signal. In the hardware-assisted implementation, the speed of encoding was a factor of between four and five faster than a software encoder running on the same CPU while allowing the CPU to perform other tasks during the encoding process.

The Internet has profoundly changed todays human being life. A variety of information and online services are offered by various companies and organizations via the Internet. Although these services have substantially improved the quality of life, at the same time they have brought new challenges and difficulties. The information security can be easily tampered by many threats from attackers for different purposes. A catastrophe event can happen when a computer or a computer network is exposed to the Internet without any security protection and an attacker can compromise the computer or the network resources for destructive intention.<p> The security issues can be mitigated by setting up a firewall between the inside network and the outside world. A firewall is a software or hardware network device used to enforce the security policy to the inbound and outbound network traffic, either installed on a single host or a network gateway. A packet filtering firewall controls the header field in each network data packet based on its configuration and permits or denies the data passing thorough the network.<p> The objective of this thesis is to design a highly customizable hardware packet filtering firewall to be embedded on a network gateway. This firewall has the ability to process the data packets based on: source and destination TCP/UDP port number, source and destination IP address range, source MAC address and combination of source IP address and destination port number. It is capable of accepting configuration changes in real time. An Altera FPGA platform has been used for implementing and evaluating the network firewall.

Corrugated steel pipe (CSP) culverts are widely used as an economical alternative for conveying streams and small rivers through road embankments. While passage of the design flow is generally the primary goal for culvert design, consideration must also be given to maintaining connectivity within the aquatic environment for fish and other aquatic organisms. In Canada, the design criteria for fish passage through culverts are generally specified in terms of a maximum mean flow velocity corresponding to the weakest swimming fish expected to be found at a specific location. Studies have shown, however, that the velocity distribution within a CSP culvert may provide sufficient areas of lower velocity flow near the culvert boundary to allow for fish passage, even when the mean flow velocity may exceed a fishs swimming ability. Improved knowledge of the hydraulic conditions within CSP culverts, combined with research into fish swimming capabilities and preferences, may make it possible to better tailor culvert designs for fish passage while at the same time decreasing construction costs. To meet the requirements of regulators, various measures may be taken to reduce culvert flow velocities. Embedding, or setting the invert of a culvert below the normal stream bed elevation, is a simple and inexpensive method of increasing the flow area in a culvert flowing partially full, thereby decreasing flow velocity. Fish traversing through an embedded culvert benefit not only in terms of lower mean flow velocities, but also even lower flow velocities in the near boundary region. In the province of Saskatchewan culvert embedment is regularly used as a means to improve fish passage conditions. In this study, a laboratory scale model was used to study the velocity distribution within a non-embedded and embedded CSP culvert. An acoustic Doppler velocimeter was used to measure point velocities throughout the flow cross section at several longitudinal locations along the culvert. The hydraulic conditions were varied by changing the discharge, culvert slope and depth of embedment. The point velocity data were analyzed to determine patterns of velocity and turbulence intensity at each cross section, as well as along the length of the culvert. The results from the embedded culvert tests were compared with the results from the equivalent non-embedded tests, so that initial conclusions could be made regarding the use of embedment to improve conditions for fish passage. Analysis of the cross section velocity distributions showed that, even the non-embedded culvert had a significant portion of the flow area with flow velocity less than the mean velocity. The results from the embedded tests confirmed that embedding the culvert reduced the flow velocity throughout each cross section, although the effect was most significant for the cross sections located greater than one culvert diameter downstream from the inlet. This variation in effectiveness of embedment at reducing flow velocities is attributed to the length of the M1 backwater profile relative to the culvert length, and thus the differential increase in flow depth that occurred at each measurement location along the culvert. For both the non-embedded and embedded culvert the peak point magnitudes of turbulence intensity were found to be located near the culvert inlet where the flow was contracting. In terms of the cross section average turbulence intensity, in the non-embedded culvert turbulence increased with distance downstream from the inlet and was highest at the cross sections located near the culvert outlet. Embedding the culvert was found to either have no impact, or to slightly increase, the cross section average turbulence intensity near the inlet. Again, a result that is attributed to the tapering out of the M1 backwater profile at locations near the inlet under the flow conditions tested. However, beyond eight culvert diameters downstream from the inlet, embedment did result in lower cross section average turbulence intensity when compared to the non-embedded culvert. The measured velocity profiles for the non-embedded tests were found to compare well to the theoretical log-law velocity distribution using a ks value of between 0.012 m and 0.022 m, or approximately one to two times the corrugation amplitude, when the datum for analysis was considered to be located at the crest of the pipe corrugation. The cross section velocity distributions for the non-embedded tests compared very well to the model proposed by Ead et al. (2000). Based on this assessment, it appears that the Ead et al. model is potentially suitable for use in predicting the amount of the cross sectional area in a non-embedded culvert with flow velocity less than the design target for culvert fish passage design purposes. Overall, the results of the study confirm that, embedding a CSP culvert may be an effective way to improve fish passage conditions in terms of both flow velocity and turbulence intensity.

Multiple trends in computer architecture are beginning to collide as process technology reaches ever smaller feature sizes. Problems with managing power, access times across a die, and increasing complexity to sustain growth are now blocking commercial products like the Pentium 4. These problems also occur in the embedded system space, albeit in a slightly different form. However, as process technology marches on, today's high-performance space is becoming tomorrow's embedded space. New techniques are needed to overcome these problems. In this thesis, we propose a novel architecture called SoftCache to address these emerging issues for embedded systems. We reduce the on-die memory controller infrastructure which reduces both power and space requirements, using the ubiquitous network device arena as a proving ground of viability. In addition, the SoftCache achieves further power and area savings by converting on-die cache structures into directly addressable SRAM and reducing or eliminating the external DRAM. To avoid the burden of programming complexity this approach presents to the application developer, we provide a transparent client-server dynamic binary translation system that runs arbitrary ELF executables on a stripped-down embedded target. One drawback to such a scheme lies in the overhead of additional instructions required to effect cache behavior, particularly with respect to data caching. Another drawback is the power use when fetching from remote memory over the network. The SoftCache comprises a dynamic client-server translation system on simplified hardware, targeted at Intel XScale client devices controlled from servers over the network. Reliance upon a network server as a ``backing store' introduces new levels of complexity, yet also allows for more efficient use of local space. The explicitly software managed aspects create a cache of variable line size, full associativity, and high flexibility. This thesis explores these particular issues, while approaching everything from the perspective of feasibility and actual architectural changes.

In a typical printed circuit board assembly, over 70 percent of the electronic components are passives such as resistors, inductors, and capacitors, and these passives could take up to 50 percent of the entire printed circuit board area. By embedding the passive components within the substrate instead of being mounted on the surface, the embedded passives could reduce the system real estate, eliminate the need for surface-mounted discrete components, eliminate lead based interconnects, enhance electrical performance and reliability, and potentially reduce the overall cost. Even with these advantages, embedded passive technology, especially for organic substrates, is at an early stage of development, and thus a comprehensive experimental and theoretical modeling study is needed to understand the fabrication and reliability of embedded passives before they can be widely used. This thesis aims to fabricate embedded passives in a multilayered organic substrate, perform extensive electrical and mechanical reliability tests, and develop physics-based models to predict the thermo-mechanical reliability of embedded capacitors. Embedded capacitors and resistors with different geometric shapes, planar dimensions, and thus different electrical characteristics have been fabricated on two different test vehicles. Capacitors are made with polymer/ceramic nanocomposite materials and have a capacitance in the range of 50 pF to 1.5 nF. Resistors are carbon ink based Polymer Thick Film (PTF) and NiCrAlSi and have a resistance in the range of 25 to 400 k. High frequency measurements have been done using Vector Network Analyzer (VNA) with 2 port signal-ground (S-G) probes. Accelerated thermal cycling (-55 to 125oC) and constant temperature and humidity tests (85oC/85RH) based on JEDEC and MIL standards have been performed. Furthermore, physics-based numerical models have been developed and validated using the experimental data. By focusing on the design and fabrication as well as the experimental and theoretical reliability assessments, this thesis aims to contribute to the overall development of embedded passive technology for Digital and Radio Frequency (RF) applications.

Miniaturization of electronic products due to the current trend in the electronics industry has led to the integration of components within the chip and package. Traditionally, individual decoupling capacitors placed on the surface of the board or the package have been used to decouple active switching circuits. However, with an increase in the clock rates and its harmonics with technology nodes, decoupling has to be provided in the GHz range. Discrete decoupling capacitors are no longer effective in this region because of the increased inductive effects of the current paths of the capacitors, which limits its effectiveness in the tens of MHz range. The use of embedded individual thick film capacitors within the package is a feasible solution for decoupling core logic above 100 MHz. They overcome the limitations of SMDs (Surface Mount Discretes), primarily in decoupling active circuits in the mid-frequency band. Inclusion of embedded planar capacitors in the board stack up have shown improvements in the overall impedance profile and have shown to exhibit better noise performance. The main contributor to the superior performance is the reduced inductive effects of the power-ground planes because of the thinner dielectrics of the embedded capacitor. The modeling, measurement and characterization of embedded decoupling capacitors in the design of PDNs (Power Distribution Networks) has been investigated in this thesis.