No description available.

[pt] Síntese de Sistemas Fuzzy por Computação Evolucionária propõe uma metodologia de projeto para o desenvolvimento de sistemas fuzzy fundamentada em técnicas de computação evolucionária. Esta metodologia contempla as etapas de concepção do sistema fuzzy e a implementação em hardware do circuito eletrônico que o representa. A concepção do sistema é realizada num ambiente de projeto no qual sua base de conhecimento - composta da base de regras e demais parâmetros característicos - é evoluída, por intermédio de simulação, através do emprego de um novo algoritmo de três estágios que utiliza Algoritmos Genéticos. Esta estratégia enfatiza a interpretabilidade e torna a criação do sistema fuzzy mais simples e eficiente para o projetista, especialmente quando comparada com o tradicional ajuste por tentativa e erro. A implementação em hardware do circuito é realizada em plataforma de desenvolvimento baseada em Eletrônica Evolucionária. Um conjunto de circuitos, denominados de blocos funcionais, foi desenvolvido e evoluído com sucesso para viabilizar a construção da estrutura final do sistema fuzzy. / [en] Synthesis of Fuzzy Systems through Evolutionary Computation proposes a methodology for the design of fuzzy systems based on evolutionary computation techniques. A three-stage evolutionary algorithm that uses Genetic Algorithms (GAs) evolves the knowledge base of a fuzzy system - rule base and parameters. The evolutionary aspect makes the design simpler and more efficient, especially when compared with traditional trial and error methods. The method emphasizes interpretability so that the resulting strategy is clearly stated. An Evolvable Hardware (EHW) platform for the synthesis of analog electronic circuits is proposed. This platform, which can be used for the implementation of the designed fuzzy system, is based on a Field Programmable Analog Array (FPAA). A set of evolved circuits called functional blocks allows the implementation of the fuzzy system.

This thesis describes creation of dynamically evolvable node, which will cooperate with other nodes. Group of these nodes will then create a distributed control system. The MQTT protocol is used for communications purposes between individual nodes. As hardware platform is used ESP32 and ESP8266. Whole operating system is written in MicroPython and supports a live uploading of user applications written in the same language. Later in thesis is decribed creation of monitoring node on Raspberry Pi, which control network. Complete system can be then used to control a intelligent house.

Master thesis is focused on classification of application protocols based on application data taken from layer L7 of ISO/OSI model. The aim of the thesis is to suggest a classifier for SDM system (Software defined monitoring) so it could be used for links with throughput up to 100 Gb/s. At the same time it should classify with the fewest possible errors.Designed classifier consists of two parts. First part depicts encoders for encoding selected attributes. Second part deals with evaluating circuit which detects series characteristic for particular application protocols on the output from the first part. Considered attributes and series are taken from statistic analyzes of application protocol data.The classifier itself is designed so it can be implemented in FPGA and enables modification set of application protocols who intended for classification. The quality of  designed classifier is tested on real network data. The results of classification are compared with current methods used for classification of application protocols.

Dynamicity and unpredictability related to markets is strongly hardening companies’ mission to follow them and satisfy customer needs mainly due to the lack of adequate engineering mechanisms. These effects are felt more intensively in markets where low volumes and high customisation are needed since this requires constant changes in systems that can range from simple setups to total line re-configuration and re-programing. State of the Art Industrial technology has historically been driven to achieve very efficient and flexible production lines for pre-thought problems; however this technology doesn’t satisfy the needs faced by current production requirements where adaptability and responsiveness are off the essence. The last decade witnessed the advent of Evolvable Production Systems (EPS) and other modern paradigms that offer promising approaches to substitute obsolete production strategies. EPS enhances system re-configurability using process-oriented modularity and multi-agent based distributed control endowing the system with units that are autonomous, self-organizing and functionality-oriented. The aggregation of these independent units will then form a system that with a well-defined system architecture and interactions rules can collaborate to complete production plans and react to unpredictable events without re-programing needs. The complexity associated with combinatorial possibilities of forming a system based in such premises raises the need to study how such system performance can be evaluated and how machine learning can be used to discover best system configurations for specific cases. This thesis goal is to enlighten the relation between EPS characteristics, Evaluation and Learning building the foundations for the achievement of Evaluation and Learning mechanisms that can contribute to better system design and configuration to improve system performance and autonomy, and contribute to a more economical solution. / <p>QC 20121218</p>

Rapid advances in integration technology have tremendously increased the design complexity of very large scale integrated (VLSI) circuits, necessitating robust optimization techniques in many stages of VLSI design. A genetic algorithm (GA) is a stochastic optimization technique that uses principles derived from the evolutionary process in nature. In this work, genetic algorithms are used to alleviate the hardware design process of VLSI application specific integrated circuits (ASICs) and reconfigurable hardware. VLSI ASIC design suffers from high design complexity and a large number of optimization objectives requiring hierarchical design approaches and multi-objective optimization techniques. The floorplanning stage of the design cycle becomes highly important in hierarchical design methods. In this work, a multi-objective genetic algorithm based floorplanner has been developed with novel crossover operators to address the multi-objective floorplanning problem for VLSI ASICs. The genetic floorplanner achieves significant wirelength savings (>19% on average) with little or no increase in area ( < 3% penalty) over previous floorplanners that perform simultaneous area and wirelength minimization. Hardware implementation of genetic algorithms is gaining importance because of their proven effectiveness as optimization engines for real-time applications. Earlier hardware implementations suffer from major drawbacks such as absence of GA parameter programmability, rigid pre-defined system architecture, and lack of support for multiple fitness functions. A compact IP core that implements a general purpose GA engine has been designed to realize evolvable hardware in field programmable gate array devices. The designed GA core achieved a speedup of around 5.16x over an analogous software implementation. Novel reconfigurable analog architectures have been proposed to realize extreme environment analog electronics. In this work, a digital framework has been developed to realize self reconfigurable analog arrays (SRAA) where genetic algorithms are used to evolve the required analog functionality and compensate performance degradation in extreme environments. The framework supports two methods of compensation, namely, model based lookup and genetic algorithm based compensation and is scalable in terms of the number of fitness evaluation modules. The entire framework has been implemented as a digital ASIC in a leading industrystrength silicon-on-insulator (SOI) technology to obtain high performance and a small form factor.

Intrinsic evolution of reconfigurable hardware is sought to solve computational problems using the intrinsic processing behavior of System-on-Chip (SoC) platforms. SoC devices combine capabilities of analog and digital embedded components within a reconfigurable fabric under software control. A new technique is developed for these fabrics that leverages the digital resources' enhanced accuracy and signal refinement capability to improve circuit performance of the analog resources' which are providing low power processing and high computation rates. In particular, Differential Digital Correction (DDC) is developed utilizing an error metric computed from the evolved analog circuit to reconfigure the digital fabric thereby enhancing precision of analog computations. The approach developed herein, Cascaded Digital Refinement (CaDR), explores a multi-level strategy of utilizing DDC for refining intrinsic evolution of analog computational circuits to construct building blocks, known as Constituent Functional Blocks (CFBs). The CFBs are developed in a cascaded sequence followed by digital evolution of higher-level control of these CFBs to build the final solution for the larger circuit at-hand. One such platform, Cypress PSoC-5LP was utilized to realize solutions to ordinary differential equations by first evolving various powers of the independent variable followed by that of their combinations to emulate mathematical series-based solutions for the desired range of values. This is shown to enhance accuracy and precision while incurring lower computational energy and time overheads. The fitness function for each CFB being evolved is different from the fitness function that is defined for the overall problem.

Orientador: Suely Cunha Amaro Mantovani / Banca: José Raimundo de Oliveira / Banca: Nobuo Oki / Resumo: Neste trabalho descreve-se uma metodologia para síntese e otimização de circuitos digitais, usando a teoria de algoritmos evolutivos e como plataforma os dispositivos reconfiguráveis, denominada Hardware Evolutivo do inglês- Evolvable Hardware - EHW. O EHW, tornou-se viável com o desenvolvimento em grande escala dos dispositivos reconfiguráveis, Programmable Logic Devices (PLD’s), cuja arquitetura e função podem ser determinadas por programação. Cada circuito pode ser representado como um indivíduo em um processo evolucionário, evoluindo-o através de operações genéticas para um resultado desejado. Como algoritmo evolutivo, aplicou-se o Algoritmo Genético (AG), uma das técnicas da computação evolutiva que utiliza os conceitos da genética e seleção natural. O processo de síntese aplicado neste trabalho, inicia por uma descrição do comportamento do circuito, através de uma tabela verdade para circuitos combinacionais e a tabela de estados para os circuitos seqüenciais. A técnica aplicada busca o arranjo correto e minimizado do circuito que desempenhe uma função proposta. Com base nesta metodologia, são implementados alguns exemplos em duas diferentes representações (mapas de fusíveis e matriz de portas lógicas). / Abstract: In this work was described a methodology for optimization and synthesis of digital circuits, which consist of evolving circuits through evolvable algorithms using as platforms reconfigurable devices, denominated Evolvable Hardware (EHW). It was became viable with the large scale development of reconfigurable devices, whose architecture and function can be determined by programming. Each circuit can be represented as an individual within an evolutionary process, evolving through genetic operations to desire results. Genetic Algorithm (GA) was applied as evolutionary algorithm where this technique evolvable computation as concepts of genetics and natural selection. The synthesis process applied in this work starts from a description from the circuits behavior. Trust table for combinatorial circuits and state transition table for sequential circuits were used for synthesis process. This technic applied search the correct arrange and minimized circuit which response the propose function. Based on this methodology, some examples are implemented in two different representations (fuse maps and logic gate matrices). / Mestre

[pt] Elementos sensores baseados no efeito GMI são uma nova família de sensores magnéticos que apresentam grande quando submetidos a campos magnéticos externos. Estes sensores têm sido utilizados no desenvolvimento de magnetômetros de alta sensibilidade, destinados à medição de campos ultra fracos. Por sua vez, a sensibilidade de um magnetômetro está diretamente associada à sensibilidade de seus elementos sensores. No caso de amostras GMI, esta sensibilidade é otimizada buscando-se a maximização da variação do módulo ou da fase da impedância em função do campo magnético ao qual a amostra é submetida. Estudos recentes mostram que transdutores GMI baseados na variação de fase podem exibir sensibilidades até 100 vezes superiores às apresentadas por transdutores baseados na leitura do módulo do elemento sensor, o que fez com que os trabalhos conduzidos nesta dissertação focassem na maximização da sensibilidade de fase, a qual é majoritariamente dependente de quatro fatores: o comprimento da amostra, o campo magnético externo, o nível DC e a frequência da corrente de excitação. Contudo, a busca do conjunto de parâmetros que otimiza a sensibilidade das amostras é geralmente empírica e muito demorada. Esta dissertação propõe uma nova técnica de otimização da sensibilidade, baseada no uso de algoritmos genéticos evoluindo em hardware, a fim de se definir qual o conjunto de parâmetros responsável pela maximização da sensibilidade das amostras. Ressalta-se que, além dos parâmetros de otimização anteriormente explicitados, também foram realizados testes considerando a amplitude da corrente de excitação como uma variável livre, sendo que os resultados obtidos são apresentados e discutidos. Foi implementada uma bancada de testes e desenvolvida uma interface gráfica em LabVIEW, para monitorar e medir o comportamento da impedância de amostras GMI em função de variações nos parâmetros de interesse. Por sua vez, implementou-se um módulo de otimização em Matlab, baseado em algoritmos genéticos, responsável por encontrar a combinação de parâmetros que maximiza a sensibilidade dos sensores GMI avaliados (ponto ótimo de operação). / [en] GMI sensors are a new family of magnetic sensors that exhibit a huge variation of their impedance when subjected to external magnetic fields. These sensors have been used in the development of high sensitivity magnetometers, aimed at measuring ultra-weak magnetic fields. In turn, the sensitivity of a magnetometer is directly associated with the sensitivity of their sensor elements. In the case of GMI samples, this sensitivity is optimized by maximizing the variation of the impedance magnitude or phase as a function of the magnetic field applied to the sample. Recent studies show that GMI transducers based on phase variation can exhibit sensitivities up to 100 times higher than those presented by transducers based on impedance magnitude readings. The results obtained in these previous studies made the current work focusing on the maximization of phase sensitivity, which is mostly dependent on four factors: sample length, external magnetic field, DC level and frequency of the excitation current. However, the search for the set of parameters that optimizes the sensitivity of the samples is usually empirical and very time consuming. Thus, this dissertation proposes a new optimization technique, based on the use of genetic algorithms evolving on hardware, in order to define which set of parameters is responsible for maximizing the sensitivity of the samples. It should be noted that in addition to the optimization parameters previously described, this work also carried out tests considering the amplitude of the excitation current as a free variable, and the results obtained are presented and discussed. A test bench was implemented and a graphical interface was developed in LabVIEW to monitor and measure the impedance behavior of GMI samples due to variations in the parameters of interest. In turn, a Matlab optimization module based on genetic algorithms was implemented, in order to find the combination of parameters that maximizes the impedance phase sensitivity of the evaluated GMI sensors (optimum operating point).

Made available in DSpace on 2014-06-11T19:22:35Z (GMT). No. of bitstreams: 0 Previous issue date: 2007-05-25Bitstream added on 2014-06-13T20:49:18Z : No. of bitstreams: 1 goulartsobrinho_ef_me_ilha.pdf: 944900 bytes, checksum: 47dc5d964428b7cb8bd18e1e00e1d994 (MD5) / Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES) / Neste trabalho descreve-se uma metodologia para síntese e otimização de circuitos digitais, usando a teoria de algoritmos evolutivos e como plataforma os dispositivos reconfiguráveis, denominada Hardware Evolutivo do inglês- Evolvable Hardware - EHW. O EHW, tornou-se viável com o desenvolvimento em grande escala dos dispositivos reconfiguráveis, Programmable Logic Devices (PLD s), cuja arquitetura e função podem ser determinadas por programação. Cada circuito pode ser representado como um indivíduo em um processo evolucionário, evoluindo-o através de operações genéticas para um resultado desejado. Como algoritmo evolutivo, aplicou-se o Algoritmo Genético (AG), uma das técnicas da computação evolutiva que utiliza os conceitos da genética e seleção natural. O processo de síntese aplicado neste trabalho, inicia por uma descrição do comportamento do circuito, através de uma tabela verdade para circuitos combinacionais e a tabela de estados para os circuitos seqüenciais. A técnica aplicada busca o arranjo correto e minimizado do circuito que desempenhe uma função proposta. Com base nesta metodologia, são implementados alguns exemplos em duas diferentes representações (mapas de fusíveis e matriz de portas lógicas). / In this work was described a methodology for optimization and synthesis of digital circuits, which consist of evolving circuits through evolvable algorithms using as platforms reconfigurable devices, denominated Evolvable Hardware (EHW). It was became viable with the large scale development of reconfigurable devices, whose architecture and function can be determined by programming. Each circuit can be represented as an individual within an evolutionary process, evolving through genetic operations to desire results. Genetic Algorithm (GA) was applied as evolutionary algorithm where this technique evolvable computation as concepts of genetics and natural selection. The synthesis process applied in this work starts from a description from the circuits behavior. Trust table for combinatorial circuits and state transition table for sequential circuits were used for synthesis process. This technic applied search the correct arrange and minimized circuit which response the propose function. Based on this methodology, some examples are implemented in two different representations (fuse maps and logic gate matrices).