This work addresses neural and analog computation on reconfigurable mixed-signal platforms. Many engineered systems could gain tremendous benefits by emulating neural systems. For example, neural systems are incredibly power efficient and fault-tolerant. They are also capable of types of computation that we cannot yet match with conventional computers. Neuromorphic engineers typically implement neural computation using analog circuits because they are low-power and naturally model some aspects of neurobiology. One problem with analog circuits is that they are typically inflexible. To address this shortcoming, our lab has developed reconfigurable analog systems known as Field Programmable Analog Arrays (FPAAs). This dissertation consists of two main parts. The first is the implementation of neural and analog circuits on FPAAs. We first implemented an adaptive winner-take-all circuit, which could model attention in neural systems. Next, we modeled the dendrite, which is the conductive tissue that relays inputs from synapses to the neuron cell body. We also implemented a subtractive music synthesizer, perhaps providing the electronic music synthesis community with a good platform for experimentation. Finally, we conducted a number of neural learning experiments on a neuromorphic platform. The second part of this dissertation includes design aspects of new FPAAs, including configurable blocks that can be used as current-mode DACs in a digitally-enhanced FPAA, the RASP 2.9v. We also consider the design of a new neuromorphic platform containing 256 neurons and over 200,000 synapses, many with learning capability. We also created an active delay line that could be used for beamforming or FIR filter applications. In summary, this work adds to the field of reconfigurable systems by both showing how to implement circuits with them and creating new systems based on lessons learned while working with previous systems.

No description available.

The purpose of this research is to create a solid framework for embedded system design with field-programmable analog arrays (FPAAs). To achieve this goal, we've created a unified approach to the three phases of FPAA system design: (1) the hardware architecture; (2) the circuit design and modeling; and (3) the high-level software tools. First, we describe innovations to the reconfigurable analog hardware that enable advanced signal processing and integration into embedded systems. We introduce the multiple-input translinear element (MITE) FPAA and the dynamically-reconfigurable RASP 2.9v FPAA, which was designed explicitly for interfacing with external digital systems. This compatibility creates a streamlined workflow for dropping the FPAA hardware into mixed-signal embedded systems. The second phase, algorithm analysis and modeling, is important to create a useful and reliable library of components for the system designer. We discuss the concept and procedure of analog abstraction that empowers non-circuit design engineers to take full advantage of analog techniques. We use the analog vector-matrix multiplier as an example for a detailed discussion on computational analog analysis and system mapping to the FPAA. Lastly, we describe high-level software tools, which are an absolute necessity for the design of large systems due to the size and complexity of modern FPAAs. We describe the Sim2Spice tool, which allows system designers to develop signal processing systems in the Simulink environment. The tool then compiles the system to the FPAA hardware. By coordinating the development of these three phases, we've created a solid unified framework that empowers engineers to utilize FPAAs.

While the development of reconfigurable analog platforms is a blossoming field, the tradeoff between usability and flexibility continues to be a major barrier. Field Programmable Analog Arrays (FPAAs) built with translinear elements offer a promising solution to this problem. These FPAAs can be built to use previously developed synthesis procedures for translinear circuits. Furthermore, large-scale translinear FPAAs can be built using floating-gate transistors as both the computational elements and the reconfigurable interconnect network. Two FPAAs, built using Multiple Input Translinear Elements (MITEs), have been designed, fabricated, and tested. These devices have been programmed to implement various circuits including multipliers, squaring circuits, current splitters, and filters. In addition, synthesis, place-and-route, and programming tools have been created in order to implement a reconfigurable system where the circuits implemented are described only by equations. Supporting circuitry for interfacing with current-mode, translinear FPAAs has also been developed. This circuitry included a voltage-to-current converter, a current-to-voltage converter, and a pipelined analog-to-digital converter. The continued development of translinear FPAAs will lead to a reconfigurable analog system that allows for a large portion of the design to be abstracted away from the user.

Orientador: Marconi Kolm Madrid / Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação / Made available in DSpace on 2018-08-10T17:06:39Z (GMT). No. of bitstreams: 1 Fazanaro_FilipeIeda_M.pdf: 19685014 bytes, checksum: ee8bcce451b826c1bc278cf9a7e3d214 (MD5) Previous issue date: 2007 / Resumo: Este trabalho teve como principal objetivo estudar a tecnologia baseada em dispositivos Field Programmable Analog Arrays (FPAAs) e identificar os benef'icios quanto ao seu uso em aplicações de identificação de fenômenos inerentes aos sistemas dinâmicos não-lineares, tais como bifurcações e caos. Esses dispositivos permitem que diferentes tipos de circuitos possam ser implementados sem a necessidade de alteração da topologia do circuito, ou seja, existe a possibilidade de que os sistemas possam ser reconfigurados em tempo de execução à medida que novas alterações sejam necessárias. Com base na Teoria do Caos e na Teoria de Sistemas de Controle, foi implementado o sistema conhecido como Circuito de Chua, que serviu para demonstrar os ganhos que se podem obter com o uso da abordagem proposta quando aplicada ao estudo de sistemas dinâmicos operando no caos em relação às técnicas consideradas mais convencionais. Resultados obtidos pela análise de séries temporais de sinais adquiridos, comprovam a grande eficiência dessa abordagem quanto ao tempo de desenvolvimento e ao tempo para a obtenção dos resultados em comparação com implementações de modelos dinâmicos bastante conhecidos na literatura em relação às implementações dos mesmos em computadores / Abstract: This work had as main objective to study the technology based on Field Programmable Analog Arrays (FPAAs) devices and to identify the benefits to use these devices in applications of identification of inherent phenomena to the nonlinear dynamic systems as bifurcations and chaos. These devices allow that different types of circuits can be implemented without the necessity of alteration of the topology of the circuit, that is, the systems implemented in the FPAA can be reconfigured in execution when new alterations are necessary. On the basis of the Chaos Theory and in the Control Systems Theory, was implemented the system known as Chua¿s Circuit which served to demonstrate the profits that can be gotten with the use of the boarding proposal when applied to the study of dynamic systems operating in chaos in relation to the considered techniques conventional. Gotten results, for the analysis of time series of acquired signals, prove the great efficiency of this boarding in the time of development and the time for obtain the results when comparing implementations of dynamic models sufficiently known in literature in relation with the implementations of the same ones in digital computers / Mestrado / Automação / Mestre em Engenharia Elétrica

Field-programmable analog arrays (FPAAs) provide a method for rapidly prototyping analog systems. Currently available commercial and academic FPAAs are typically based on operational amplifiers (or other similar analog primitives) with only a few computational elements per chip. While their specific architectures vary, their small sizes and often restrictive interconnect designs leave current FPAAs limited in functionality, flexibility, and usefulness. Recent advances in the area of floating-gate transistors have led to an analog technology that is very small, accurately programmable, and extremely low in power consumption. By leveraging the advantages of floating-gate devices, a large-scale FPAA is designed that dramatically advances the current state of the art in terms of size, functionality, and flexibility. A large-scale FPAA is used as part of a mixed-signal prototyping platform to demonstrate the viability and benefits of cooperative analog/digital signal processing. This work serves as a roadmap for future FPAA research. While current FPAAs can be compared with the small, relatively limited, digital, programmable logic devices (PLDs) of the 1970s and 1980s, the floating-gate FPAAs introduced here are the first step in enabling FPAAs to support large-scale, full-system prototyping of analog designs similar to modern FPGAs.

This work is a first step towards a long-term goal of understanding computations occurring in the brain and using those principles to make more efficient machines. The traditional computing paradigm calls for using digital supercomputers to simulate large scale brain-like neural networks resulting in large power consumption which limits scalability or model detail. For example, IBM's digital simulation of a cat brain with simplistic neurons and synapses consumes power equivalent to that of a thousand houses! Instead of digital methods, this work uses analog processing concepts to develop scalable, low-power silicon models of neurons which have been shown to be around ten thousand times more power efficient. This has been achieved by modeling the dynamical behavior of Hodgkin-Huxley (H-H) or Morris-Lecar type equations instead of modeling the exact equations themselves. In particular, the two silicon neuron designs described exhibit a Hopf and a saddle-node bifurcation. Conditions for the bifurcations allow the identification of correct biasing regimes for the neurons. Also, since the hardware neurons compute in real time, they can be used for dynamic clamp protocols in addition to computational experiments. To empower this analog implementation with the flexibility of a digital simulation, a family of field programmable analog array (FPAA) architectures have been developed in 0.35 um CMOS that provide reconfigurability in the network of neurons as well as tunability of individual neuron parameters. This programmability is obtained using floating-gate (FG) transistors. The neurons are organized in blocks called computational analog blocks (CAB) which are embedded in a programmable switch matrix. An unique feature of the architecture is that the switches, being FG elements, can be used also for computation leading to more than 50,000 analog parameters in 9 sq. mm. Several neural systems including central pattern generators and coincidence detectors are demonstrated. Also, a separate chip that is capable of implementing signal processing algorithms has been designed by modifying the CAB elements to include transconductors, multipliers etc. Several systems including an AM demodulator and a speech processor are presented. An important contribution of this work is developing an architecture for programming the FG elements over a wide dynamic range of currents. An adaptive logarithmic transimpedance amplifier is used for this purpose. This design provides a general solution for wide dynamic range current measurement with a low power dissipation and has been used in imaging chips too. A new generation of integrated circuits have also been designed that are 25 sq. mm in area and contain several new features including adaptive synapses and support for smart sensors. These designs and the previous ones should allow prototyping and rapid development of several neurally inspired systems and pave the path for the design of larger and more complex brain like adaptive neural networks.

The Cooperative Analog/Digital Signal Processing (CADSP) research group's approach to signal processing is to see what opportunities lie in adjusting the line between what is traditionally computed in digital and what can be done in analog. By allowing more computation to be done in analog, we can take advantage of its low power, continuous domain operation, and parallel capabilities. One setback keeping Analog Signal Processing (ASP) from achieving more wide-spread use, however, is its lack of programmability. The design cycle for a typical analog system often involves several iterations of the fabrication step, which is labor intensive, time consuming, and expensive. These costs in both time and money reduce the likelihood that engineers will consider an analog solution. With CADSP's development of a reconfigurable analog platform, a Field-Programmable Analog Array (FPAA), it has become much more practical for systems to incorporate processing in the analog domain. In this Thesis, I present an entire chain of tools that allow one to design simply at the system block level and then compile that design onto analog hardware. This tool chain uses the Simulink design environment and a custom library of blocks to create analog systems. I also present several of these ASP blocks, covering a broad range of functions from matrix computation to interfacing. In addition to these tools and blocks, the most recent FPAA architectures are discussed. These include the latest RASP general-purpose FPAAs as well as an adapted version geared toward high-speed applications.

Neste trabalho o teste de dispositivos analógicos programáveis é abordado. Diversas metodologias de teste analógico existentes são estudadas e algumas delas são utilizadas nas estratégias desenvolvidas. Dois FPAAs (Field Programmable Analog Arrays) comerciais de fabricantes e modelos distintos são utilizados para validar as estratégias de teste propostas. O primeiro dispositivo estudado é um FPAA de tempo contínuo (capaz de implementar circuitos contínuos no tempo) da Lattice Semiconductors. Tal dispositivo é marcado pela característica estrutural de sua programabilidade. Por esta razão, a estratégia a ele aplicada é baseada em um método de teste também estrutural, conhecido como OBT (Oscillation-Based Test). Neste método o circuito é dividido em blocos simples que são transformados em osciladores. Os parâmetros do sinal obtido, tais como a freqüência de oscilação e a amplitude, têm relação direta com os componentes utilizados na implementação do oscilador. Desta maneira, é possível detectar falhas no FPAA observando os parâmetros do sinal gerado. Esta estratégia é estudada inicialmente considerando uma análise externa dos parâmetros do sinal. Como uma alternativa de redução de custos e melhoria na cobertura de falhas, um analisador de resposta baseado em um duplo integrador é adotado, permitindo que a avaliação do sinal gerado pelo oscilador seja feita internamente, utilizando-se os recursos programáveis do próprio FPAA. Os resultados obtidos para as análises interna e externa são então comparados. O segundo FPAA estudado, da Anadigm Company, é um dispositivo a capacitores chaveados que tem como característica a programabilidade funcional. Por esta razão o desenvolvimento de uma técnica de teste estrutural é dificultado, pois não se conhece detalhes da arquitetura do componente. Por esta razão, uma técnica de teste funcional, conhecida como Transient Response Analysis Method, é aplicada ao teste deste FPAA. Neste método o circuito sob teste é dividido em blocos funcionais de primeira e segunda ordem e a resposta transiente destes blocos para um dado estímulo de entrada é analisada. O bloco sob teste é então duplicado e um esquema de auto-teste integrado baseado em redundância é desenvolvido, com o intuito de se obter um sinal de erro. Este sinal de erro representa a diferença das respostas transientes dos blocos duplicados. Como proposta para se aumentar a observabilidade do sinal de erro o mesmo é integrado ao longo tempo, aumentando a capacidade de detecção de falhas quando utilizado este método. Em ambas estratégias o objetivo principal do trabalho é testar os blocos analógicos programáveis dos FPAAs explorando ao máximo a programabilidade dos dispositivos e utilizando recursos pré-existentes para auxiliar no teste. Os resultados obtidos mostram que as estratégias desenvolvidas configuram boas alternativas para o auto-teste integrado deste tipo de componente. / This work addresses the test of programmable analog devices. Several analog test methodologies are studied and some of them are applied in the developed strategies. In order to validate these strategies, two commercial FPAAs (Field Programmable Analog Arrays), of different vendors and distinct models, are considered as devices under test. The first studied device is a continuous-time FPAA from Lattice Semiconductors. One important characteristic of such device is the structural programmability. For this reason the test strategy applied to this FPAA is based in a structural method known as OBT (Oscillation-Based Test). In this method, blocks of the circuit under test are individually converted into oscillators. The parameters of the generated signal, such as the frequency and amplitude, can be expressed as function of the components used in the oscillator implementation. This way, it is possible to detect faults in the FPAA simply observing such parameters. This method is firstly studied considering an external analysis of the signal parameters. However, in a second moment, an internal response analyzer, based on a double integrator, is built with the available programmable resources of the FPAA. This way, overall test cost is reduced, while the fault coverage is increased with no area overhead. The obtained results considering the external analysis and the built-in response evaluation are compared. The second considered FPAA, from Anadigm Company, is a switched capacitor device whose programming characteristic is strictly functional. Thus, a structural test method cannot be easily developed and applied without the previous knowledge of he device architectural details. For this reason, a functional test method known as TRAM (Transient Response Analysis Method) is adopted. In this method the Circuit Under Test (CUT) is programmed to implement first and second order blocks and the transient response of these blocks for a given input stimuli is analyzed. Taking advantage of the inherent programmability of the FPAAs, a BIST-based scheme is used in order to obtain an error signal representing the difference between the fault-free and faulty Configurable Analog Blocks (CABs). As a proposal to augmenting the observability, the error signal is integrated, enhancing de fault detection capability when using this method. In both developed strategies the main objective is to test the CABs of the FPAAs exploiting the device programmability, using the existing resources in order to aid the test. The obtained results show that the developed strategies represent good alternatives to the built-in self-test of such type of device.

Neste trabalho o teste de dispositivos analógicos programáveis é abordado. Diversas metodologias de teste analógico existentes são estudadas e algumas delas são utilizadas nas estratégias desenvolvidas. Dois FPAAs (Field Programmable Analog Arrays) comerciais de fabricantes e modelos distintos são utilizados para validar as estratégias de teste propostas. O primeiro dispositivo estudado é um FPAA de tempo contínuo (capaz de implementar circuitos contínuos no tempo) da Lattice Semiconductors. Tal dispositivo é marcado pela característica estrutural de sua programabilidade. Por esta razão, a estratégia a ele aplicada é baseada em um método de teste também estrutural, conhecido como OBT (Oscillation-Based Test). Neste método o circuito é dividido em blocos simples que são transformados em osciladores. Os parâmetros do sinal obtido, tais como a freqüência de oscilação e a amplitude, têm relação direta com os componentes utilizados na implementação do oscilador. Desta maneira, é possível detectar falhas no FPAA observando os parâmetros do sinal gerado. Esta estratégia é estudada inicialmente considerando uma análise externa dos parâmetros do sinal. Como uma alternativa de redução de custos e melhoria na cobertura de falhas, um analisador de resposta baseado em um duplo integrador é adotado, permitindo que a avaliação do sinal gerado pelo oscilador seja feita internamente, utilizando-se os recursos programáveis do próprio FPAA. Os resultados obtidos para as análises interna e externa são então comparados. O segundo FPAA estudado, da Anadigm Company, é um dispositivo a capacitores chaveados que tem como característica a programabilidade funcional. Por esta razão o desenvolvimento de uma técnica de teste estrutural é dificultado, pois não se conhece detalhes da arquitetura do componente. Por esta razão, uma técnica de teste funcional, conhecida como Transient Response Analysis Method, é aplicada ao teste deste FPAA. Neste método o circuito sob teste é dividido em blocos funcionais de primeira e segunda ordem e a resposta transiente destes blocos para um dado estímulo de entrada é analisada. O bloco sob teste é então duplicado e um esquema de auto-teste integrado baseado em redundância é desenvolvido, com o intuito de se obter um sinal de erro. Este sinal de erro representa a diferença das respostas transientes dos blocos duplicados. Como proposta para se aumentar a observabilidade do sinal de erro o mesmo é integrado ao longo tempo, aumentando a capacidade de detecção de falhas quando utilizado este método. Em ambas estratégias o objetivo principal do trabalho é testar os blocos analógicos programáveis dos FPAAs explorando ao máximo a programabilidade dos dispositivos e utilizando recursos pré-existentes para auxiliar no teste. Os resultados obtidos mostram que as estratégias desenvolvidas configuram boas alternativas para o auto-teste integrado deste tipo de componente. / This work addresses the test of programmable analog devices. Several analog test methodologies are studied and some of them are applied in the developed strategies. In order to validate these strategies, two commercial FPAAs (Field Programmable Analog Arrays), of different vendors and distinct models, are considered as devices under test. The first studied device is a continuous-time FPAA from Lattice Semiconductors. One important characteristic of such device is the structural programmability. For this reason the test strategy applied to this FPAA is based in a structural method known as OBT (Oscillation-Based Test). In this method, blocks of the circuit under test are individually converted into oscillators. The parameters of the generated signal, such as the frequency and amplitude, can be expressed as function of the components used in the oscillator implementation. This way, it is possible to detect faults in the FPAA simply observing such parameters. This method is firstly studied considering an external analysis of the signal parameters. However, in a second moment, an internal response analyzer, based on a double integrator, is built with the available programmable resources of the FPAA. This way, overall test cost is reduced, while the fault coverage is increased with no area overhead. The obtained results considering the external analysis and the built-in response evaluation are compared. The second considered FPAA, from Anadigm Company, is a switched capacitor device whose programming characteristic is strictly functional. Thus, a structural test method cannot be easily developed and applied without the previous knowledge of he device architectural details. For this reason, a functional test method known as TRAM (Transient Response Analysis Method) is adopted. In this method the Circuit Under Test (CUT) is programmed to implement first and second order blocks and the transient response of these blocks for a given input stimuli is analyzed. Taking advantage of the inherent programmability of the FPAAs, a BIST-based scheme is used in order to obtain an error signal representing the difference between the fault-free and faulty Configurable Analog Blocks (CABs). As a proposal to augmenting the observability, the error signal is integrated, enhancing de fault detection capability when using this method. In both developed strategies the main objective is to test the CABs of the FPAAs exploiting the device programmability, using the existing resources in order to aid the test. The obtained results show that the developed strategies represent good alternatives to the built-in self-test of such type of device.