International Telemetering Conference Proceedings / October 30-November 02, 1995 / Riviera Hotel, Las Vegas, Nevada / The Central Control Unit (CCU) for a decentralised on-board base-band telemetry system is designed for use in launch vehicle missions of the Indian Space Research Organisation (ISRO). This new design is a highly improved and miniaturised version of an earlier design. The major design highlights are as follows: usage of CMOS Field Programmable Gate Array (FPGA) devices in place of LS TTL devices, high level user programmability of TM format using EEPROMs, usage of high density memory for on-board data storage and delayed data transmission, HMC based pre-modulation filter and final output driver etc. The entire system is realised on a single 6 layer MLB and is packaged on a stackable modular frame. This design has resulted in a 1:4 reduction in weight, 1:4 reduction in volume, 1:5 reduction in power consumption and 1:3 reduction in height in addition to drastic reduction of part diversity and solder joints and thus greatly increased reliability. This paper discusses the design approach, implementation details, tools used, simulations carried out and the results of detailed qualification tests done on the realised qualification model.

Outer space is a very harsh environment that can cause electronics to not operate as they were originally intended. Aside from the extreme amount of radiation found in space, temperatures can also change very dramatically in a relatively small time frame. In order to test electronics that will be used in this environment, they first need to be tested on Earth under replicated conditions. Vanderbilt University designed a dewar that allows devices to be tested at these extreme temperatures while being radiated. For this thesis, a test setup that met all of the dewar's constraints was designed that would allow a 12-bit, 16-channel analog-to-digital converter to be tested while inside.

Outer space is a very harsh environment that can cause electronics to not operate as they were originally intended. Aside from the extreme amount of radiation found in space, temperatures can also change very dramatically in a relatively small time frame. In order to test electronics that will be used in this environment, they first need to be tested on Earth under replicated conditions. Vanderbilt University designed a dewar that allows devices to be tested at these extreme temperatures while being radiated. For this thesis, a test setup that met all of the dewar's constraints was designed that would allow a 12-bit, 16-channel analog-to-digital converter to be tested while inside.

Σε μία εποχή όπου η ψηφιοποίηση δεδομένων έχει αυξηθεί ραγδαία η ανάγκη για τη βέλτιστη μετάδοσή τους είναι απαραίτητη. Από τα πλέον σημαντικά μέρη των προτύπων μετάδοσης είναι η κωδικοποίηση του καναλιού μέσω ειδικών αλγορίθμων ώστε να επιτευχθεί η εύρεση και διόρθωση τυχών λαθών. Οι κώδικες Bose, Chaudhuri και Hocquenghem (BCH) είναι τέτοιου είδους κώδικες που χρησιμοποιούνται ευρέως σε εφαρμογές όπως τα CD, DVD, σκληροί δίσκοι, δίσκοι στερεάς κατάστασης (SSD) και το πρότυπο δορυφορικής μετάδοσης τηλεόρασης υψηλής ανάλυσης (HDTV), DVB-S2. Στην παρούσα διπλωματική εργασία σχεδιάστηκε και υλοποιήθηκε κωδικοποιητής και αποκωδικοποιητής BCH για τις 11 περιπτώσεις κανονικού πλαισίου που προσφέρει το πρότυπο DVB-S2. Κύριος στόχος ήταν η όσο το δυνατόν καλύτερη υλοποίηση με γνώμονα το μέγεθος, με τη χρήση κοινών κυκλωμάτων και για τις 11 περιπτώσεις. Αποτέλεσμα αυτής της βελτιστοποίησης μεγέθους, ήταν κάποιες τεχνικές βελτιστοποίησης της ταχύτητας αποκωδικοποίησης, όπως το shortening, να μη χρησιμοποιηθούν καθώς θα είχαν ως αποτέλεσμα την αύξηση της επιφάνειας μερών του αποκωδικοποιητή κατά περίπου 11 φορές. Καθώς σκοπός της διπλωματικής ήταν η μελέτη της απόδοσης των κωδίκων BCH, μελετήθηκε ο ρυθμός λαθών σε διάφορες τιμές της αναλογίας ενέργειας – θορύβου (Eb / N0 ), αφού πρώτα υλοποιήθηκε σε FPGA. / The amount of digital information is growing rapidly the recent decades, making transmission optimization one of the top priorities in digital information systems. One of the main parts of every transmission standard is channel encoding, with the use of algorithms aimed at finding and correcting errors (Forward Error Correction – FEC). Such codes are Bose, Chaudhuri and Hocquenghem (BCH) code, which are widely used in applications like CDs, DVDs, Hard Drives, Solid State Drives (SSDs) and DVB-S2, a satellite transmission standard mostly used for High Definition Television (HDTV). This thesis sets out to account for the design and implementation of a BCH encoder and decoder for all 11 different code rates proposed by the DVB-S2 standard for normal frames. The design was area optimized in order for all 11 code rate encoders and decoders to work on the same FPGA. This lead to some optimization techniques being unused. Even though the codes are shortened, no shortening algorithms which aim at clock cycle optimization were used. Were they used, would lead parts of the decoder to be almost 11 times larger. The main goal of the thesis is to analyze the performance of the codes, so the error rate was measured under different values of the energy to noise ratio (Eb/ N0 ).

Distributed generation that utilizes 5-10kW Solid Oxide Fuel Cells requires power electronics to optimize the overall system efficiency while reducing the cost. The Adaptive Energy Zero-Voltage-Switching Phase-Shift-Modulated Full-Bridge (AE-ZVS-PSM-FB) topology meets these criteria under all loading conditions, but suffers from complexity associated with an analog control implementation. This thesis presents a novel Look-Up-Table (LUT) based digital controller required for such converter. The applied design approach also reduces the design time and controller requirements, which in turn decreases the overall system cost. Steady-state analysis for the AE-ZVS-PSM-FB converter is performed using a piece-wise equivalent circuit model. This analysis is used to verify the LUT concept that forms the basis for the proposed LUT-based digital controller. The proposed LUT-based digital control algorithm is developed and verified using Field Programmable Gate Array (FPGA) Logic platform. Design procedures and operational function under steady state and step change conditions are presented. Simulation results demonstrate the LUT concept in the AE-ZVS-PSM-FB converter, and the simplicity of the proposed LUT-based digital controller in producing the expected switching sequence. Simulation results were also produced showing successful dynamic response of LUT-based digital controller interconnected with the converter under different operating conditions. A Xilinx FPGA demonstration board was used to generate experimental switching sequence results to demonstrate the simplicity of the proposed controller. / Thesis (Master, Electrical & Computer Engineering) -- Queen's University, 2007-09-25 10:26:39.909

The high-radiation environment in space can lead to anomalies in normal satellite operation. A major cause of concern to spacecraft-designers is the single event upset (SEU). SEUs can result in deviations from expected component behavior and are capable of causing irreversible damage to hardware. In particular, Field Programmable Gate Arrays (FPGAs) are known to be highly susceptible to SEUs. Radiation-hardened versions of such devices are associated with an increase in power consumption and cost in addition to being technologically inferior when compared to contemporary commercial-off-the-shelf (COTS) parts. This thesis consequently aims at exploring the option of using COTS FPGAs in satellite payloads. A framework is developed, allowing the SEU susceptibility of such a device to be studied. SEU testing is carried out in a software-simulated fault environment using a set of Java classes called JBits. A radiation detector module, to measure the radiation backdrop of the device, is also envisioned as part of the final design implementation.

Στόχος της παρούσας Διπλωματικής Εργασίας είναι ο σχεδιασμός και υλοποίηση ενός Κρυπτογραφικού Συστήματος με βάση τον Αλγόριθμο κατακερματισμού JH. Ο σχεδιασμός του κρυπτογραφικού αυτού συστήματος έγινε με τη χρήση γλώσσας VHDL (Very High Speed Integrated Circuits hardware description language) και στη συνέχεια η υλοποίηση αυτή έγινε πάνω σε πλατφόρμα FPGA (Field Programmable Gate Array). Ο αλγόριθμος JH είναι ένας αλγόριθμος κατακερματισμού (hash function) ο οποίος σχεδιάστηκε στα πλαίσια του διαγωνισμου κρυπτογραφιας NIST (National Institute of Standards and Technology). Η πρώτη του έκδοση έγινε στις 31 Οκτωβρίου 2008 ενώ η τελική του έκδοση έγινε στις 16 Ιανουαρίου 2011. Ο Αλγόριθμος JH έχει τρεις υποκατηγορίες. Υπάρχει ο JH-224, JH-256, JH-384 και ο JH-512. Βασικό χαρακτηριστικό του αλγορίθμου αυτού είναι το γεγονός πώς οι λειτουργίες που συμβαίνουν σε κάθε γύρο είναι ίδιες. Επίσης σημαντικό γνώρισμα ειναι η ασφάλεια που παρέχει ο αλγόριθμος αυτός καθώς ο μεγάλος αριθμός των ενεργών S-boxes που χρησιμοποιούνται και ταυτόχρονα το γεγονός ότι σε κάθε γύρο χρησιμοποιείται ένα διαφορετικό κλειδι το οποίο παράγεται εκεινη τη στιγμή και δεν ειναι αποθηκευμένο σε ένα σημείο, στο οποίο θα μπορούσε κάποιος να επέμβει, κάνει το σύστημά μας εξαιρετικά δυνατό και ανθεκτικό απέναντι σε επιθέσεις όπως είναι η διαφορική κρυπτανάλυση. Για την εξακρίβωση της ορθής λειτουργίας του συστήματος χρησιμοποιήθηκε μία υλοποίηση του Αλγορίθμου JH σε γλώσσα C. Χρησιμοποιώντας την υλοποίηση αυτή κάθε φορά που θέλουμε να κρυπτογραφήσουμε ένα μήνυμα το οποίο είναι μία σειρά από bit, λαμβάνουμε το κρυπτογραφημένο μήνυμα. Αυτο το κρυπτογραφημένο μήνυμα το συγκρίνουμε με αυτό που παίρνουμε στην έξοδο του συστήματος JH που σχεδιάσαμε και με αυτό το τρόπο επιβεβαιώνουμε την ορθότητα του αποτελέσματος. Ύστερα από την non-pipelined υλοποίηση του συστήματος αυτού, χρησιμοποιήθηκε η τεχνική της συσωλήνωσης (pipeline). Πιο συγκεκριμένα εγιναν 4 διαφορετικές pipelined υλοποιήσεις με 2,3,6 και 7 στάδια. Σκοπός είναι για κάθε μία pipelined υλοποίηση να γίνει έλεγχος σε θέματα απόδοσης, κατανάλωσης ισχύος καθώς επίσης και σε θέματα επιφάνειας. Στη συνέχεια γίνεται μία σύγκριση στα προαναφερθέντα θέματα μεταξύ των διαφορετικών pipelined υλοποιήσεων και με την non-pipelined υλοποίηση του κρυπτογραφικού συστήματος JH. Επίσης αξίζει να σημειωθεί πώς γίνεται ιδιαίτερη αναφορά στο throughput και στο throughput per area των pipelined υλοποιήσεων. Από τα πειραματικά αποτελέσματα που προέκυψαν η JH NON PIPELINED υλοποίηση έχει απόδοση 97 MHz με κατανάλωση ισχύος 137mW και συνολική επιφάνεια 2284 slices σε SPARTAN 3E FPGA συσκευή. Ενώ από την ανάλυση της JH NON PIPELINED υλοποίησης και των 4 pipelined υλοποιήσεων σε 4 διαφορετικά FPGA (2 της οικογένειας SPARTAN και 2 της οικογένειας VIRTEX) συμπεραίνουμε πώς στην οικογένεια VIRTEX η κατανάλωση ισχύος είναι πάντα μεγαλύτερη σε σχεση με την οικογένεια SPARTAN. / The purpose of this Thesis Project is the design and implementation of a Cryptographic System using the JH Hash Algorithm. The design of this Cryptographic System was performed using the VHDL language (Very High Speed Integrated Circuits hardware description language) and then this implementation was executed on a FPGA platform (Field Programmable Gate Array).The JH Algorithm is a hash algorithm that was developed during the NIST (National Institute of Standards and Technology) Cryptography Competition. Its first version was released on 31 October 2008 while its last version was released on 16 January 2011. The JH Hash Algorithm has three subcategories. There is JH-224, JH-256, JH-384, and JH-512. Basic characteristic of this Algorithm is the fact that the functions that are executed in each round are identical. Moreover important characteristic is the security that this Algorithm provides us while the big number of active S-Boxes that is used and in the same time the fact that in each round a different key is produced on the fly, and is not stored in a place that a third person could have access, makes our system really strong and resistant to attacks such as the differential attack. To confirm the right functionality of the system the implementation of the JH Algorithm in C Language is used. Using this implementation each time we want to cipher a message, which is a sequence of bits, we get the message digest. This message digest is compared with the message digest that we get from the JH system that we developed with VHDL and in this way we confirm the correctness of the result. After the non pipelined implementation of the JH system the pipeline technique was used. To be more specific 4 different pipelined implementations with 2, 3, 6 and 7 stages were performed. The target was to check the performance, area and power dissipation for each pipelined implementation. Next a comparison was performed between the various pipelined implementations and the non pipelined implementation for the above mentioned issues. In addition to this it is worth to mention that considerable reference is made for throughput and throughput per area for the pipelined implementations. According to the experimental results the JH NON PIPELINED implementation has a performance of 97 MHz, with power dissipation of 137mW and a total area of 2284 Slices on SPARTAN 3E FPGA device. From the JH NON PIPELINED implementation and the other 4 pipelined implementations on 4 different FPGA Devices (2 from the VIRTEX family and 2 from the SPARTAN family) we concluded that the power dissipation is bigger in VIRTEX family devices in comparison to SPARTAN family Devices.

Οι κρυπτογραφικές συναρτήσεις κατακερματισμού αποτελούν στις μέρες μας ένα από τα δημοφιλέστερα συστατικά των κρυπτογραφικών συστημάτων, λόγω των ιδιαίτερων ιδιοτήτων τους. Λαμβάνοντας υπόψη τη συνεχή αύξηση του όγκου δεδομένων και των ταχυτήτων επικοινωνίας, η χρήση μιας συνάρτησης κατακερματισμού με χαμηλή ρυθμοαπόδοση μπορεί να επιβραδύνει το συνολικό ψηφιακό τηλεπικοινωνιακό σύστημα. Ο σχεδιασμός ενός δεδομένου αλγορίθμου κατακερματισμού ώστε να έχει τη βέλτιστη ρυθμοαπόδοση αποτελεί ζήτημα μεγάλης σημασίας. Στη συγκεκριμένη διπλωματική εργασία παρουσιάζεται μια μεθοδολογία σχεδιασμού με στόχο τη βέλτιστη ρυθμοαπόδοση κρυπτογραφικών αλγορίθμων που βασίζονται σε συγκεκριμένη επαναληπτική μορφή. Για το σκοπό αυτό αναπτύχθηκε ένα λογισμικό, που συνδυάζει δύο τεχνικές, τον επαναχρονισμό και την ξεδίπλωση, παράγοντας το βέλτιστο σχεδιαστικό αποτέλεσμα. Η μεθοδολογία εφαρμόστηκε σε δύο δημοφιλείς συναρτήσεις κατακερματισμού, τις SHA-1 και SHA-256. Οι μετασχηματισμένοι αλγόριθμοι συνθέθηκαν και υλοποιήθηκαν σε FPGA, επιβεβαιώνοντας την αποτελεσματικότητα της μεθόδου. / Nowadays, cryptographic hash functions are one of the most popular primitive components in the cryptographic systems, due to their key features. Considering that data sizes and communication speeds are increasing every year, the use of a hash algorithm with low throughput can be a bottle neck in the digital communication system. Designing a given hash algorithm to be throughput optimum is a critical issue. In this diploma thesis a design methodology is presented which oprimizes the throughput of cryptographic hash functions that rely on a specific iterative structure. For this purpose, a software was designed combining two techniques, retiming and unfolding, that generates the optimal throughput design. The methodology was applied to two popular hash algorithms, SHA-1 and SHA-256. The transformed algorithms were synthesized and implemented in a FPGA device, confirming its effectiveness.

As we can find through the development of TV systems in America, the digital TV related digital broadcasting is just the road we would walk into. Nowadays digital television is prevailing in China, and the government is promoting the popularity of digital television. However, because of the economic development, analog television will still take its place in the TV market during a long period. But the broadcasting system has not been reformed, as a result, we should not only take use of the traditional analog system we already have, but also improve the quality of the pictures of analog system. With the high-speed development of high-end television, the research and application of digital television technique, the flaws caused by interlaced scan in traditional analog television, such as color-crawling, flicker and fast-moved object's boundary blur and zigzag, are more and more obvious. Therefore the conversion of interlaced scan to progressing scan, which is de-interlacing, is an important part of current television production. At present there are many kinds of TV sets appearing in the market. They are based on digital processing technology and use various digital methods to process the interlaced, low-field rate video data, including the de-interlacing and field rate conversion. The digital process chip of television is the heart of the new-fashioned TV set, and is the reason of visual quality improvement. As a requirement of real time television signal processing, most of these chips has developed novel hardware architecture or data processing algorithm. So far, the most quality effective algorithm is based on motion compensation, in which motion detection and motion estimation will be inevitably involved, in despite of the high computation cost. in video processing chips, the performance and complexity of motion estimation algorithm have a direct impact on speed area and power consumption of chips. Also, motion estimation determined the efficiency of the coding algorithms in video compression. This thesis proposes a Down-sampled Diamond NTSS algorithm (DSD-NTSS) based on New Three Step Search (NTSS) algorithm, taking both performance and complexity of motion estimation algorithms into consideration. The proposed DSD-NTSS algorithm makes use of the similarity of neighboring pixels in the same image and down-samples pixels in the reference blocks with the decussate pattern to reduce the computation cost. Experiment results show that DSD-NTSS is a better tradeoff in the terms of performance and complexity. The proposed DSD-NTSS reduces the computation cost by half compared with NTSS when having the equivalent image quality. Further compared with Four Step Search(FSS) Diamond Search(DS)、Three Step Search(TSS) and some other fast searching algorithms, the proposed DSD-NTSS generally surpasses in performance and complexity. This thesis focuses on a novel computation-release motion estimation algorithm in video post-processing system and researches the FPGA design of the system.

Weather monitoring and forecasting systems have witnessed rapid advancement in recent years. However, one of the main challenges faced by these systems is poor coverage in lower atmospheric regions due to earth's curvature. The Engineering Research Center for the Collaborative Adaptive Sensing of the Atmosphere (CASA) has developed a dense network of small low-power radars to improve the coverage of weather sensing systems. Traditional, mechanically-scanned antennas used in these radars are now being replaced with high-performance electronically-scanned phased-arrays. Phased-Array radars, however, require large number of active microwave components to scan electronically in both the azimuth and elevation planes, thus significantly increasing the cost of the entire radar system. To address this issue, CASA has designed a "Phase-Tilt" radar, that scans electronically in azimuth and mechanically in elevation. One of the core components of this system is the Phased-Array controller or the Array Formatter. The Array Formatter is a Field Programmable Gate Array (FPGA)-based master controller that translates user commands from a computer to control and timing signals for the radar system. The objective of this thesis is to design and test an FPGA-based Array Formatter for CASA's Phase-Tilt radar system.