A large amount of the information in conversations come from non-verbal cues such as facial expressions and body gesture. These cues are lost when we don't communicate face-to-face. But face-to-face communication doesn't have to happen in person. With video communication we can at least deliver information about the facial mimic and some gestures. This thesis is about video communication over distances; communication that can be available over networks with low capacity since the bitrate needed for video communication is low. A visual image needs to have high quality and resolution to be semantically meaningful for communication. To deliver such video over networks require that the video is compressed. The standard way to compress video images, used by H.264 and MPEG-4, is to divide the image into blocks and represent each block with mathematical waveforms; usually frequency features. These mathematical waveforms are quite good at representing any kind of video since they do not resemble anything; they are just frequency features. But since they are completely arbitrary they cannot compress video enough to enable use over networks with limited capacity, such as GSM and GPRS. Another issue is that such codecs have a high complexity because of the redundancy removal with positional shift of the blocks. High complexity and bitrate means that a device has to consume a large amount of energy for encoding, decoding and transmission of such video; with energy being a very important factor for battery-driven devices. Drawbacks of standard video coding mean that it isn't possible to deliver video anywhere and anytime when it is compressed with such codecs. To resolve these issues we have developed a totally new type of video coding. Instead of using mathematical waveforms for representation we use faces to represent faces. This makes the compression much more efficient than if waveforms are used even though the faces are person-dependent. By building a model of the changes in the face, the facial mimic, this model can be used to encode the images. The model consists of representative facial images and we use a powerful mathematical tool to extract this model; namely principal component analysis (PCA). This coding has very low complexity since encoding and decoding only consist of multiplication operations. The faces are treated as single encoding entities and all operations are performed on full images; no block processing is needed. These features mean that PCA coding can deliver high quality video at very low bitrates with low complexity for encoding and decoding. With the use of asymmetrical PCA (aPCA) it is possible to use only semantically important areas for encoding while decoding full frames or a different part of the frames. We show that a codec based on PCA can compress facial video to a bitrate below 5 kbps and still provide high quality. This bitrate can be delivered on a GSM network. We also show the possibility of extending PCA coding to encoding of high definition video.

Most computing and communicating devices have been personal computers that were connected to Internet through a fixed network connection. It is believed that future communication devices will not be of this type. Instead the intelligence and communication capability will move into various objects that surround us. This is often referred to as the "Internet of Things" or "Wireless Embedded Internet". This thesis deals with video processing and communication in these types of systems. One application scenario that is dealt with in this thesis is real-time video transmission over wireless ad-hoc networks. Here a set of devices automatically form a network and start to communicate without the need for any previous infrastructure. These devices act as both hosts and routers and can build up large networks where they forward information for each other. We have identified two major problems when sending real-time video over wireless ad-hoc networks. One is the reactive design used by most ad-hoc routing protocols. When nodes move some links that are used in the communication path between the sender and the receiver may disappear. The reactive routing protocols wait until some links on the path breaks and then start to search for a new path. This will lead to long interruptions in packet delivery and does not work well for real-time video transmission. Instead we propose an approach where we identify when a route is about to break and start to search for new routes before this happen. This is called a proactive approach. Another problem is that video codecs are very sensitive for packet losses and at the same time the wireless ad-hoc network is very error prone. The most common way to handle lost packets in video codecs is to periodically insert frames that are not predictively coded. This method periodically corrects errors regardless there has been an error or not. The method we propose is to insert frames that are not predictively coded directly after a packet has been lost, and only if a packet has been lost. Another area that is dealt with in this thesis is video sensor networks. These are small devices that have communication and computational capacity, they are equipped with an image sensor so that they can capture video. Since these devices in general have very limited resources in terms of energy, computation, communication and memory they demand a lot of the video compression algorithms used. In standard video compression algorithms the complexity is high for the encoder while the decoder has low complexity and is just passively controlled by the encoder. We propose video compression algorithms for wireless video sensor networks where complexity is reduced in the encoder by moving some of the image analysis to the decoder side. We have implemented our approach on actual low-power sensor nodes to test our developed algorithms. Finally we have built a "Digital Zoo" that is a complete system including a large scale outdoor video sensor network. The goal is to use the collected data from the video sensor network to create new experiences for physical visitors in the zoo, or "cyber" visitors from home. Here several topics that relate to practical deployments of sensor networks are addressed.

Rapid development in CMOS technology has resulted in its suitability for the implementation of readout front-end systems in terms of high integration density, and low power consumption yet at the same time posing many challenges for analog circuits design like readout front-end. One of the significant challenges is the low noise design for high speed front-end systems, while at the same time minimizing the power consumption as much as possible. A high speed, low noise, low power, and programmable readout front-end system is designed and implemented for an X-ray detector in CMOS 0.18 m technology in this thesis work. The front-end system has a peaking time of 10 ns, which is the highest speed ever reported in the published work. The front-end system is designed to achieve low noise in terms of ENC, and a low power consumption of 2.9 mW. The detector capacitance is the most dominating parameter to low noise, which in turn is directly related to the power consumption. In this thesis work an ENC of 435 electrons is achieved for a detector capacitance of 5 pF and an ENC of 320 electrons for a detector capacitance of 3 pF. Based on the comparison to related published work, a performance improvement of at least two times is achieved taking peaking time, power, ENC, and detector capacitance all into consideration. The output pulse after amplification has peak amplitude of 300 mV for a maximum injected charge of 40000 electrons from the detector. The readout front-end system noise performance is strongly dependent on the input MOSFET type, size, and biasing. In this work a PMOS has been selected and optimized as the input device due to its smaller 1/f noise and high gain as compare to NMOS when biased at same currents. The architecture designed in this work consists of a folded cascode CSA with extra cascode in first stage, a pole-zero cancellation circuit to eliminate undershoot, a shaper amplifier, and integrators using Gm-C filter technique. All of these components are optimized for low power while meeting the noise requirements. The whole front-end system is programmed for peaking times of 10, 20, and 40 ns. The programmability is achieved by switching different capacitors and resistors values for all the poles and zeros in the front-end, and by switching parallel transconductance in the Gm-C filters. Finally fine tuning of all the capacitance, resistance, and transconductance values is done to achieve required performance.

In today’s world the multi-standard wireless receivers are gaining more and more popularity. End-users want to access voice, data and streaming media from a single wireless terminal. An ideal approach for multi-standard receiver front-end is to digitize a wide band RF signal available from the antenna. All radio functions such as downconversion, demodulation and channel selection can be then performed in the digital domain. Analog to Digital Converter in such a case should guarantee very high linearity, speed and bandwidth specifications while consuming a lot of power. Unfortunately an ADC with such stringent requirements cannot be realized in today’s CMOS technology. In a typical receiver a mixer is used to downconvert the RF signal to baseband (or IF) before digitization is performed. A passive mixer is often used in this case to mitigate the effect of the low frequency flicker noise. Specially it can be a sampling mixer which also serves as a S/H circuit usually required for A/D conversion. In this thesis a lowpass sigma-delta converter with RF sampling is presented. The ΣΔ modulator is SC passive circuit plus comparator, so an operational amplifier usually needed to realize the integrator is avoided. To reduce the complexity, the sampling mixer in front of the modulator is merged with the passive loop filter. As a result the sampling mixer is closed in the modulator loop, so the overall linearity of the frontend is improved to some extent. Downconversion is combined with digitization that reduces the circuit complexity as well.The challenges while digitizing high frequency RF signal are discussed in details. Switches required to realize the loop filter are very critical and tend to be nonlinear. Parasitic effects associated with MOS transistors strongly show up at GHz frequencies. Optimized transistor sizes are obtained through simulation while addressing the speed and linearity trade-off. Another major challenge is the kT/C noise that is the real bottleneck in high frequency SC circuit design. A thermal noise model for ΣΔ-modulator with second-order loop filter is presented and it is shown that a passive ΣΔ-modulator is  in fact thermal noise limited rather than quantization noise limited. It is because the capacitor values are limited by the very high sampling frequency used in this case.The downconverting lowpass ΣΔ modulator with second order SC passive loop filter and 1-bit quantizer is simulated at transistor level in 90nm CMOS process. This modulator can operate at very high sampling frequency upto 4GHz and can sample RF signal with carrier of upto 4GHz as well. The designed ΣΔ modulator is flexible and supports sub-sampling by 2 to 8 (fs = 500MHz, ... 2GHz). Besides, the presented design is very power efficient as it does not use OpAmps – which consume most of the power in the typical ΣΔ modulators. From schematic simulation on average, signal-to-noise and distortion ratio (SNDR) of 52 dB is obtained (ENOB = 8.3). SNDR results does not vary much for three different cases of baseband digitalization, RF sampling and RF sub-sampling. This SNDR value seems to be a good number for a passive sigma-delta modulator. The detailed simulation results for the three cases discussed in the thesis work shown that, the modulator performs equally well for a wide range of sampling and RF signal frequencies.

A wave digital filter is derived from an analog filter, which is realized as classical doubly resistively terminated reactancefilters. Perfectly designed wave digital filters express good dynamic signal range, low roundoff noise and excellent stabilitycharacteristics with respect to nonlinearity which are produced due to finite wordlength effects. Wave digital filters inheritthe sensitivity properties from analog filters, therefore, coefficients values can be selected to favorable values.Wave digital filters, derived from ladder filters, have low coefficient sensitivity in the passband and stopband. These WDFsare very complicated and are non-modular. The lattice wave digital filters are modular and are not complex. However, theyhave very high sensitivity in the stopband and thus require large coefficient wordlengths. The number of coefficients equalsthe filter order which have to be odd.This thesis discusses the wave digital filter structures that are modular because they are designed by cascading the first-orderand second-order sections. These WDFs can be pipelined. They also exhibit all the above mentioned favorable properties.Similar to lattice WDFs, these structures are restricted to symmetrical and antisymmetrical transfer functions. The synthesisof these structures is based on the factorization of the scattering matrix of lossless two-ports.In this thesis work, lowpass wave digital filters based on circulator-tree structure are designed with different orders startingfrom 3 and going upto 13. In parallel to these circulator-tree wave digital filters, the simple digital filters are also designedwith the same specification. The results of the two filters are compared with each other. It is observed that impulse responseand attenuation response of the two kind of filters perfectly match. Therefore, it is can be concluded that circulator-tree WDFupto Nth order can be synthesized. The implementation examples of two filter with order 3 and order 7 is presented in thisdocumentation for ready reference. It has also been shown that the order of sections does not affect the transfer function ofthe filter. Noise has been introduced and adaptor sections are penetrated. From the results it is concluded that the order of theadaptor sections does not matter and also that the noise does not affect the other adaptors sections, it only propagates throughother adaptors sections.

Large scale path loss modeling plays a fundamental role in designing both fixed and mobile radio systems. Predicting the radio coverage area of a system is not done in a standard manner. Wireless systems are expensive systems. Therefore, before setting up a system one has to choose a proper method depending on the channel environment, frequency band and the desired radio coverage range. Path loss prediction plays a crucial role in link budget analysis and in the cell coverage prediction of mobile radio systems. Especially in urban areas, increasing numbers of subscribers brings forth the need for more base stations and channels. To obtain high efficiency from the frequency reuse concept in modern cellular systems one has to eliminate the interference at the cell boundaries. Determining the cell size properly is done by using an accurate path loss prediction method. Starting from the radio propagation phenomena and basic path loss models this thesis aims at describing various accurate path loss prediction methods used both in rural and urban environments. The Walfisch-Bertoni and Hata models, which are both used for UHF propagation in urban areas, were chosen for a detailed comparison. The comparison shows that the Walfisch-Bertoni model, which involves more parameters, agrees with the Hata model for the overall path loss.

The goal of the thesis is to design the star-based mesh topology by introducing multiple pan-coordinators (hub/switches) under a multipath-fading environment and to improve the data transaction rate of a network which usually gets worst when there is a single pan-coordinator for synchronization of devices in conventional mesh topology; also reduce the hop-count as least as possible. Most of the work has been done on NS-2 network simulator; therefore the research model which has been used here is a simulation model. Altogether 3 simulations have been done. The first scenario is done on a simplest mesh network with a single coordinator and a radio propagation model which has been used is two-ray ground reflection model. The second scenario simulation is similar to the first scenario but in-order to provide multi-path signal fading and highly congested environment the propagation model which has been used this time is shadowing model. The final simulation which has been done is of multiple-star based mesh topology it also uses the similar radio propagation model which has been defined for second scenario. An intensive performance measurement of all the three simulations has been done in terms of transactions made per-second, packet drop rate along with an analysis of packet drop. An hop-count is also measured between star and mesh topology. For multiple star based mesh topology it can be assumed if multiple stars with a routing capability can be used then nodes in a network will be synchronized or re-synchronized with least number of hops in the congested network with a near-by pan-coordinator (hub/switch). One of the major applications of this topology can be automobile manufacturing industry where alot of machines are installed in a congested network and monitoring of every area is mandatory for swift production.

At Acreo AB located in Norrköping, Sweden, research and development in the field of organic electronics have been conducted since 1998. Several electronic devices and systems have been realized. In late 2003 a commercial printing press was installed to test large scale production of these devices. Prior to the summer of 2005 the project made significant progress. As a step towards industrialisation, the variability and yield of the printing process needed to bee studied. A decision to implement Statistical Process Control (SPC) and Design of Experiments (DOE) to evaluate and improve the process was taken. SPC has been implemented on the EC-patterning step in the process. A total of 26 Samples were taken during the period October-December 2005. An - and s-chart were constructed from these samples. The charts clearly show that the process is not in statistical control. Investigations of what causes the variation in the process have been performed. The following root causes to variation has been found: PEDOT:PSS-substrate sheet resistance and poorly cleaned screen printing drums. After removing points affected by root causes, the process is still not in control. Further investigations are needed to get the process in control. Examples of where to go next is presented in the report. In the DOE part a four factor full factorial experiment was performed. The goal with the experiment was to find how different factors affects switch time and life length of an electrochromic display. The four factors investigated were: Electrolyte, Additive, Web speed and Encapsulation. All statistical analysis was performed using Minitab 14. The analysis of measurements from one day and seven days after printing showed that: - Changing Electrolyte from E230 to E235 has small effect on the switch time - Adding additives Add1 and Add2 decreases the switch time after 1 and 7 days - Increasing web speed decreases the switch time after 1 and 7 days - Encapsulation before UV-step decreases the switch time after 7 days

<p>During the past years has the Nostrum Network on Chip <i>(NoC)</i> been developed to become a competitive platform for network based on-chip communication. The Nostrum NoC provides a versatile communication platform to connect a large number of intellectual properties <i>(IP) </i>on a single chip. The communication is based on a packet switched network which aims for a small physical footprint while still providing a low communication overhead. To reduce the communication network size, a queue-less network has been the research focus. This network uses de ective hot-potato routing which is implemented to perform routing decisions in a single clock cycle.</p><p>Using a platform like this results in increased design reusability, validated signal integrity, and well developed test strategies, in contrast to a fully customised designs which can have a more optimal communication structure but has a significantly longer development cycle to verify the new design accordingly.</p><p>Several factors are considered when designing a communication platform. The goal is to create a platform which provides low communication latency, high throughput, low power consumption, small footprint, and low design, verification, and test overhead. Proximity Congestion Awareness is one technique that serves to reduce</p><p>the network load. This leads to that the latency is reduced which also increases the network throughput. Another technique is to implement low latency paths called<i> Data Motorways</i> achieved through a clocking method called Globally Pseudochronous Locally Synchronous clocking. Furthermore, virtual circuits can be used to provide guarantees on latency and throughput. Such guarantees are dificult in</p><p>hot-potato networks since network access has to be ensured. A technique that implements virtual circuits use looped containers that are circulating on a predefined circuit. Several overlapping virtual circuits are possible by allocating the virtual circuits in different Temporally Disjoint Networks.</p><p>This thesis summarise the impact the presented techniques and methods have on the characteristics on the Nostrum model. It is possible to reduce the network load by a factor of 20 which reduces the communication latency. This is done by distributing load information between the Switches in the network. Data Motorways</p><p>can reduce the communication latency with up to 50% in heavily loaded networks. Such latency reduction results in freed buffer space in the Switch registers which allows the traffic rate to be increased with about 30%.</p>

<p>Large scale path loss modeling plays a fundamental role in designing both fixed and mobile radio systems. Predicting the radio coverage area of a system is not done in a standard manner. Wireless systems are expensive systems. Therefore, before setting up a system one has to choose a proper method depending on the channel environment, frequency band and the desired radio coverage range. Path loss prediction plays a crucial role in link budget analysis and in the cell coverage prediction of mobile radio systems. Especially in urban areas, increasing numbers of subscribers brings forth the need for more base stations and channels. To obtain high efficiency from the frequency reuse concept in modern cellular systems one has to eliminate the interference at the cell boundaries. Determining the cell size properly is done by using an accurate path loss prediction method. Starting from the radio propagation phenomena and basic path loss models this thesis aims at describing various accurate path loss prediction methods used both in rural and urban environments. The Walfisch-Bertoni and Hata models, which are both used for UHF propagation in urban areas, were chosen for a detailed comparison. The comparison shows that the Walfisch-Bertoni model, which involves more parameters, agrees with the Hata model for the overall path loss.</p>