The thesis is composed of two topics: a power-saving DRAMs with an adaptive refreshing clock generator, and a high precision low dropout regulator with nested feedback loops. In the first topic, an adaptive refreshing circuitry design for DRAMs is presented in this work. The proposed refreshing circuitry utilizes a voltage comparator to monitor the voltage drop caused by the data loss of a memory cell resulted from leakage currents to dynamically adjust the refreshing period of DRAM cells. A process variation monitor is also included in the proposed design to compensate the process drifting problem. Therefore, the proposed design is insensitive to temperature variations as well as process drifts. The period of the refreshing clock is automatically adjusted to save a great portion of standby power of DRAMs. A 4-Kb DRAM is implemented using a typical 0.13-£gm 1P8M digital CMOS process. Post-layout simulation results and a prototype on silicon justify the correctness of the adaptive refreshing cycles generated by the proposed design. In the second topic, a high precision low dropout regulator (LDO) with nested feedback loops is proposed in this paper. By nesting a zero-tracking compensation loop inside of the negative feedback loop comprising an Error Amplifier, the independence of off-chip capacitor and ESR is ensured for different load currents and operating voltages. Therefore, in low Iddq or low voltage scenarios, the total error of the output voltage caused by line and load variations is less than ¡Ó3% according to the on-silicon measurement results.

The advancement in integrated circuit (IC) technology has resulted in scaling down of device sizes and supply voltages without proportionally scaling down the threshold voltage of the MOS transistor. This, coupled with the increasing demand for low power, portable, battery-operated electronic devices, like mobile phones, and laptops provides the impetus for further research towards achieving higher integration on chip and low power consumption. High gain, wide bandwidth amplifiers driving large capacitive loads serve as error amplifiers in low-voltage low drop out regulators in portable devices. This demands low power, low area, and frequency-compensated multistage amplifiers capable of driving large capacitive loads. The first part of the research proposes two power and area efficient frequency compensation schemes: Single Miller Capacitor Compensation (SMC) and Single Miller Capacitor Feedforward Compensation (SMFFC), for multistage amplifiers driving large capacitive loads. The designs have been implemented in a 0.5??m CMOS process. Experimental results show that the SMC and SMFFC amplifiers achieve gain-bandwidth products of 4.6MHz and 9MHz, respectively, when driving a load of 25Kδ/120pF. Each amplifier operates from a ??1V supply, dissipates less than 0.42mW of power and occupies less than 0.02mm2 of silicon area. The inception of the latest IEEE standard like IEEE 802.16 wireless metropolitan area network (WMAN) for 10 -66 GHz range demands wide band amplifiers operating at high frequencies to serve as front-end circuits (e.g. low noise amplifier) in such receiver architectures. Devices used in cascade (multistage amplifiers) can be used to increase the gain but it is achieved at an expense of bandwidth. Distributing the capacitance associated with the input and the output of the device over a ladder structure (which is periodic), rather than considering it to be lumped can achieve an extension of bandwidth without sacrificing gain. This concept which is also known as distributed amplification has been explored in the second part of the research. This work proposes certain guidelines for the design of distributed low noise amplifiers operating at very high frequencies. Noise analysis of the distributed amplifier with real transmission lines is introduced. The analysis for gain and noise figure is verified with simulation results from a 5-stage distributed amplifier implemented in a 0.18??m CMOS process.

This dissertation presents circuit techniques for designing high performance amplifiers. In low power design, the range of common mode input signal shrinks due to reduced power supply voltage. In addition, due to reduced bias current, noise density rises. The reduced input signal range and raised noise floor severely degrade system dynamic range. A novel rail to rail input circuit is presented. The proposed circuit has advantages over conventional circuits in term of noise and power consumption. Moreover, due to reduced bias current, low power amplifiers typically have lower bandwidth and slew rate, which limits their dynamic performance. The bandwidth is further reduced at high gain settings because of the constant gain bandwidth product. A novel self-adaptive compensation technique to extend small signal bandwidth and improve slew behavior is presented. If an amplifier needs to drive various capacitive and/or resistive loads, parallel Miller compensation is the most power efficient frequency compensation scheme. However, the frequency response of parallel Miller compensation is complicated and no thorough analysis on frequency response has been given in literatures. To illustrate the connection between poles/zeros and each individual circuit component, we use a design oriented approach to derive transfer functions for various load conditions. With these transfer functions, circuit designers can optimize their design accordingly. As a case study, a low power precision instrumentation amplifier is designed. Compared to low power instrumentation amplifiers on the market or reported in literature, it can save at least 40% power, meanwhile offer higher bandwidth and faster slew rate at typical gain settings. Many challenges also exist in designing high voltage amplifiers. To achieve low cost and high performance, a novel topology of a high voltage current sensing amplifier is proposed. With this topology, major portion of amplifiers can be designed with low voltage, for instance, 5 V, devices, and only a limited amount of LDMOS are required to stand off high voltage. This topology does not have high noise gain as conventional solutions have. The same principle can be used for other high voltage amplifiers. A prototype chip is fabricated. The amplifier functions as expected. Test results are presented.

This work deals with a methods for increasing the PSRR of the linear active filters of supply voltage or if linear regulators and voltage range of supply, primarily his minimal value. In the work are used ideal parts of reference voltage source and reference current source. The work describes how to eliminate effect of feedback loop on the PSRR, how to decrrease minimal power supply voltage and how to set stability of total schematic.

Rail à rail entrée - sortie, classe AB, faible consommation sont autant de critères que le concepteur d'amplificateur opérationnel (AOP) intègre pour réaliser une cellule analogique performante. Pour un AOP standard, l'accent n'est pas porté sur une caractéristique particulière mais sur l’ensemble de celle-ci. Dans le but d'augmenter le nombre de fonction par circuit intégré, la tension d'alimentation des AOPs ainsi que leur consommation en courant tendent à diminuer. L'objectif des circuits réalisés est de doubler le facteur de mérite des circuits déjà présents dans le portefeuille de STMicroelectronics. Le facteur de mérite est un indice qui compare des circuits équivalents. Il est défini par le rapport entre le produit capacité de charge x produit gain bande-passante et le produit courant de consommation x tension d'alimentation. L'état de l'art des structures d'AOPs a orienté l'étude vers des structures analogiques possédant au moins trois étages de gain. Un niveau de gain statique supérieur à la centaine de décibel est nécessaire pour utiliser ces amplificateurs dans des systèmes contre-réactionnés. Puisque chaque étage de gain introduit un noeud haute impédance et que chaque noeud haute impédance est à l'origine d'un pôle, l'étude de la compensation fréquentielle s'est avérée indispensable pour obtenir des structures optimisées. Pour simplifier l'étude de ces AOPs, le développement d'outils d'aide à la conception analogique a contribué à l'automatisation de plusieurs tâches.. Ces différents travaux ont été ponctués par la réalisation et la caractérisation de six circuits. Les compensations fréquentielles utilisées dans ces circuits sont la compensation nested miller , la compensation reversed nested miller et la compensation multipath nested miller . Parmi les six circuits, une moitié a été réalisée uniquement dans le but de valider des concepts de compensation fréquentielle et l'autre moitié avec toutes les contraintes d'une documentation technique propre à la famille d'AOP standard. / To be in line with the standard of operational amplifier (opamp), designer integrates in his circuit several functionalities like a Rail to rail input and output, class AB output stage and low power consumption. For standard products, there is no outstanding performance but the average of all of them has to be good. In order to increase the number of functions on an integrated circuit, the power supply and current consumption are permanently decreasing. The aim of the designed circuits is to double the figure of merit (FOM) of the actual ST portfolio products. The FOM allows the comparison of similar opamps. It is defined by the ratio of the product of capacitive load x gain-bandwith product over the power consumption. The opamps’ state of the art has led this study to three stages analog cells. A DC gain higher than hundreds of decibel is required to use opamps in feedback configuration. As each stage of the structure introduces a high impedance node and as each high impedance node introduces a pole, the study of frequency compensation technics became essential for well optimized structures. To simplify the study of the opamps, three tools have been developed to help in the design of the frequency compensation network and to automate some tasks. This work has been followed by the realization of six cells. Three of them were designed to validate frequency compensation structure and the other three to satisfy a standard opamp datasheet. Nested Miller, Reversed Nested Miller and Multipath Nested Miller compensations were used in these circuits.