O advento da utilização de circuitos integrados pela sociedade se deu por dois motivos. O primeiro consiste na miniaturização das dimensões dos dispositivos integrados. Essa miniaturização permitiu a construção de dispositivos menores, mais rápidos e que consomem menos frequência. O outro fator é a utilização da metodologia baseada em biblioteca de células. Esta metodologia permite o projeto de um circuito eficiente em um curto espaço de tempo. Com a redução dos dispositivos, novos fatores que eram desconsiderados no fluxo automático passaram a ter importância. Dentre eles podemos citar o consumo estático, a variabilidade, a manufaturabilidade e o envelhecimento. Alguns desses fatores, como o consumo estático e a variabilidade, já estão integrados à metodologia baseada em biblioteca de células. Os efeitos de envelhecimento tem sua degradação aumentada a cada novo processo tecnológico, assim como tem aumentado também a sua importância em relação à confiabilidade do circuito ao longo da sua vida útil. Este trabalho irá explorar estes efeitos de envelhecimento no projeto de circuitos integrados digitais. Dentre as principais contribuições pode-se destacar a definição de um custo de envelhecimento na definição de portas lógicas, que pode ser explorado pelos algoritmos de síntese lógica para obterem um circuito mais confiável. Este custo também pode ser utilizado pelas ferramentas de análise a fim de obter uma estimativa da degradação que o circuito proposto irá sofrer ao longo da sua vida útil. Além disso, é apresentada uma proposta de reordenamento estrutural do arranjo de transistores em portas lógicas, a fim de tratar os efeitos de envelhecimento nos níveis mais iniciais do fluxo. Por fim, uma análise simplificada de características a serem exploradas ao nível de circuito é discutida utilizando o auxílio do projeto de portas lógicas complexas. Os resultados apresentam uma boa e rápida estimativa da degradação das portas lógicas. A reestruturação do arranjo dos transistores tem se apresentado como uma boa alternativa ao projeto de circuitos mais confiáveis. Além disso, a utilização de arranjos mais complexos também é uma excelente alternativa que explora a robustez intrínseca da associação de transistores em série. Além disso, as alternativas propostas podem ser utilizadas em conjunto com técnicas já existentes na literatura. / The increased presence of integrated circuit (IC) in the people’s life has occurred for main two reasons. The first is the aggressive scaling of integrated device dimensions. This miniaturization enabled the construction of smaller, faster and lower power consumption devices. The other factor is the use of a cell based methodology in IC design. This methodology is able to provide efficient circuits in a short time. With the devices scaling, new factors that were usually ignored in micrometer technologies have become relevant in nanometer designs. Among them, it can be mentioned the static consumption, process parameters variability, manufacturability and aging effects. Some of these factors, such as static consumption and variability, are already taken into account by the standard cell design methodology. On the other hand, the degradation caused by aging effects has increased at each new technology node, as well as the importance in relation to the circuit reliability throughout its entire lifetime has also increased. This thesis explores such aging effects in the design of digital IC. The main contributions can be highlighted as the definition of a cost of aging that can be exploited by logic synthesis algorithms to produce a more reliable circuit. This cost can be also used by the analysis tools in order to obtain an estimative of the degradation that specific circuit experiences throughout their lifetime. In addition, a proposal to reorder the transistor structural arrangement of logic gates is presented in order to treat the effects of aging on initial steps in the design flow. Finally, a simplified analysis of the characteristics to be exploited at circuit level is performed exploring details of the design of complex logic gates. The aging cost results have given a good and fast prediction of logic gates degradation. The transistor arrangement restructuring approach is a good alternative to design more reliable circuits. Furthermore, the use of complex arrangements is also an excellent alternative which exploits the intrinsic robustness of series transistors association. Moreover, the discussed approaches can be easily used together with existing techniques in the literature to achieve better results.

A crescente evolução das tecnologias de fabricação de circuitos integrados demanda o desenvolvimento de novas ferramentas de CAD. O desenvolvimento tradicional de circuitos digitais a nível físico baseia-se em bibliotecas de células. Estas bibliotecas de células oferecem certa previsibilidade do comportamento elétrico do projeto devido à caracterização prévia das células. Além disto,diferentes versões para cada célula são requeridas de forma que características como atraso e consumo sejam atendidos, aumentando o número de células necessárias em uma bilioteca. A geração automática de leiautes é uma alternativa cada vez mais importante para a geracão baseada em células. Este método implementa transistores e conexões de acordo com padrões que são definidos em algoritmos sem as limitações impostas pelo uso de uma biblioteca de células. A previsibilidade em leiautes gerado automaticamente é oferecida por ferramentas de análise e estimativa. Estas ferramentas devem ser aptas a trabalhar com estimativas do leiaute e gerar informações relativas a atraso, potência e área. Este trabalho inclui a pesquisa de novos métodos de síntese física e a implementação de um gerador automático de leiautes cujas células são geradas no momento da síntese do leiaute. A pesquisa investiga diferentes estratégias de disposição dos componentes (transistores, contatos e conexões) em um leiaute e seus efeitos na ocupação de área e no atraso e de um circuito. A estratégia de leiaute utilizada aplica técnicas de otimização de atraso pela integração com uma técnicas de dimensionamento de transistores. Isto é feito de forma que o método de folding permita diferentes dimensionamentos para os transistores. As principais características da estratégia proposta neste trabalho são: linhas de alimentação entre bandas, roteamento sobre o leiaute (não são utilizados canais de roteamento) e geração de leiautes visando a redução do atraso do circuito pela aplicação da técnica de dimensionamento ao leiaute e redução do comprimento médio das conexões. O fato de permitir a implementação de qualquer combinação de equações lógicas, sem as restrições impostas pelo uso de uma biblioteca de células, permite a síntese de circuitos com uma otimização do número de transistores utilizados. Isto contribui para a diminuição de atrasos e do consumo, especialmente do consumo estático em circuitos submicrônicos. Comparações entre a estratégia proposta e outros métodos conhecidos são apresentadas de forma a validar a proposta apresentada. / The evolution of integrated circuits technologies demands the development of new CAD tools. The traditional development of digital circuits at physical level is based in library of cells. These libraries of cells offer certain predictability of the electrical behavior of the design due to the previous characterization of the cells. Besides, different versions of each cell are required in such a way that delay and power consumption characteristics are taken into account, increasing the number of cells in a library. The automatic full custom layout generation is an alternative each time more important to cell based generation approaches. This strategy implements transistors and connections according patterns defined by algorithms. So, it is possible to implement any logic function avoiding the limitations of the library of cells. Tools of analysis and estimate must offer the predictability in automatic full custom layouts. These tools must be able to work with layout estimates and to generate information related to delay, power consumption and area occupation. This work includes the research of new methods of physical synthesis and the implementation of an automatic layout generation in which the cells are generated at the moment of the layout synthesis. The research investigates different strategies of elements disposition (transistors, contacts and connections) in a layout and their effects in the area occupation and circuit delay. The presented layout strategy applies delay optimization by the integration with a gate sizing technique. This is performed in such a way the folding method allows individual discrete sizing to transistors. The main characteristics of the proposed strategy are: power supply lines between rows, over the layout routing (channel routing is not used), circuit routing performed before layout generation and layout generation targeting delay reduction by the application of the sizing technique. The possibility to implement any logic function, without restrictions imposed by a library of cells, allows the circuit synthesis with optimization in the number of the transistors. This reduction in the number of transistors decreases the delay and power consumption, mainly the static power consumption in submicrometer circuits. Comparisons between the proposed strategy and other well-known methods are presented in such a way the proposed method is validated.

O advento da utilização de circuitos integrados pela sociedade se deu por dois motivos. O primeiro consiste na miniaturização das dimensões dos dispositivos integrados. Essa miniaturização permitiu a construção de dispositivos menores, mais rápidos e que consomem menos frequência. O outro fator é a utilização da metodologia baseada em biblioteca de células. Esta metodologia permite o projeto de um circuito eficiente em um curto espaço de tempo. Com a redução dos dispositivos, novos fatores que eram desconsiderados no fluxo automático passaram a ter importância. Dentre eles podemos citar o consumo estático, a variabilidade, a manufaturabilidade e o envelhecimento. Alguns desses fatores, como o consumo estático e a variabilidade, já estão integrados à metodologia baseada em biblioteca de células. Os efeitos de envelhecimento tem sua degradação aumentada a cada novo processo tecnológico, assim como tem aumentado também a sua importância em relação à confiabilidade do circuito ao longo da sua vida útil. Este trabalho irá explorar estes efeitos de envelhecimento no projeto de circuitos integrados digitais. Dentre as principais contribuições pode-se destacar a definição de um custo de envelhecimento na definição de portas lógicas, que pode ser explorado pelos algoritmos de síntese lógica para obterem um circuito mais confiável. Este custo também pode ser utilizado pelas ferramentas de análise a fim de obter uma estimativa da degradação que o circuito proposto irá sofrer ao longo da sua vida útil. Além disso, é apresentada uma proposta de reordenamento estrutural do arranjo de transistores em portas lógicas, a fim de tratar os efeitos de envelhecimento nos níveis mais iniciais do fluxo. Por fim, uma análise simplificada de características a serem exploradas ao nível de circuito é discutida utilizando o auxílio do projeto de portas lógicas complexas. Os resultados apresentam uma boa e rápida estimativa da degradação das portas lógicas. A reestruturação do arranjo dos transistores tem se apresentado como uma boa alternativa ao projeto de circuitos mais confiáveis. Além disso, a utilização de arranjos mais complexos também é uma excelente alternativa que explora a robustez intrínseca da associação de transistores em série. Além disso, as alternativas propostas podem ser utilizadas em conjunto com técnicas já existentes na literatura. / The increased presence of integrated circuit (IC) in the people’s life has occurred for main two reasons. The first is the aggressive scaling of integrated device dimensions. This miniaturization enabled the construction of smaller, faster and lower power consumption devices. The other factor is the use of a cell based methodology in IC design. This methodology is able to provide efficient circuits in a short time. With the devices scaling, new factors that were usually ignored in micrometer technologies have become relevant in nanometer designs. Among them, it can be mentioned the static consumption, process parameters variability, manufacturability and aging effects. Some of these factors, such as static consumption and variability, are already taken into account by the standard cell design methodology. On the other hand, the degradation caused by aging effects has increased at each new technology node, as well as the importance in relation to the circuit reliability throughout its entire lifetime has also increased. This thesis explores such aging effects in the design of digital IC. The main contributions can be highlighted as the definition of a cost of aging that can be exploited by logic synthesis algorithms to produce a more reliable circuit. This cost can be also used by the analysis tools in order to obtain an estimative of the degradation that specific circuit experiences throughout their lifetime. In addition, a proposal to reorder the transistor structural arrangement of logic gates is presented in order to treat the effects of aging on initial steps in the design flow. Finally, a simplified analysis of the characteristics to be exploited at circuit level is performed exploring details of the design of complex logic gates. The aging cost results have given a good and fast prediction of logic gates degradation. The transistor arrangement restructuring approach is a good alternative to design more reliable circuits. Furthermore, the use of complex arrangements is also an excellent alternative which exploits the intrinsic robustness of series transistors association. Moreover, the discussed approaches can be easily used together with existing techniques in the literature to achieve better results.

Conselho Nacional de Desenvolvimento CientÃfico e TecnolÃgico / We investigate the performance of three different non linear directional assymmetrical fibers couplers that include a profile of self-modulation of increasing and decreasing phase. The asymmetry is associated with the profile of self-modulation of phase of one of the chanels. Initially, we investigate the performance of the considered coupler using ultrashort pulses, type sÃliton with 2ps of width and later operating with signal CW. Observing the characteristics of transmission of the device, through the direct chanel and cross chanel, we made a study of the extinction ratio (Xratio) of the devices. The extinction ratio of a switching on-off is the relation among the exit power in the state on and the power of exit in the state off. It was observed that the performance of gates AND, XOR, OR are dependents of the profile of non linearity. In the profile of constant it was not verified that logics AND and XOR present one better performance with the device operating in CW, while logic OR present better with the coupler operating in pulse regime. We conclude that coupler to operate it as logic gate we can control the non-linearity profile to optimize the characteristics of transmission through the extinction ratio. / NÃs investigamos o desempenho de trÃs diferentes acopladores direcionais nÃolineares duplo assimÃtrico que incluem um perfil de auto modulaÃÃo de fase crescente e decrescente. A assimetria està associada ao perfil de auto modulaÃÃo de fase de um dos canais. Inicialmente, investigamos o desempenho do acoplador proposto utilizando pulsos ultracurtos, tipo sÃliton com 2ps de largura e posteriormente operando com sinal CW. Observando as caracterÃsticas de transmissÃo do dispositivo, atravÃs do canal direto e cruzado, fizemos um estudo do coeficiente de extinÃÃo (Xratio) dos dispositivos. O coeficiente de extinÃÃo de um chaveamento on-off à a relaÃÃo entre a potÃncia de saÃda no estado on e a potÃncia de saÃda no estado off . Foi observado que a performance de portas AND, XOR, OR sÃo dependentes do perfil de nÃo linearidade. No perfil de nÃo linearidade constante verificou-se que as lÃgicas AND e XOR apresentam um melhor desempenho com o dispositivo operando em CW, enquanto a lÃgica OR mostra-se melhor com o acoplador operando em regime pulsado. ConcluÃmos que para o acoplador operar como porta lÃgica nÃs podemos controlar o perfil de nÃo linearidade para otimizar as caracterÃsticas de transmissÃo atravÃs do coeficiente de extinÃÃo.

Orientador: Jose Antonio Roversi / Tese (doutorado) - Universidade Estadual de Campinas, Instituto de Fisica Gleb Wataghin / Made available in DSpace on 2018-08-23T20:03:52Z (GMT). No. of bitstreams: 1 Yabu-uti_BrunoFerreiradeCamargo_D.pdf: 3039693 bytes, checksum: f0b083dd372cff54e492778d15824a5b (MD5) Previous issue date: 2013 / Resumo: Na presente tese estudamos o processamento de informação quântica no sistema de átomos e cavidades acopladas. Em particular, a comunicação quântica estabelecida entre átomos remotos e a implementação de portas lógicas no sistema de cavidades acopladas. Iniciamos apresentando o sistema de cavidades acopladas, o Hamiltoniano que governa sua evolução, algumas promissoras implementações experimentais e a transferência de um estado de campo arbitrário de um fóton ao longo da cadeia. Incluindo um sistema massivo, propomos um novo protocolo para uma transferência perfeita, determinística e flexível de estados quânticos entre átomos remotos interagindo sucessivamente com o sistema de cavidades acopladas (atuando como quantum bus). Mesmo levando em conta efeitos dissipativos e erros de procedimento obtivemos uma alta fidelidade máxima de transmissão. Por fim, apresentamos uma proposta alternativa para a implementação de um porta R(rotação)- controlada de dois qubits. A proposta está baseada em operações de um qubit e fase geométrica não-convencional em átomos de três níveis idênticos fortemente bombeados por um campo clássico ressonante em cavidades ópticas distantes conectadas por uma fibra óptica. Nossa proposta resulta em um tempo operacional constante e, com um acoplamento qubit-bus ajustável (atomoressonador), pode-se especificar uma rotação R particular no qubit alvo / Abstract: In this thesis we study the quantum information processing in the system of atom-coupled cavity. In particular, the quantum communication between remote atoms and the implementation of logic gates in the coupled cavities system. We begin by presenting the system of coupled cavities, the Hamiltonian that governs its evolution, some promising experimental implementations and the transfer of an arbitrary one photon field state along the array. Including a massive system, we propose a new protocol for a perfect, deterministic and flexible quantum state transfer between remote atoms interacting successively with the system of coupled cavities (which act as a quantum bus). Even taking into account dissipative effects and error procedure we obtained a maximum high-fidelity transmission. We also present an alternative proposal for the implementation of a controlled-R gate of two qubits. The proposal is based on single qubit operations and unconventional geometric phases on two identical three-level atoms, strongly driven by a resonant classical field, trapped in distant cavities connected by an optical fiber. Our scheme results in a constant gating time and, with an adjustable qubit-bus coupling (atom-resonator), one can specify a particular rotation R on the target qubit / Doutorado / Física / Doutor em Ciências

In 1920, Leon Brillouin discovered a new kind of light scattering – Brillouin scattering – which occurs as a result of the interaction of light with a transparent material’s temporal periodic variations in density and refractive index. Many advances have since been made in the study of Brillouin scattering, in particular in the field of fiber optics. An in-depth investigation of Brillouin scattering in optical fibers has been carried out in this thesis, and the theory of stimulated Brillouin scattering (SBS) and combined Brillouin gain and loss has been extended. Additionally, several important applications of SBS have been found and applied to current technologies. Several mathematical models of the pump-probe interaction undergoing SBS in the steady-state regime have emerged in recent years. Attempts have been made to find analytical solutions of this system of equations, however, previously obtained solutions are numerical with analytical portions and, therefore, qualify as hybrid solutions. Though the analytical portions provide useful information about intensity distributions along the fiber, they fall short of describing the spectral characteristics of the Brillouin amplification and the lack of analytical expressions for Brillouin spectra substantially limits the utility of the hybrid solutions for applications in spectral measurement techniques. In this thesis, a highly accurate, fully analytic solution for the pump wave and the Stokes wave in Brillouin amplification in optical fibers is given. It is experimentally confirmed that the reported analytic solution can account for spectral distortion and pump depletion in the parameter space that is relevant to Brillouin fiber sensor applications. The analytic solution provides a valid characterization of Brillouin amplification in both the low and high nonlinearity regime, for short fiber lengths. Additionally, a 3D parametric model of Brillouin amplification is proposed, which reflects the effects of input pump and Stokes powers on the level of pump wave depletion in the fiber, and acts as a classification tool to describe the level of similarity between various Brillouin amplification processes in optical fibers. At present, there exists a multitude of electro-optic modulators (EOM), which are used to modulate the amplitude, frequency, phase and polarization of a beam of light. Among these modulators, phase modulation provides the highest quality of transmitted signal. As such, an improved method of phase-modulation, based on the principles of stimulated Brillouin scattering, as well as an optical phase-modulator and optical phase network employing the same, has been developed. Due to its robustness, low threshold power, narrow spectrum and simplicity of operation, stimulated Brillouin scattering (SBS) has become a favourable underlying mechanism in fiber-based devices used for both sensing and telecommunication applications. Since birefringence is a detrimental effect for both, it is important to devise a comprehensive characterization of the SBS process in the presence of birefringence in an optical fiber. In this thesis, the most general model of elliptical birefringence in an optical fiber has been developed for a steady-state and transient stimulated Brillouin scattering (SBS) interaction, as well as the combined Brillouin gain and loss regime. The impact of the elliptical birefringence is to induce a Brillouin frequency shift and distort the Brillouin spectrum – which varies with different light polarizations and pulse widths. The model investigates the effects of birefringence and the corresponding evolution of spectral distortion effects along the fiber, and proposes regimes that are more favourable for sensing applications related to SBS – providing a valuable prediction tool for distributed sensing applications. In recent years, photonic computing has received considerable attention due to its numerous applications, such as high-speed optical signal processing, which would yield much faster computing times and higher bandwidths. For this reason, optical logic has been the focus of many research efforts and several schemes to improve conventional logic gates have been proposed. In view of this, a combined Brillouin gain and loss process has been proposed in a polarization maintaining optical fiber to realize all-Optical NAND/NOT/AND/OR logic gates in the frequency domain. A model describing the interaction of a Stokes, anti-Stokes and a pump wave, and two acoustic waves inside a fiber, ranging in length from 350m-2300m, was used to theoretically model the gates. Through the optimization of the pump depletion and gain saturation in the combined gain and loss process, switching contrasts of 20-83% have been simulated for different configurations.

Introduction: Bihar ranks among the most socio-economically disadvantaged states in India, and its public health system had long suffered from structural deficiencies which contributed to poor health outcomes. In November 2013, the Bihar government, with funding from Gates Foundation and technical support from CARE India, launched the state-wide Bihar Technical Support Program (BTSP) – seeking to address gaps in infrastructure, supply chain, and human resources, as well as the quality of service delivery, so as to improve reproductive, maternal, newborn and child health (RMNCH) and nutrition service provision. BTSP adopted a two-pronged strategy – conducting (i) periodic comprehensive facility assessments (CFAs) to identify and address the structural gaps; and (ii) nurse-mentoring programs to develop competency among nursing cadres in providing basic and comprehensive emergency obstetric and newborn care (BEmONC/ CEmONC) services. Through three inter-linked papers, the dissertation aimed to conduct an evidence-based assessment of this health system strengthening program. “Facility readiness” (structural readiness of public health facilities) was operationalized in terms of infrastructure, essential supplies, and human resources, while “facility performance” was operationalized based on the direct observation of normal vaginal deliveries and newborn care (including management of immediate complications if needed) and infection prevention practices in the labor rooms. The first paper describes the evolution of BTSP, and examines the initial progress made in facility readiness between 2015 and 2016. The second paper: (i) conducts a comparative assessment of facility readiness between 2017 (at end of the first four years of BTSP) and 2019, and describes the continuation of progress or lack thereof; (ii) quantifies facility readiness through a scoring system that reflects the readiness to provide maternal and newborn care (MNC) services; and (3) compares the change in this score over time (2015, 2017 and 2019) across different districts and levels of health facilities in Bihar. Thus, the first and second papers together examine the extent to which Bihar’s public health facilities were structurally strengthened in terms of physical infrastructure, supplies and workforce by utilizing data from all four rounds of CFAs conducted till date. The third paper asks the next logical question in a health system strengthening process – was facility readiness positively and significantly associated with facility performance? This is an important query, as it aims to provide evidence of synergistic progress, as envisioned under BTSP. First, the paper examines whether the facility-level performance changed, by comparing baseline (May-December, 2018) and endline (October-December, 2019) assessment data from the nurse-mentoring program (locally called AMANAT Jyoti). Second, it assesses the association of facility readiness (based on CFA 2019 data) with endline facility performance in providing MNC services. Methods: The first paper utilizes a structured, narrative review of scientific and grey literature to describe evolution of the BTSP since 2014, based on programmatic learnings through prior years (2011-2013) of collaborative vertical interventions. Subsequently, the paper measures the tangible change in select facility-level characteristics, utilizing quantitative data generated through two rounds of CFAs conducted by CARE India in 2015 (n=534 facilities) and 2016 (n=550 facilities). The second paper utilizes quantitative data generated through two rounds of CFAs conducted by CARE India in 2017 (n=550 facilities) and 2019 (n=552 facilities). Each CFAs covered all Level 2 (primary health centers) and Level 3 (higher-level facilities) public health facilities in Bihar that conducted at least 100 deliveries in the preceding year. Subsequently, the paper constructs a “facility-level MNC structural readiness score” – henceforth referred to as facility readiness score, based on a common set of indicators from CFA 2015, 2017 and 2019, to reflect human resources, infrastructure and essential supplies related to delivering MNC services. The paper uses this score to map the change at 2-year intervals, from 2015 to 2019, at both facility and district levels. The third paper utilizes quantitative data generated through two separate assessments conducted by CARE India – the 2019 CFA, and the 2018-2019 assessment of AMANAT Jyoti (nurse-mentoring program), which involved direct observation of normal vaginal deliveries, newborn care, and infection prevention practices in the labor rooms. The paper constructs baseline and endline facility-level MNC performance scores – henceforth referred to as facility performance scores based on data from AMANAT Jyoti assessments, and examines the association between endline facility performance and facility readiness scores. While descriptive statistics was used to present findings from the CFAs and AMANAT Jyoti assessments, paired t tests were used to test the mean change in scores over time and between the different levels of facilities. The association between endline facility performance and facility readiness scores was tested using simple as well as multiple linear and multinomial logistic regression modelling. Results: With a demonstrated intent to improve the ailing public health sector, the Bihar government in 2010 forged a collaboration with Gates Foundation to accelerate progress across RMNCH and nutrition programs. Through the Integrated Family Health Initiative program (IFHI, 2011-2013), outreach-based and facility-based solutions were implemented in eight programmatically-prioritized districts to address the stated goals. However, over this period, it became apparent that long-term success of such initiatives remained critically dependent on strengthening the foundational components of Bihar’s public health system –physical infrastructure, supply chain for drugs, consumables and equipment, and the skilled health workforce. These programmatic learnings motivated a re-think and consequent state-wide launch of the BTSP – characterized by a novel structure of health governance that was deeply embedded within the public health system, and a robust information management system that could generate, analyze and disseminate data on community- and facility-level services to support decision making. The quantitative analyses of CFA data (in first and second papers) provided an assessment of the changes that happened at the level of health facilities, likely supported by the policy-level modifications. There was a clear sense of prioritization of the limited resources – with constant focus on structurally preparing health facilities to deliver basic MNC services, more so at Level 2 (primary health centers). By 2019, at least 99% facilities at either level provided 24x7 delivery services and had designated labor rooms, 97% had designated newborn care corners which were mostly located inside the labor rooms, 70% or more had at least one functional fetal doppler, baby weighing machine, radiant warmer, and AMBU bag with neonatal oxygen masks. The improvement in availability of essential supplies like oxytocin, misoprostol, magnesium sulphate, antibiotics, and reproductive health commodities (condoms, intrauterine contraceptive devices, sanitary napkins, iron-folic acid tablets, contraceptive pills) were particularly notable during the 2017 and 2019 CFAs. However, the supply chain variably faltered for a number of other essential supplies like oral rehydration solutions, functional oxygen cylinders, normal saline and ringer lactate solutions. The data revealed that facility-level inefficiencies in utilizing the electronic inventory management system to accurately reflect actual status of supplies within the facility, likely compromised procurement and distribution. With regards to human resources, while a large number of auxiliary and general nurse midwives were available for service during CFA 2019, the BTSP faced continuing challenges (2015-2019) in recruiting and/or retaining physicians, especially the specialist physician cadres. By CFA 2019, these structural changes were also supported by remarkable improvements in two related services areas –availability of emergency transport, and laboratory services. The comparison of facility readiness scores (second paper) based on CFA 2015, 2017 and 2019 showed that while the mean scores increased sharply for both Level 2 (increase=1.51 (95% confidence interval: 1.39, 1.63)) and Level 3 (1.39 (1.1, 1.69)) facilities between 2015 and 2017, the progress was less pronounced at both levels between 2017 and 2019. 25 of the 38 districts in Bihar demonstrated a continuous increase in mean scores over the 3 CFAs. As for the remaining 13 districts, their 2019 mean scores remained higher than that during 2015. The analysis of AMANAT Jyoti assessment data (third paper) revealed improvements across 36 (80%) of the 45 performance parameters assessed through direct observation of deliveries between the baseline and endline. However, at least 80% compliance was observed for only 11 of 45 (24%) assessed parameters at baseline, and 16 of 45 (36%) at endline. The mean facility performance score increased significantly among both types and levels of facilities – but the increase was higher among Level 3 (mean increase = 1.56, p=0.0005, n=13) and CEmONC (1.82, p=0.0029, n=9) facilities, than among Level 2 (0.32, p =0.0288, n=121) and BEmONC (0.33, p=0.0168, n=125) facilities. The regression analysis failed to identify any linear relationship between facility readiness and performance scores. However, a significant positive association was observed between facility readiness score and the middle tertile of endline facility performance score (vs. lowest tertile as reference) in multiple multinomial logistic regression modeling (n=132 facilities). With increasing facility readiness score, the odds of a facility being in the middle tertile of the endline facility performance score relative to the lowest tertile was 1.68 (95% CI = 1.02, 2.76), after controlling for baseline facility performance score, mean delivery volume, and the facility level. Conclusion: The BTSP can be best described as a diagonal health system strengthening initiative –one that starts with a focus on specific programmatic (RMNCH) outcomes, but strives to achieve these through identifying and addressing bottlenecks across the health system. The efforts made to revamp health governance through creating structures for technical support from the state- to block-levels is particularly laudable, as is the remarkable capacity building in collecting and using facility-level data to inform programs and policies. The dissertation identified that BTSP has made appreciable progress in structurally preparing Bihar’s public health facilities to deliver basic MNC services – with improvements in related infrastructure, essential supplies, and supportive services like referral transport and laboratory facilities, as well as through recruitment of large number of ANM and GNM nurses. However, the process encountered a number of challenges, and it may be worthwhile to adopt a targeted approach to address some of these concerns. For example, it is important that the BTSP works to equip all facilities with electronic inventory management systems, while simultaneously training the personnel using such systems. To circumvent the chronic shortage of specialist physicians, a “task shifting” approach may help maximize utilization of existing health workforce to strengthen service delivery capacity. Further, the overall level of facility performance of MNC service delivery remained low at endline despite improvement from the baseline scores, and there was limited evidence of a significant positive association between facility readiness and performance scores. As these scores reflect the minimum essential requirements for a MNC service delivery setting, the BTSP clearly has challenges ahead. They must continue to address the persistent challenges in facility readiness and facility performance so that these two facility-level interventions will complement each other and influence outcomes. As the onus of this diagonal health system strengthening program incrementally shifts from development partners to the government, it will be important to recognize the significance and complexity of this effort.

In line with the rising demand for smarter solutions and embedded systems, Microelectromechanical systems (MEMS) have gained increasing importance for digital computing devices and Internet-of-Things (IoT) applications, most notably for mobile wearable devices. This achievement is driven by MEMS resonators' inherent properties such as simplicity, sensitivity, reliability, and low power consumption. Hence, they are being explored for ultra-low-power computing machines. Several fundamental digital logic gates, switching, and memory devices have been demonstrated based on MEMS microstructures' static and dynamic behavior. The interest of researchers in using MEMS resonators is due to seeking an alternative approach to circumvent the notable current leakage and power density problems of complementary metal-oxide-semiconductor (CMOS) technology. The continuous miniaturization of CMOS has increased the operating speed and reduces the size of the device. However, this has led to a relative increase in the leakage energy. This drawback in CMOS has renewed the interest of researchers in mechanical digital computations, which can be traced back to the work of Charles Babbage in 1822 on calculating engines. This dissertation presents axially-loaded and coupled-MEMS resonators investigations to demonstrate memory elements and different logic functions. The studies in this dissertation can be categorized majorly into three parts based on the implementation of logic functions using three techniques: electrothermal frequency tunability, electrostatic frequency modulations, and activation/deactivation of the resonant frequency. Firstly, the influence of the competing effects of initial curvature and axial loads on the mechanical behavior of MEMS resonator arches are investigated theoretically to predict the tunability of arches under axial loads. Then, the concept of electrothermal frequency tunability is used to demonstrate fundamental 2-bit logic gates. However, this concept consumes a considerable amount of energy due to the electrothermal technique. Next, the dynamic memory element and combinational logic functions are demonstrated using the concept of electrostatic frequency modulation. Though this approach is energy efficient compared to the electrothermal technique, it does not support the cascadability of MEMS resonator-based logic devices. Lastly, complex multifunctional logic gates are implemented based on selective modes activation and deactivation, resulting in significant improvement in energy efficiency and enabling cascadability of MEMS resonator-based logic devices.

This paper will explain my current compositional work, which focuses on the thematization, deconstruction, and reconstruction of musical idioms. I give an overview of the historical and aesthetic background for my work, drawing connections between Afro-diasporic aesthetics and the 20th and 21st century phenomenological tradition. I explain how I apply literary critic Henry Louis Gates’ concept of Signifyin(g) in my music through intertextuality, anachronistic instrumentation, microtonality, and rhythmic transformation. I then give an in- depth analysis of three pieces from Orlando Furioso (2022), En Tornasol, Galliard, and Bootstrap Bernie. I show how these concepts and resources can be applied to composition in creative and productive ways.

The notion of mechanical computation has been revived in the past few years, with the advances of nanofabrication techniques. Although electromechanical devices are inherently slow, they offer zero or very low off-state current, which reduces the overall power consumption compared to the fast complementary-metal-oxide-semiconductor (CMOS) counterparts. This energy efficiency feature is the most crucial requirement for most of the stand-alone battery-operated gadgets, biomedical devices, and the internet of things (IoT) applications, which do not require the fast processing speeds offered by the mainstream CMOS technology. In particular, using Micro-Electro-Mechanical (MEM) resonators in mechanical computing has drawn the attention of the research community and the industry in the last decade as this technology offers low power consumption, reduced circuit complexity compared to conventional CMOS designs, run-time re- programmability and high reliability due to the contactless mode of operation compared to other MEM switches such as micro-relays. In this thesis, we introduce digital circuit design techniques tailored for clamped-clamped beam MEM resonators. The main operation mechanism of these circuit blocks is based on fine-tuning of the resonance frequency of the micro-resonator beam, and the logic function performed by the devices is mainly determined by factors such as input/output terminal arrangement, signal type, resonator operation regime (linear/non-linear), and the operation frequency. These proposed circuits include the major building blocks of any microprocessor such as logic gates, a full adder which is a key block in any arithmetic and logic operation units (ALU), and I/O interface units, including digital to analog (DAC) and analog to digital (ADC) data converters. All proposed designs were first simulated using a finite element software and then the results were experimentally verified. Important aspects such as energy per operation, speed, and circuit complexity are evaluated and compared to CMOS counterparts. In all applications, we show that by proper scaling of the resonator’s dimensions, MHz operation speeds and energy consumption in the range of femto-joules per logic operation are attainable. Finally, we discuss some of the challenges in using MEM resonators in digital circuit design at the device level and circuit level and propose solutions to tackle some of them.