Security issues play an important role in almost all modern communication and computer networks. As Internet applications continue to grow dramatically, security requirements have to be strengthened. Hyperelliptic curve cryptosystems (HECC) allow for shorter operands at the same level of security than other public-key cryptosystems, such as RSA or Diffie-Hellman. These shorter operands appear promising for many applications. Hyperelliptic curves are a generalization of elliptic curves and they can also be used for building discrete logarithm public-key schemes. A major part of this work is the development of computer architectures for the different algorithms needed for HECC. The architectures are developed for a reconfigurable platform based on Field Programmable Gate Arrays (FPGAs). FPGAs combine the flexibility of software solutions with the security of traditional hardware implementations. In particular, it is possible to easily change all algorithm parameters such as curve coefficients and underlying finite field. In this work we first summarized the theoretical background of hyperelliptic curve cryptosystems. In order to realize the operation addition and doubling on the Jacobian, we developed architectures for the composition and reduction step. These in turn are based on architectures for arithmetic in the underlying field and for arithmetic in the polynomial ring. The architectures are described in VHDL (VHSIC Hardware Description Language) and the code was functionally verified. Some of the arithmetic modules were also synthesized. We provide estimates for the clock cycle count for a group operation in the Jacobian. The system targeted was HECC of genus four over GF(2^41).

Particle filters are a class of sequential Monte-Carlo methods which are used commonly when estimating various unknowns of the time-varying signals presented in real time, especially when dealing with nonlinearity and non-Gaussianity in BOT applications. This thesis work is designed to perform one such estimate involving tracking a person using the road information available from an IR surveillance video. In this thesis, a parallel custom hardware is implemented in Altera cyclone IV E FPGA device utilizing SIRF type of particle filter. This implementation has accounted how the algorithmic aspects of this sampling based filter relate to possibilities and constraints in a hardware implementation. Using 100MHz clock frequency, the synthesised hardware design can process almost 50 Mparticles/s. Thus, this implementation has resulted in tracking the target, which is defined by a 5-dimensional state variable, using the noisy measurements available from the sensor.

A codificação de vídeo digital depende de uma série de etapas para ser alcançada a compressão de dados necessária para, então, o vídeo ser enviado ou armazenado em um meio. Existe uma série de padrões que se propõe a isso e dentre eles, o que apresenta o melhor desempenho em termos de compressão de dados e qualidade de vídeo até o presente momento é o H.264/AVC. Considerando então o padrão H.264/AVC, uma das etapas do seu processamento é a codificação de entropia, sendo que um dos algoritmos usados para esse fim é o CAVLC (Context-Based Adaptive Variable Length Coding). Esta técnica faz uso de uma série de características onde o código gerado pela seqüência de vídeo processada tende a assumir, para, então, gerar códigos menores para padrões do vídeo que tendem a aparecer mais freqüentemente em detrimento a padrões que são mais raros, fazendo para isso uso de código de comprimento variável que depende do contexto atual em que cada porção do código está sendo processada. Baseado nisso, este trabalho apresenta uma arquitetura para o algoritmo CAVLC segundo o padrão H.264/AVC, onde foi inserida uma nova técnica para diminuir o gargalo na etapa inicial do algoritmo, além de usar técnicas já conhecidas na literatura para diminuir os ciclos necessários para o processamento do componente, fazendo com que a arquitetura aqui apresentada tenha um ganho em relação aos demais trabalhos da literatura encontrados e comparados. Esse trabalho está inserido no esforço do grupo de TV Digital da UFRGS e pretende-se que, no futuro, esse módulo seja integrado aos demais módulos desenvolvidos no grupo para formar um codificador H.264/AVC completo. / The digital video encoding depends on different phases to reach the necessary data compression, so the video can be transmitted through or stored in the medium. There are a variety of compression standards that are designed to that purpose and, among them, the one that has the best performance currently is the H.264/AVC. Considering the H.264/AVC standard, one of the processing stages is the entropy encoding. CAVLC (Context-Based Adaptive Variable Length Coding) is one of the algorithms that can be used for that end. It can use many of the code particularities, generated by the video sequence being processed. This way, CAVLC can generate codes with less bits for portions of the video sequence that occur more often, and codes with more bits for rarer patterns of the video sequence, using variable code lengths that depend on the current context for each portion of the code being processed. Based on this, the present work presents a VLSI hardware architecture for the CAVLC algorithm, according to the H.264/AVC standard. The architecture introduces a new technique to decrease the bottleneck at the initial stage of the algorithm and, furthermore, well-known techniques already tested in works found in the literature, were also implemented, to save processing cycles at the other stages of the component. The present architecture is then able to achieve gains compared to the other works found in the literature. This work is inserted into the effort of the Digital TV Group at UFRGS and it is intended to be integrated with the others developed by the group to make a complete H.264/AVC encoder.

A codificação de vídeo digital depende de uma série de etapas para ser alcançada a compressão de dados necessária para, então, o vídeo ser enviado ou armazenado em um meio. Existe uma série de padrões que se propõe a isso e dentre eles, o que apresenta o melhor desempenho em termos de compressão de dados e qualidade de vídeo até o presente momento é o H.264/AVC. Considerando então o padrão H.264/AVC, uma das etapas do seu processamento é a codificação de entropia, sendo que um dos algoritmos usados para esse fim é o CAVLC (Context-Based Adaptive Variable Length Coding). Esta técnica faz uso de uma série de características onde o código gerado pela seqüência de vídeo processada tende a assumir, para, então, gerar códigos menores para padrões do vídeo que tendem a aparecer mais freqüentemente em detrimento a padrões que são mais raros, fazendo para isso uso de código de comprimento variável que depende do contexto atual em que cada porção do código está sendo processada. Baseado nisso, este trabalho apresenta uma arquitetura para o algoritmo CAVLC segundo o padrão H.264/AVC, onde foi inserida uma nova técnica para diminuir o gargalo na etapa inicial do algoritmo, além de usar técnicas já conhecidas na literatura para diminuir os ciclos necessários para o processamento do componente, fazendo com que a arquitetura aqui apresentada tenha um ganho em relação aos demais trabalhos da literatura encontrados e comparados. Esse trabalho está inserido no esforço do grupo de TV Digital da UFRGS e pretende-se que, no futuro, esse módulo seja integrado aos demais módulos desenvolvidos no grupo para formar um codificador H.264/AVC completo. / The digital video encoding depends on different phases to reach the necessary data compression, so the video can be transmitted through or stored in the medium. There are a variety of compression standards that are designed to that purpose and, among them, the one that has the best performance currently is the H.264/AVC. Considering the H.264/AVC standard, one of the processing stages is the entropy encoding. CAVLC (Context-Based Adaptive Variable Length Coding) is one of the algorithms that can be used for that end. It can use many of the code particularities, generated by the video sequence being processed. This way, CAVLC can generate codes with less bits for portions of the video sequence that occur more often, and codes with more bits for rarer patterns of the video sequence, using variable code lengths that depend on the current context for each portion of the code being processed. Based on this, the present work presents a VLSI hardware architecture for the CAVLC algorithm, according to the H.264/AVC standard. The architecture introduces a new technique to decrease the bottleneck at the initial stage of the algorithm and, furthermore, well-known techniques already tested in works found in the literature, were also implemented, to save processing cycles at the other stages of the component. The present architecture is then able to achieve gains compared to the other works found in the literature. This work is inserted into the effort of the Digital TV Group at UFRGS and it is intended to be integrated with the others developed by the group to make a complete H.264/AVC encoder.

A codificação de vídeo digital depende de uma série de etapas para ser alcançada a compressão de dados necessária para, então, o vídeo ser enviado ou armazenado em um meio. Existe uma série de padrões que se propõe a isso e dentre eles, o que apresenta o melhor desempenho em termos de compressão de dados e qualidade de vídeo até o presente momento é o H.264/AVC. Considerando então o padrão H.264/AVC, uma das etapas do seu processamento é a codificação de entropia, sendo que um dos algoritmos usados para esse fim é o CAVLC (Context-Based Adaptive Variable Length Coding). Esta técnica faz uso de uma série de características onde o código gerado pela seqüência de vídeo processada tende a assumir, para, então, gerar códigos menores para padrões do vídeo que tendem a aparecer mais freqüentemente em detrimento a padrões que são mais raros, fazendo para isso uso de código de comprimento variável que depende do contexto atual em que cada porção do código está sendo processada. Baseado nisso, este trabalho apresenta uma arquitetura para o algoritmo CAVLC segundo o padrão H.264/AVC, onde foi inserida uma nova técnica para diminuir o gargalo na etapa inicial do algoritmo, além de usar técnicas já conhecidas na literatura para diminuir os ciclos necessários para o processamento do componente, fazendo com que a arquitetura aqui apresentada tenha um ganho em relação aos demais trabalhos da literatura encontrados e comparados. Esse trabalho está inserido no esforço do grupo de TV Digital da UFRGS e pretende-se que, no futuro, esse módulo seja integrado aos demais módulos desenvolvidos no grupo para formar um codificador H.264/AVC completo. / The digital video encoding depends on different phases to reach the necessary data compression, so the video can be transmitted through or stored in the medium. There are a variety of compression standards that are designed to that purpose and, among them, the one that has the best performance currently is the H.264/AVC. Considering the H.264/AVC standard, one of the processing stages is the entropy encoding. CAVLC (Context-Based Adaptive Variable Length Coding) is one of the algorithms that can be used for that end. It can use many of the code particularities, generated by the video sequence being processed. This way, CAVLC can generate codes with less bits for portions of the video sequence that occur more often, and codes with more bits for rarer patterns of the video sequence, using variable code lengths that depend on the current context for each portion of the code being processed. Based on this, the present work presents a VLSI hardware architecture for the CAVLC algorithm, according to the H.264/AVC standard. The architecture introduces a new technique to decrease the bottleneck at the initial stage of the algorithm and, furthermore, well-known techniques already tested in works found in the literature, were also implemented, to save processing cycles at the other stages of the component. The present architecture is then able to achieve gains compared to the other works found in the literature. This work is inserted into the effort of the Digital TV Group at UFRGS and it is intended to be integrated with the others developed by the group to make a complete H.264/AVC encoder.

The 21st century is considered as the era of mass communication and electronic information exchange. There is a dramatic increase in electronic communications and e-transactions worldwide. However, this advancement results in the appearance of many security issues, especially when the exchanged information is sensitive and/or confidential. A significant aspect of security is authentication, which in most of the cases is provided through a cryptographic hash function. As happens for the majority of security primitives, software design and implementation of hash functions is becoming more prevalent today. However, hardware is the embodiment of choice for military and safety-critical commercial applications due to the physical protection and increased performance that they offer. Hence, similarly to general hardware designs, regarding cryptographic hash function ones, three crucial issues, among others, arise: performance, reliability, and flexibility. In this PhD dissertation, hardware solutions regarding cryptographic hash functions, addressing the aforementionted three crucial issues are proposed. Specifically, a design methodology for developing high-throughput and area-efficient sole hardware architectures of the most widely-used cryptographic hash families, i.e. the SHA-1 and SHA-2, is proposed. This methodology incorporates several algorithmic-, system-, and circuit-level techniques in an efficient, recursive way, exploiting the changes in the design’s graph dependencies that are resulted by a technique’s application. Additionally, high-throughput and area-efficient hardware designs for the above families as well as new ones (e.g. JH and Skein), are also proposed. These architectures outperform significantly all the similar ones existing in the literature. Furthermore, a design methodology for developing Totally Self-Checking (TSC) architectures of the most widely-used cryptographic hash families, namely the SHA-1 and SHA-2 ones is proposed for the first time. As any RTL architecture for the above hash families is composed by similar functional blocks, the proposed methodology is general and can be applied to any RTL architecture of the SHA-1 and SHA-2 families. Based on the above methodology, TSC architectures of the two representatice hash functions, i.e. SHA-1 and SHA-256, are provided, which are significantlty more efficient in terms of Throughput/Area, Area, and Power than the corresponding ones that are derived using only hardware redundancy. Moreover, a design methodology for developing hardware architectures that realize more than one cryptographic hash function (mutli-mode architectures) with reasonable throughput and area penalty is proposed. Due to the fact that any architecture for the above hash families is composed by similar functional blocks, the proposed methodology can be applied to any RTL architecture of the SHA-1 and SHA-2 families. The flow exploits specific features appeared in SHA-1 and SHA-2 families and for that reason it is tailored to produce optimized multi-mode architectures for them. Based on the above methodology, two multi-mode architectures, namely a SHA256/512 and a SHA1/256/512, are introduced. They achieve high throughput rates, outperforming all the existing similar ones in terms of throughput/area cost factor. At the same time, they are area-efficient. Specifically, they occupy less area compared to the corresponding architectures that are derived by simply designing the sole hash cores together and feeding them to a commercial FPGA synthesis/P&R/mapping tool. Finally, the extracted knowledge from the above research activities was exploited in three additional works that deal with: (a) a data locality methodology for matrix–matrix multiplication, (b) a methodology for Speeding-Up Fast Fourier Transform focusing on memory architecture utilization, and (c) a near-optimal microprocessor & accelerators co-design with latency & throughput constraints. / Ο 21ος αιώνας θεωρείται η εποχή της μαζικής επικοινωνίας και της ηλεκτρονικής πληροφορίας. Υπάρχει μία δραματική αύξηση των τηλεπικοινωνιών και των ηλεκτρονικών συναλλαγών σε όλο τον κόσμο. Αυτές οι ηλεκτρονικές επικοινωνίες και συναλλαγές ποικίλουν από αποστολή και λήψη πακέτων δεδομένων μέσω του Διαδικτύου ή αποθήκευση πολυμεσικών δεδομένων, έως και κρίσιμες οικονομικές ή/και στρατιωτικές υπηρεσίες. Όμως, αυτή η εξέλιξη αναδεικνύει την ανάγκη για περισσότερη ασφάλεια, ιδιαίτερα στις περιπτώσεις όπου οι πληροφορίες που ανταλλάσονται αφορούν ευαίσθητα ή/και εμπιστευτικά δεδομένα. Σε αυτές τις περιπτώσεις, η ασφάλεια θεωρείται αναπόσπαστο χαρακτηριστικό των εμπλεκομένων εφαρμογών και συστημάτων. Οι συναρτήσεις κατακερματισμού παίζουν έναν πολύ σημαντικό ρόλο στον τομέα της ασφάλειας και, όπως συμβαίνει στην πλειοψηφία των βασικών αλγορίθμων ασφαλείας, οι υλοποιήσεις σε λογισμικό (software) επικρατούν στις μέρες μας. Παρόλα αυτά, οι υλοποιήσεις σε υλικό (hardware) είναι η κύρια επιλογή οσον αφορά στρατιωτικές εφαρμογές και εμπορικές εφαρμογές κρίσιμης ασφάλειας. Η NSA, για παράδειγμα, εξουσιοδοτεί μόνο υλοποιήσεις σε υλικό. Αυτό γιατί οι υλοποιήσεις σε υλικό είναι πολύ γρηγορότερες από τις αντίστοιχες σε λογισμικό, ενώ προσφέρουν και υψηλά επίπεδα «φυσικής» ασφάλειας λόγω κατασκευής. Έτσι, όσον αφορά τις κρυπτογραφικές συναρτήσεις κατακερματισμού, όπως ίσχυει γενικά στις υλοποιήσεις υλικού, ανακύπτουν τρία (ανάμεσα σε άλλα) κύρια θέματα: Επιδόσεις, Αξιοπιστία, Ευελιξία. Σκοπός της παρούσας διατριβής είναι να παράσχει λύσεις υλοποίησης σε υλικό για κρυπτογραφικές συναρτήσεις κατακερματισμού, στοχεύοντας στα τρία κύρια ζητήματα που αφορούν υλοποιήσεις σε υλικό, τα οποία και προαναφέρθηκαν (Επιδόσεις, Αξιοπιστία, Ευελιξία). Συγκεκριμένα, προτείνονται μεθοδολογίες σχεδιασμού αρχιτεκτονικών υλικού (καθώς και οι αρχιτεκτονικές αυτές καθαυτές) για τις οικογένειες SHA-1 και SHA-2 οι οποίες επιτυγχάνουν υψηλή ρυθμαπόδοση με λογική αύξηση της επιφάνειας ολοκλήρωσης. Επίσης, προτείνονται αρχιτεκτονικές οι οποίες επιτυγχάνουν υψηλή ρυθμαπόδοση με λογική αύξηση της επιφάνειας ολοκλήρωσης για νέες κρυπτογραφικές συναρτήσεις, δηλαδή για τις JH και Skein. Ακόμα, προτείνονται μεθοδολογίες σχεδιασμού αρχιτεκτονικών υλικού (καθώς και οι αρχιτεκτονικές αυτές καθαυτές) για τις οικογένειες SHA-1 και SHA-2 οι οποίες έχουν τη δυνατότητα να ανιχνέυουν πιθανά λάθη κατά τη λειτουργία τους ενώ επιτυγχάνουν υψηλή ρυθμαπόδοση με λογική αύξηση της επιφάνειας ολοκλήρωσης. Τέλος, προτείνονται μεθοδολογίες σχεδιασμού πολύ-τροπων αρχιτεκτονικών υλικού (καθώς και οι αρχιτεκτονικές αυτές καθ’αυτές) για τις οικογένειες SHA-1 και SHA-2 οι οποίες έχουν τη δυνατότητα να υποστηρίξουν παραπάνω από μία συνάρτηση ενώ επιτυγχάνουν υψηλή ρυθμαπόδοση με λογική αύξηση της επιφάνειας ολοκλήρωσης.

FPGA based systems have been heavily used to prototype and test Application Specic Integrated Circuit (ASIC) designs with much lower costs and development time compared to hardwired prototypes. In recentyears, thanks to both the latest technology nodes and a change in the architecture of reconfigurable integrated circuits (from traditional Complex Programmable Logic Device (CPLD) to full-CMOS FPGA), FPGAs have become more popular in embedded systems, both as main computation resources and as hardware accelerators. A new era is beginning for FPGA based systems: the partial run-time reconguration of a FPGA is a feature now available in products already on the market and hardware designers and software developers have to exploit this capability. Previous works show that, when designed properly, a system can improve both its power efficiency and its performance taking advantage of a partial run-time reconfigurable architecture. Unfortunately, taking advantage of run-time reconfigurable hardware is very challenging and there are several problems to face: the reconfiguration overhead is not negligible compared to nowadays CPUs performance,the reconfiguration time is not easily predictable, and the software has to be re-though to work with a time-evolving platform. This thesis project aims to investigate the performance of a modern run-time reconfigurable SoC (a Xilinx Zynq 7020), focusing on the reconfiguration overhead and its predictability, on the achievable speedup, and the trade-off and limits of this kind of platform. Since it is not always obvious when an application (especially a real-time one) is really able to use at its own advantage a partial run-time reconfigurable platform, the data collected during this project could be a valid help for hardware designers that use reconfigurable computing. / FPGA-baserade system har tidigare främst använts för snabb och kostnadseffektiv konstruktion av prototyper vid framtagandet av applikationsspecika integrerade kretsar (ASIC). På senare år har användandet av FPGA:er i inbyggda system för implementation av hårdvaruacceleratorers såväl som huvudsaklig beräkningsenhet ökat. Denna ökning har möjliggjorts mycket tack vare den utveckling som har skett av rekonfigurerbara integrerade kretsar: från de mer traditionella Complex Programmable Logic Devices (CPLD) till helt CMOS-baserade FPGA:er. Nu inleds en ny era för FPGA-baserade system tack vare möjligheten att under körning rekonfigurera delar av FPGA:n genom så kallad partial run-time reconguration(RTR) - en teknik som redan idag finns tillgänglig i produkter på marknaden. Tidigare forskning visar att användandet av en RTR-baserad hårdvaruarkitektur kan ha en positiv effekt med avseende på prestanda såväl som strömförbrukning. Att använda RTR-baserad hårdvara innebär dock flera utmaningar: En ej försumbar rekonfigurationstid måste tas i beaktning, så även den icke-deterministiska exekveringstiden som en rekonfiguration kan innebära. Vidare måste anpassningar av mjukvaran göras för att fungera med en hårdvaruplattform som förändras över tid. Denna uppsats syftar till att undersöka prestandan hos ett modernt RTRbaserat SoC (Xilinx Zynq 7020) med fokus på rekonfigurationstider och dess förutsägbarhet, prestanda ökning, begränsningar samt nödvändiga kompromisser som denna arkitektur innebär. Huruvida en applikation kan dra nytta av en RTR-baserad arkitektur eller inte kan vara svårt att avgöra. Den insamlade datan som presenteras i denna rapport kan dock fungera som stöd för hårdvarukonstruktörer som önskar använda en RTR-baserad plattform.