DC/DC Power converter design has been following a trend of reducing size while also increasing performance for the last several years. This push for higher power output and smaller footprint and profile requires integration and higher switching frequencies in order to continue. Higher frequencies require physical integration to eliminate problems induced by parasitics, which increase losses. GE's Power Overlay and Philip's PCB integration schemes have been clear steps in the quest to reduce size with new system design techniques. However, both have downsides. GE Power Overlay embeds the devices inside a milled AlN ceramic cavity and then layers interconnections on top using polyimide dielectric interlayers. The milling of AlN ceramic is a very costly and time consuming task due to the brittleness of the material, and the interlayers add additional complexity to the fabrication process. Philip's PCB integration was primarily aimed at integrating passives along with the PCB process for reduction of size. Inductor windings and capacitive layers were built up along with FR4 epoxy layers using typical PCB fabrication methods. However, unlike GE's Power Overlay, the substrate material was several times lower in thermal conductivity which invariably has corresponding thermal penalties. The work presented here reconciles the good of both integration techniques. Initially called Embedded Power, alumina ceramic was used as the substrate and rather than milling holes for the devices, holes were laser cut all the way through and interconnections were made by using interlayers and sputtered copper deposition, similar to GE's method. Integration of passives was done using LTCC ferrite to make an inductor of thin profile, rather than embedding cores and windings inside PCB. However, fabrication remained time consuming due to numerous solder masking and sputtering steps and thermal performance was not optimized due to the use of alumina ceramic. A revised design method called Stacked Power is presented in this dissertation that follows on the work of Embedded Power, but improves on it by simplifying fabrication through the elimination of thermally-restrictive interlayers, as well as time consuming sputtering and electroplating of copper interconnections. Instead, AlN Direct Bonded Copper is used as a multifunctional material thanks to its many-times-greater thermal conductivity than PCB or alumina, solderable device dies are implemented in a vertical fashion, and interconnections are simply made using copper straps soldered into place. For applications where moisture contamination and breakdown isolation are potential problems, dip conformal coating can easily be applied, replacing laborious solder masking. The work in this dissertation describes the fabrication methodology for Stacked Power, demonstrates the thermal advantages, and shows examples of high-frequency buck converters that achieve super-high levels of power density in the smallest of volumes and require no more thermal management than modest airflow. The added cost incurred with aluminum nitride is traded for distinct advantages in terms of low-profile, low airflow requirements for the power output, capability of natural convection for use in locations where fans are prohibitive and compact size for ease of implementation. / Ph. D.

Over the past several years, energy efficiency and power density have become the top concerns for power conversion. Rising energy intensity leads to a higher cost of delivering power. Meanwhile, the demand for compact power supplies grows significantly. It requires power supplies with high efficiency, low profile and high power density. Dc-dc power conversion has been widely applied for industry, medial, military and airspace applications. Conventional PWM dc-dc converters have relatively low power transfer efficiency and low power density. In contrast, resonant dc-dc converters have numerous advantages for dc-dc power conversions. In this work, topologies and system optimization of resonant converters are investigated to meet challenges of high efficiency, high power density, low EMI, easy startup and over current protection. LLC resonant converters can achieve zero-voltage-switching (ZVS) for primary side devices and zero-current-switching (ZCS) for the secondary side rectifiers. The switching loss is minimized. LLC is very attractive to overcome the issues of conventional circuits. However, challenges still remain. First of all, for low-voltage high-current applications, the synchronous rectifier (SR) with lower conduction loss is a must for high efficiency. To solve the driving issues of SRs, a novel synchronous driving scheme is proposed. Experimental results demonstrate the considerable loss reduction with utilization of the proposed driving scheme. Secondly, dc-dc converters are required to meet EMI standard. This work proposes an EMI mode. Based on the proposed model, EMI analysis and noise attenuation techniques are proposed and verified by experiments. Thirdly, startup and over-load protection are another issues of LLC resonant converters. With proposed multi-element resonant converters, the current limit issues can be resolved. In addition, the proposed multi-element resonant converters can utilize higher-order harmonics to enhance power transfer. Fourthly, for high-current applications, the secondary side structure becomes very critical. An improved secondary side construction is proposed to alleviate ac termination losses and SR paralleling issues. Novel winding structures are proposed to reduce the winding loss. The magnetic integration technique is proposed and analyzed, and an optimal integrated transformer design is proposed, which has low loss and compact size. / Ph. D.

Since future microprocessors will have higher current in accordance with Moore's law, there are still challenges for voltage regulators (VRs). Firstly, high efficiency is required not only for easy thermal management, but also for saving on electricity costs for data centers, or battery life extension for laptop computers. At the same time, high power density is required due to the increased power of the microprocessors. This is especially true for data centers, since more microprocessors are required within a given space (per rack). High power density is also required for laptop computers to reduce the size and the weight. To improve power density, a high frequency is required to shrink the size of the output inductors and output capacitors of the multi-phase buck VR. It has been demonstrated that the output bulk capacitors can be eliminated by raising the VR control bandwidth to around 350kHz. Assuming the bandwidth is one-third of the switching frequency, a VR should run at 1MHz to ensure a small size. However, the efficiency of a 12V VR is very poor at 1MHz due to high switching losses. As a result, a 12V VR can only run at 300kHz to 600kHz, and the power density is very low. To attain high efficiency and high power density at the same time, two-stage power architecture was proposed. The concept is "Divide and Conquer". A single-stage VR is split into two stages to get better performance. The second stage has about 5V-6V input voltage; thus the duty cycle can be extended and the switching losses are greatly reduced compared with a single-stage VR. Moreover, a sub-20V MOSFET can be used to further improve the efficiency at high frequencies. The first stage of the proposed two-stage architecture is converting 12V to 5-6V. High efficiency is required for the first stage since it is in series with the second stage. Previous first stage which is a buck converter has good efficiency but bulky size due to low frequency operation. Another problem with using a buck converter is that light-load efficiency of the first stage is poor. To solve these problems, switched-capacitor voltage dividers are proposed. Since the first stage does not require voltage regulation, the sweet point for the voltage divider can be determined and high efficiency can be achieved. At the same time, since there are no magnetic components for the switched-capacitor voltage divider, high power density can be achieved. By very careful design, a power density of more than 2000W/in3 with more than 97% efficiency can be achieved for the proposed voltage divider. The light-load efficiency of the voltage divider can be as high as 99% by reducing the switching frequency at light load. As for the second stage, different low-voltage devices are evaluated, and the best device combinations are found for high-frequency operation. It has been demonstrated that 91% efficiency can be achieved with 600kHz frequency, and 89% efficiency can be achieved with a 1MHz frequency for the second stage. Moreover, adaptive on-time control method and a non-linear inductor structure are proposed to improve CCM and DCM efficiency for the second stage respectively. Previously the two-stage VR was only used as a CPU VR. The two-stage concept can also be applied to other systems. In this dissertation, the two-stage power architecture is applied to two different applications: laptop computers and high-end server microprocessors. The common characteristics of the two applications are their thermal design power (TDP) requirement. Thus the first stage can be designed with much lower power than the maximum system power. It has been demonstrated that the two-stage power architecture can achieve either higher efficiency or higher power density and a lower cost when compared with the single-stage VR. To get higher efficiency, a parallel two-stage power architecture, named sigma architecture, is proposed for VR applications. The proposed sigma VR takes advantage of the high-efficiency, fast-transient unregulated converter (DCX) and relies on this converter to deliver most of the output power, while using a low-power buck converter to achieve voltage regulation. Both the DCX converter and the buck converter can achieve around 90% efficiency when used in the sigma VR, which ensures 90% efficiency for the sigma VR. The small-signal model of the sigma VR is studied to achieve adaptive voltage positioning (AVP). The sigma power architecture can also be applied to low-power point of load (POL) applications to reduce the magnetic component size and improve the efficiency. Finally, the two-stage VR and the sigma VR are briefly compared. / Ph. D.

The growing demand for high voltage, compact pulsed power supplies has gained great attention. It requires power supplies with high power density, low profile and high efficiency. In this thesis, topologies and techniques are investigated to meet and exceed these challenges. Non-isolation type topologies have been used for this application. Due to the high voltage stress of the output, non-isolation topologies will suffer severe loss problems. Extremely low switching frequency will lead to massive magnetic volume. For non-isolation topologies, PWM converters can achieve soft switching to increase switching frequency. However, for this application, due to the large voltage regulation range and high voltage transformer nonidealities, it is difficult to optimize PWM converters. Secondary diode reverse recovery is another significant issue for PWM techniques. Resonant converters can achieve ZCS or ZVS and result in very low switching loss, thus enabling power supplies to operate at high switching frequency. Furthermore, the PRC and LCC resonant converter can fully absorb the leakage inductance and parasitic capacitance. With a capacitive output filter, the secondary diode will achieve natural turn-off and overcome reverse recovery problems. With a three-level structure, low voltage MOSFETs can be applied for this application. Switching frequency is increased to 200 kHz. In this paper, the power factor concept for resonant converters is proposed and analyzed. Based on this concept, a new methodology to measure the performance of resonant converters is presented. The optimal design guideline is provided. A novel constant power factor control is proposed and studied. Based on this control scheme, the performance of the resonant converter will be improved significantly. Design trade-offs are analyzed and studied. The optimal design aiming to increase the power density is investigated. The parallel resonant converter is proven to be the optimum topology for this application. The power density of 31 W/inch3 can be achieved by using the PRC topology with the constant power factor control. / Master of Science

Pulse power system is widely used for medical, industrial and military applications. The operational principle of the pulse power system is that the energy from the input source is stored in the capacitor bank or superconducting inductive device through a dc-dc converter. Then, when a discharging signal exists, the stored energy is released to the load through pulse forming network (PFN) generating high peak power pulse up to gigawatts within several tens of or hundreds of microseconds. The pulse power system has been originally developed for the defense application. After the format of the voltage compression and voltage addition stages for the short-pulse high power acceleration has been established, it has been evolved to be common. Then, its application has been extended to food processing, medical equipment sterilization and wastewater treatment since many present environmental problems have been known in the early 70's or even earlier. In addition, the pulse power system is newly spotlighted due to the recent world events. The application examples are to treat anthrax-contaminated mail, and the use of accelerators to produce high power X-rays for security screening. Furthermore, the pulse power system has been applied for the tactical weapon system such as electrothermal-chemical (ETC) gun, coilgun and active armor system. Because the pulse power system applied for the tactical weapon system has the potential to be integrated in the military vehicle, a compact, lightweight pulse power system is strongly required for the future weapon system. In this thesis, a distributed power system (DPS) for the capacitor charger is introduced for the application of the active armor system. Furthermore, a design methodology is presented for the front-end converter to achieve the high efficiency as well as the high power density. Design parameters are identified and their impact on the design result is studied. the optimal operating point is determined based on the loss comparison between different operating points. In order to further improve the power density utilizing the unique operation mode i.e. pulse power operation, transformer design using amorphous-based core is provided and the design result is compared with that using ferrite-based core. A 5 kW prototype converter is built up and the experimentation is performed to verify the design. / Master of Science

The next generation of power converters not only must meet the characteristics demanded by the load, but also has to meet some specific requirements like limited space and high ambient temperature etc. This needs the power converter to achieve high power density and high temperature operation. It is usually required that the active power devices operate at higher switching frequencies to shrink the passive components volume. The power semiconductor devices for high frequency high density power converter applications have been investigated. Firstly, the methodology is developed to evaluate the power semiconductor devices for high power density applications. The power density figure of merit (PDFOM) for power MOSFET and IGBT are derived from the junction temperature rise, power loss and package points of view. The device matrices are generated for device comparison and selection to show how to use the PDFOM. A calculation example is given to validate the PDFOM. Several semiconductor material figures of merit are also proposed. The wide bandgap materials based power devices benefits for power density are explored compared to the silicon material power devices. Secondly, the high temperature operation characteristics of power semiconductor devices have been presented that benefit the power density. The electrical characteristics and thermal stabilities are tested and analyzed, which include the avalanche breakdown voltage, leakage current variation with junction temperature rise. To study the thermal stability of power device, the closed loop thermal system and stability criteria are developed and analyzed. From the developed thermal stability criterion, the maximum switching frequency can be derived for the converter system design. The developed thermal system analysis approach can be extended to other Si devices or wide bandgap devices. To fully and safely utilize the power devices the junction temperature prediction approach is developed and implemented in the system test, which considers the parasitic components inside the power MOSFET module when the power MOSFET module switches at hundreds of kHz. Also the thermal stability for pulse power application characteristics is studied further to predict how the high junction temperature operation affects the power density improvement. Thirdly, to develop high frequency high power devices for high power high density converter design, the basic approaches are paralleling low current rating power MOSFETs or series low voltage rating IGBTs to achieve high frequency high power output, because power MOSFETs and low voltage IGBTs can operate at high switching frequency and have better thermal handling capability. However the current sharing issues caused by transconductance, threshold voltage and miller capacitance mismatch during conduction and switching transient states may generate higher power losses, which need to be analyzed further. A current sharing control approach from the gate side is developed. The experimental results indicate that the power MOSFETs can be paralleled with proper gate driver design and accordingly the switching losses are reduced to some extent, which is very useful for the switching loss dominated high power density converter design. The gate driving design is also important for the power MOSFET module with parallel dice inside thus increased input capacitance. This results in the higher gate driver power loss when the traditional resistive gate driver is implemented. Therefore the advanced self-power resonant gate driver is investigated and implemented. The low gate driver loss results in the development of the self-power unit that takes the power from the power bus. The overall volume of the gate driver can be minimized thus the power density is improved. Next, power semiconductor device series-connection operation is often used in the high power density converter to meet the high voltage output such as high power density boost converter. The static and dynamic voltage balancing between series-connected IGBTs is achieved using a hybrid approach of an active clamp circuit and an active gate control. A Scalable Power Semiconductor Switch (SPSS) based on series-IGBTs is developed with built-in power supply and a single optical control terminal. An integrated package with a common baseplate is used to achieve a better thermal characteristic. These design features allow the SPSS unit to function as a single optically controlled three-terminal switching device for users. Experimental evaluation of the prototype SPSS shows it fully achieved the design objectives. The SPSS is a useful power switch concept for building high power density, high switching frequency and high voltage functions that are beyond the capability of individual power devices. As conclusions, in this dissertation, the above-mentioned issues and approaches to develop high density power converter from power semiconductor devices standpoint are explored, particularly with regards to high frequency high temperature operation. To realize such power switches the related current sharing, voltage balance and gate driving techniques are developed. The power density potential improvements are investigated based on the real high density power converter design. The power semiconductor devices effects on power density are investigated from the power device figure of merit, high frequency high temperature operation and device parallel operation points of view. / Ph. D.

The increased power consumption and power density demands of modern technologies combined with the focus on global energy savings have increased the demands on DC/DC power supplies. DC/DC converters are ubiquitous in everyday life, found in products ranging from small handheld electronics requiring a few watts to warehouse sized server farms demanding over 50 megawatts. To improve efficiency and power density while reducing complexity and cost the modular building block approach is gaining popularity. These modular building blocks replace individually designed specialty power supplies, providing instead an optimized complete solution. To meet the demands for lower loss and higher power density, higher efficiency and higher frequency must be targeted in future designs. The objective of this dissertation is to explore and propose methods to improve the power density and performance of point of load modules ranging from 10 to 600W. For non-isolated, low current point of load applications targeting outputs ranging from one to ten ampere, the use of a three level converter is proposed to improve efficiency and power density. The three level converter can reduce the voltage stress across the devices by a factor of two compared to the traditional buck; reducing switching losses, and allowing for the use of improved low voltage lateral and lateral trench devices. The three level can also significantly reduce the size of the inductor, facilitating 3D converter integration with a low profile magnetic by doubling the effective switching frequency and reducing the volt-second across the inductor. This work also proposes solutions for the drive circuit, startup, and flying capacitor balancing issues introduced by moving to the three level topology. The emerging technology of gallium nitride can offer the ability to push the frequency of traditional buck converters to new levels. Silicon based semiconductors are a mature technology and the potential to further push frequency for improved power density is limited. GaN transistors are high electron mobility transistors offering a higher band gap, electron mobility, and electron velocity than Si devices. These material characteristics make the GaN device more suitable for higher frequency and voltage operation. This work will discuss the fundamentals of utilizing the GaN transistor in high frequency buck converter design; addressing the packaging of the GaN transistor, fundamental operating differences between GaN and Si devices, driving of GaN devices, and the impact of dead time on loss in the GaN buck converter. An analytical loss model for the GaN buck converter is also introduced. With significant improvements in device technology and packaging, the circuit layout parasitics begins to limit the switching frequency and performance. This work will explore the design of a high frequency, high density 12V integrated buck converter, identifying the impact of parasitics on converter performance, propose design improvements to reduce critical parasitics, and assess the impact of frequency on passive integration. The final part of this research considers the thermal design of a high density 3D integrated module; this addresses the thermal limitations of standard PCB substrates for high power density designs and proposes the use of a direct bond copper (DBC) substrate to improve thermal performance in the module. For 48V isolated applications, the current solutions are limited in frequency by high loss generated from the use of traditional topologies, devices, packaging, and transformer design. This dissertation considers the high frequency design of a highly efficient unregulated bus converter targeting intermediate bus architectures for use in telecom, networking, and high end computing applications. This work will explore the impact of switching frequency on transformer core volume, leakage inductance, and winding resistance. The use of distributed matrix transformers to reduce leakage inductance and winding resistance, improving high frequency transformer performance will be considered. A novel integrated matrix transformer structure is proposed to reduce core loss and core volume while maintaining low leakage inductance and winding resistance. Lastly, this work will push for higher frequency, higher efficiency, and higher power density with the use of low loss GaN devices. / Ph. D.

Moore's Law has been used to describe and predict the blossom of IC industries, so increasing the data density is clearly the ultimate goal of all technological development. If the power density of power electronics converters can be analogized to the data density of IC's, then power density is a critical indicator and inherent driving force to the development of power electronics. Increasing the power density while reducing or keeping the cost would allow power electronics to be used in more applications. One of the design challenges of the high-density power converter design is to have high-density magnetic components which are usually the most bulky parts in a converter. Increasing the switching frequency to shrink the passive component size is the biggest contribution towards increasing power density. However, two factors, losses and parasitics, loom and compromise the effect. Losses of high-frequency magnetic components are complicated due to the eddy current effect in magnetic cores and copper windings. Parasitics of magnetic components, including leakage inductances and winding capacitances, can significantly change converter behavior. Therefore, modeling loss and parasitic mechanism and control them for certain design are major challenges and need to be explored extensively. In this dissertation, the abovementioned issues of high-frequency transformers are explored, particularly in regards to high-power converter applications. Loss calculations accommodating resonant operating waveform and Litz wire windings are explored. Leakage inductance modeling for large-number-of-stand Litz wire windings is proposed. The optimal design procedure based on the models is developed. / Ph. D.

In recent years, the SiC power semiconductor has emerged as an attractive alternative that pushes the limitations of junction temperature, power rating, and switching frequency of Si devices. These advanced properties will lead converters to higher power density. However, the reliability of the SiC semiconductor is still under investigation, and at the same time, the standard Si device packages do not meet the requirement of high temperature operation. In order to take full advantage of SiC semiconductor devices, high density, high temperature device packaging needs to be developed. In this dissertation, a high temperature wirebond package for multi-chip phase-leg power module using SiC devices was designed, developed, fabricated and tested. The details of the material selection and thermo-mechanical reliability evaluation are described. High temperature power test shows that the presented package can perform well at the high junction temperature. In order to increase the power density, reduce the parasitic parameters, and enhance the electrical, thermo-mechanical performance over wirebond packages, planar package is utilized to better take advantages of SiC device. This dissertation proposed a novel package, in which the interconnections can be formed on small dimensional pads and enclosed pads that may baffle the regular solder based connection in other planar packages. Electrical and thermo-mechanical tests of the prototype module demonstrate the functionality and reliability of the presented planar packaging methodology. In this dissertation, together with the design example, the manual module layout design and automatic module layout design process are also presented. Furthermore, a systematic optimal design process and parametric study of the heatsink-fan cooling system by applying the analytical model is described. This dissertation also established a systematic testing procedure which can rapidly detect defects and reduce the risk in high temperature packaging testing. Finally, a wirebond module and a planar module are designed for 175 ºC junction temperature and 250 ºC junction temperatures. All the key concepts and ideas developed in this work are implemented in the prototype module development and then verified by the experimental results. / Ph. D.

This dissertation proposes a high-power, high-frequency and high-density three-level parallel resonant converter for capacitor charging. DC-DC pulsed power converters are widely used in military and medical systems, where the power density requirement is often stringent. The primary means for reducing the power converter size has been to reduce loss for reduced cooling systems and to increase the frequency for reduced passive components. Three-level resonant converters, which combine the merits of the three-level structure and resonant converters, are an attractive topology for these applications. The three-level configuration allows for the use of lower-voltage-rating and faster devices, while the resonant converter reduces switching loss and enhances switching capability. This dissertation begins with an analysis of the influence of variations in the structure of the resonant tank on the transformer volume, with the aim of achieving a high power density three-level DC-DC converter. As one of the most bulky and expensive components in the power converter, the different positions of the transformer within the resonant tank cause significant differences in the transformer's volume and the voltage and current stress on the resonant elements. While it does not change the resonant converter design or performance, the improper selection of the resonant tank structure in regard to the transformer will offset the benefits gained by increasing the switching frequency, sometimes even making the power density even worse than the power density when using a low switching frequency. A methodology based on different structural variations is proposed for a high-density design, as well as an optimized charging profile for transformer volume reduction. The optimal charging profile cannot be perfectly achieved by a traditional output-voltage based variable switching frequency control, which either needs excess margin to guarantee ZVS, or delivers maximum power with the danger of losing ZVS. Moreover, it cannot work for widely varied input voltages. The PLL is introduced to overcome these issues. With PLL charging control, the power can be improved by 10% with a narrow frequency range. The three-level structure in particular suffers unbalanced voltage stress in some abnormal conditions, and a fault could easily destroy the system due to minimized margin. Based on thoroughly analysis on the three-level behaviors for unbalanced voltage stress phenomena and fault conditions, a novel protection scheme based on monitoring the flying capacitor voltage is proposed for the three-level structure, as well as solutions to some abnormal conditions for unbalanced voltage stresses. A protection circuit is designed to achieve the protection scheme. A final prototype, built with a custom-packed MOSFET module, a SiC Schottky diode, a nanocrystalline core transformer with an integrated resonant inductor, and a custom-designed oil-cooled mica capacitor, achieves a breakthrough power density of 140W/in3 far beyond the highest-end power density reported (<100 W/in3) in power converter applications. / Ph. D.