The functionality provided by mobile devices such as cellular phones and tablets continues to increase over the years, with integration of an ever larger number of wireless standards within a given device. In several of these designs, each standard supported by a device requires its own IC receiver to be mounted on the device’s PCB. In multistandard and multimode radios, it is desirable to integrate all receivers onto the same IC as the digital processors for the standards, in order to reduce device cost and size. Ideally all the receivers should also share a single signal chain. Since each standard has its own requirements for linearity and noise figure, and each standard operates at a different RF carrier frequency, implementing such a receiver is very challenging. Such a receiver could be theoretically implemented using a broadband mixing receiver or by direct sampling by a high-speed analog-to-digital converter (ADC). Broadband mixing requires the use of a harmonic rejection mixer (HRM) or tunable band pass filter to remove harmonic mixing effects, which in the past have suffered from a large primary clock tuning range and high power consumption. However, direct sampling of the RF input requires a high-speed ADC with large dynamic range which is typically limited by clock timing skew, clock jitter, or harmonic folding. In this dissertation, techniques for programmable broadband radio receivers are proposed. A local oscillator (LO) synthesis method within HRMs is proposed which reduces the required primary clock tuning range in broadband receivers. The LO synthesis method is implemented in 130-nm CMOS. A clocking technique is introduced within the two-stage HRM, which helps in achieving state-of-the-art harmonic rejection performance without calibration or harmonic filtering. An analog frequency synthesis based broadband channelizer is proposed using the LO synthesis method which is capable of channelizing a broadband input using a single mixing stage and primary clock frequency. A frequency-folded ADC architecture is proposed which enables high-speed sampling with high dynamic range. A receiver based on the frequency-folded ADC architecture is implemented in 65-nm CMOS and achieves a sample rate of 2-GS/s, a mean 49-dB SNDR, and 8.5-dB NF. / text

Recent studies on growth of telecomm sector depict an ever rising demand for high bandwidth applications such as on-line gaming, high definition television and many more. This demand is coupled with increase in internet connected utilities per house hold - each requiring a portion of bandwidth. The fast development of broadband telecommunication services calls for an upgrade of access infrastructure. This challenge could be met by technologies such as Fiber-To-The-Home/Building (FTTH/B) point-to-multipoint (P2MP) optical access networking. Further, FTTH is also widely regarded as a future proof solution for broadband telecommunication services within scientific and industrial sectors. This has encouraged large amount of research and development throughout the globe to find optimal topologies for FTTH. OFDM based optical access network topology abbreviated as OTONES is an ongoing EU FP 7 project under the PIANO+ framework. The OTONES project addresses the next generation optical access networking on the basis of Orthogonal Frequency Division Multiplexing (OFDM) and Orthogonal Frequency Multiple Access (OFDMA), with special provision for reduced complexity and signal processing aspects of the subscriber side terminals (ONUs). This thesis focuses on the theoretical investigation of OFDM based optical access network topology OTONES. The thesis provides an in depth view of the salient aspects of the topology and formulates the key requirements of OTONES topology. The investigation primarily delves on two important aspects of the topology. First, finding the optimal analog circuitry for the optical network unit (ONU). Second, finding the optimal operation regime for the topology and hence optimizing the system level concept. In this thesis, we show that the requirement of an analog circuitry originates from the need of successive up-conversions in OTONES topology which also produces image spectrum. This image spectrum causes a 3 dB loss in power and spectral efficiency in absence of a proper image rejection circuitry. Thus, we discuss the generic SSB generation methods for efficient image rejection. Novel Bedrosian method based on Bedrosian Theorem is established as a promising method for image rejection. We show that this method is an analog implementation of Hilbert Transform Method and does not involve any approximation. Both generic methods for SSB along with the Novel Bedrosian method are evaluated based on the criterion established for OTONES topology. Finally, optical filtering from the set of generic SSB method is proposed for the downstream path and Novel Bedrosian method is proposed for the upstream path. The tolerance limits for Novel Bedrosian method, are also established for its physical implementation. We further discuss the realistic implementation of various components of the OTONES topology. We also establish the optimal operation regime of the full concurrent topology based on parameters such as input optical power, pilot tone separation and many more. Finally as a key feature of the thesis, we optimize the system level concept of the topology with the use of the proposed Novel Bedrosian Method as the optimal analog circuitry for OTONES topology and provide a region of optimal operation of the topology.