An interactive software shell has been developed which integrates several packaging simulation tools developed at the University of Arizona which are used to analyze electro-magnetic coupling between interconnects in an integrated circuit. This software shell uses experimental frames to manage this simulation process. Through the experimental frames, the model descriptions and the model inputs are separated, and input data is verified for correctness. This model/input separation allows several model variations to be tested based on several input variations. The results of these simulations are then analyzed and displayed graphically. Further work for the software shell is discussed. This tool provides a user-friendly, efficient method for performing coupled-line analyses in interconnect systems.

The objective of this research is to explore the feasibility of addressing the major performance and reliability problems or issues, such as wirelength, stress-induced carrier mobility variation, temperature, and quality trade-offs, found in three-dimensional integrated circuits (3D ICs) that use through-silicon vias (TSVs) at placement stage. Four main works that support this goal are included. In the first work, wirelength of TSV-based 3D ICs is the main focus. In the second work, stress-induced carrier mobility variation in TSV-based 3D ICs is examined. In the third work, temperature inside TSV-based 3D ICs is investigated. In the final work, the quality trade-offs of TSV-based 3D-IC designs are explored. In the first work, a force-directed, 3D, and gate-level placement algorithm that efficiently handles TSVs is developed. The experiments based on synthesized benchmarks indicate that the developed algorithm helps generate GDSII layouts of 3D-IC designs that are optimized in terms of wirelength. In addition, the impact of TSVs on other physical aspects of 3D-IC designs is also studied by analyzing the GDSII layouts. In the second work, the model for carrier mobility variation caused by TSV and STI stresses is developed as well as the timing analysis flow considering the stresses. The impact of TSV and STI stresses on carrier mobility variation and performance of 3D ICs is studied. Furthermore, a TSV-stress-driven, force-directed, and 3D placement algorithm is developed. It exploits carrier mobility variation, caused by stress around TSVs after fabrication, to improve the timing and area objectives during placement. In addition, the impact of keep-out zone (KOZ) around TSVs on stress, carrier mobility variation, area, wirelength, and performance of 3D ICs is studied. In the third work, two temperature-aware global placement algorithms are developed. They exploit die-to-die thermal coupling in 3D ICs to improve temperature during placement. In addition, a framework used to evaluate the results from temperature-aware global placements is developed. The main component of the framework is a GDSII-level thermal analysis that considers all structures inside a TSV-based 3D IC while computing temperature. The developed placers are compared with several state-of-the-art placers published in recent literature. The experimental results indicate that the developed algorithms help improve the temperature of 3D ICs effectively. In the final work, three block-level design styles for TSV-based die-to-wafer bonded 3D ICs are discussed. Several 3D-IC layouts in the three styles are manually designed. The main difference among these layouts is the position of TSVs. Finally, the area, wirelength, timing, power, temperature, and mechanical stress of all layouts are compared to explore the trade-offs of layout quality.

A series of complex digital blocks have been designed and fabricated using the newly developed current-mode differential CMOS logic family viz. the Folded Source-Coupled Logic ( FSCL ). The main feature of this logic family is the low current spikes generated during the switching transitions ( at least 2 orders of magnitude smaller than the conventional static CMOS gates ). The design of a decimation filter using novel Multi-Rate systolic architecture and it's implementation in Folded Source-Coupled Logic is also considered. The decimation filter thus designed can be used in mixed-mode applications like Sigma-Delta A/D converter to improve it's performance characteristics like dynamic range, resolution and phase linearity at higher sampling rates. / Graduation date: 1992

dimensional integrated circuits (3D ICs) fabricated with through-silicon vias (TSVs) have smaller planar dimensions, shorter wire length, and better performance than 2D ICs. Heat dissipation causing temperature increase has posed new challenges for design of 3D integrated circuits (IC). In addition to the thermal problem, 3D ICs also require careful design of power grids/network because many inter-tier resistive through-silicon vias in 3D IC can cause larger voltage drop than 2D ICs. The performance optimization of a 3D stack requires validation of thermal and electrical integrity during the co-design. Many 3D stacks will combine digital and analog circuitry, requiring a strong mixed-signal design approach. This will require close collaboration between different domains of circuit fabrication which traditionally have been working separately. Hence there must be some standards to facilitate smooth and effective design of 3D ICs. In this thesis, we perform steady-state electrical and thermal simulations to analyze the properties of a 3D stack. We optimize electrical and thermal performance using genetic algorithm to achieve optimized power map profile for minimizing voltage drop and temperature, which can benefit both thermal and power integrity management. This thesis presents initial efforts in designing such standards. Steady state electrical and thermal simulations are performed to demonstrate the necessary information that needs to be exchanged between the dies to ensure adequate co-design. The main purpose of a Design Exchange Format (DEF) between dies is to permit sharing of information necessary for design by external parties without disclosing their intellectual property (IP). The requirements of the standards should be the minimum necessary to produce satisfactory answers. Producing such models is just a customer support function. The role of the standards is to facilitate the transfer of information through a compact model, not necessarily to build one.

Optical interconnects are important to the future development of microelectronics. Volume grating couplers (VGCs) provide a compact, efficient coupling mechanism that is compatible with microelectronics fabrication processes. In this dissertation, some of the performance characteristics of VGCs are investigated. Also, integration of VGCs with Sea of Polymer Pillars (SoPP), an emerging high-density input/output interconnect technology, is demonstrated and its performance quantitatively investigated. First, the polarization-dependent performance of VGCs is analyzed, and the design constraints for achieving high-efficiency polarization-dependent and polarization-independent VGCs are examined. The effects of loss on VGC performance are also presented. Then, the wavelength response of VGCs and its dependence on grating parameters is quantitatively examined. Experimental demonstrations of polarization-dependent and polarization-independent VGCs are then presented. Finally, a VGC integrated with a SoPP is demonstrated and its performance characterized.

published_or_final_version / Electrical and Electronic Engineering / Doctoral / Doctor of Philosophy

Not available / text

Thesis (Ph. D.)--State University of New York at Binghamton, Department of Computer Science, Thomas J. Watson School of Engineering and Applied Science, 2007. / Includes bibliographical references.

Thesis (Ph.D.) - Carleton University, 2002. / Includes bibliographical references (p. 159-172). Also available in electronic format on the Internet.

Thesis (M.App.Sc.) - Carleton University, 2005. / Includes bibliographical references (p. 126-132). Also available in electronic format on the Internet.