On Computer Science research, traditionally, most efforts have been devoted to research hardness for the worst case of problems (proving NP completeness and comparing and reducing problems between them are the two most known). Artifcial Intelligence research, recently, has focused also on how some characteristics of concrete instances have dramatic effects on complexity and hardness while worst-case complexity remains the same. This has lead to focus research efforts on understanding which aspects and properties of problems or instances affect hardness, why very similar problems can require very diferent times to be solved. Research search based problems has been a substantial part of artificial intelligence research since its beginning. Big part of this research has been focused on developing faster and faster algorithms, better heuristics, new pruning techniques to solve ever harder problems. One aspect of this effort to create better solvers consists on benchmarking solver performance on selected problem sets, and, an, obviously, important part of that benchmarking is creating and defining new sets of hard problems. This two folded effort, on one hand to have at our disposal new problems, harder than previous ones, to test our solvers, and on the other hand, to obtain a deeper understanding on why such new problems are so hard, thus making easier to understand why some solvers outperform others, knowledge that can contribute towards designing and building better and faster algorithms and solvers. This work deals with designing better, that is harder and easy to generate, problems for CSP solvers, also usable for SAT solvers. In the first half of the work general concepts on hardness and CSP are introduced, including a complete description of the chosen problems for our study. This chosen problems are, Random Binary CSP Problems (BCSP), Quasi-group Completion Problems (QCP), Generalised Sudoku Problems (GSP), and a newly defined problem, Edge-Matching Puzzles (GEMP). Although BCSP and QCP are already well studied problems, that is not the case with GSP and GEMP. For GSP we will define new creation methods that ensure higher hardness than standard random methods. GEMP on the other hand is a newly formalised problem, we will define it, will provide also algorithms to build easily problems of tunable hardness and study its complexity and hardness. On the second part of the work we will propose and study new methods to increase the hardness of such problems. Providing both, algorithms to build harder problems and an in-depth study of the effect of such methods on hardness, specially on resolution time.

After the 2008 global financial tsunami, the global economy has been undergoing a ¡§great recession¡¨, and it has a tremendous impact on Taiwan's venture capital industry. Not only overall investment, but also financing is descending rapidly. Although Taiwan has always performed well in the field of venture capital, it encounters many setbacks nowadays, such as ¡§Hard to find the target.¡¨,¡¨ Recession of capital market.¡¨, ¡§Narrowest Cash-out. ¡¨ and "Major innovations take longer and more resources." etc. These problems are difficult to overcome. Therefore, to spend money on the cutting edge, investing in professional fields is the best policy of venture capital, and it requires of venture capital institutions substantial accumulation of professional knowledge in the specific fields as well as industrial integration capabilities. Scholars have put forth the view that corporate venture capital and independent venture capital must learn from each other. How to dominate the standards of investment industry , how to make the global positioning strategy, whether corporate venture capital needs to meet the overall strategy, and venture capital strategy , organizing, management methods. These are key issues for corporate venture capital. Intel capital is the world's largest science and technology intensive venture capital. This study will draw on its experience of successful and unique investment, combined with the concept of open innovation¡Asuggesting that corporate venture capital in Taiwan take "innovation intermediary" mode which will not only reduce investment risk and but also investment cost.

En aquesta tesi s’estudien diferents estructures algèbriques, reticles i monoides, en el conjunt de nombres borrosos discrets. En particular, s’analitza en profunditat el reticle distributiu fitat de nombres borrosos discrets que tenen per suport un subconjunt de nombres naturals consecutius inclòs en la cadena finita L={0,1,...,n}. Sobre aquest reticle, es proporcionen diferents mètodes per a construir funcions d’agregació (t-normes, t-conormes, uninormes, nulnormes, ...) a partir de funcions d’agregació anàlogues definides sobre la cadena finita L. D’altra banda, aquest treball també se centra en l’estudi i construcció de funcions d’implicació sobre dit reticle. En particular s’analitzen els quatre tipus més clàssics de tals funcions. La darrera part d’aquesta memòria proporciona dues possibles aplicacions de la teoria desenvolupada. En la primera, s’investiguen diferents processos d’agregació de la informació basats en l’extensió de funcions d’agregació discretes. Finalment, es proposen diferents extensions del concepte clàssic de multiconjunt i s’estudien diferents propietats i estructures reticulars / En esta tesis se estudian diferentes estructuras algebraicas, retículos y monoides, en el conjunto de números borrosos discretos. En particular, se analiza el retículo distributivo acotado de números borrosos discretos que tienen por soporte un subconjunto de números naturales consecutivos incluido en la cadena finita L={0,1,…,n}. Sobre este retículo, se proporcionan diferentes métodos para construir funciones de agregación (t-normas, t-conormas, uninormas, nulnormas, ...) a partir de funciones de agregación análogas definidas sobre L. Además, se estudian y construyen funciones de implicación sobre dicho retículo borroso. En particular, se analizan las cuatro clases más usuales de estas funciones. En la última parte de esta memoria se proponen dos posibles aplicaciones de la teoría desarrollada. En la primera, se investigan diferentes procesos de agregación de la información basados en la extensión de funciones de agregación discretas. Finalmente, se proponen diferentes extensiones del concepto clásico de multiconjunto, estudiando diferentes propiedades y estructuras reticulares. / In this thesis we study different algebraic structures, lattices and monoids, in the set of discrete fuzzy numbers. In particular, we analyze in depth the bounded distributive lattice of discrete fuzzy numbers whose support is a subset of consecutive natural numbers included in the finite chain L ={0,1, ..., n}. On this lattice, different methods are also provided to build aggregation functions (t-norms, t-conorms, uninorms, nullnorms, …) from analogous aggregation functions defined on L. Moreover, this work also focuses on the study and construction of implication functions on this lattice. In particular, the four most classical types are studied. In the last part of this work, we propose two possible applications of the developed theory. Firstly, we investigate different aggregation information processes based on the extension of discrete aggregation functions. Finally, we propose different extensions of the classical concept of multiset. From these extensions, we study several properties and lattice structures.

This thesis describes an environment to evaluate and compare static schedulers for real pipelined streaming applications on massively parallel architectures, such as Intel Single chip Cloud Computer (SCC), Adapteva Epiphany, and Tilera TILE-Gx series. The framework allows performance comparison of schedulers in their execution time, or the energy usage of static schedules with energy models and measurements on real platform. This thesis focuses on the implementation of a framework evaluating the energy consumption of such streaming applications on the SCC. The framework can run streaming applications, built as task collections, with static schedules including dynamic frequency scaling. Streams are handled by the framework with FIFO buffers, connected between tasks. We evaluate the framework by considering a pipelined mergesort implementation with different static schedules. The runtime is compared with the runtime of a previously published task based optimized mergesort implementation. The results show how much overhead the framework adds on to the streaming application. As a demonstration of the energy measuring capabilities, we schedule and analyze a Fast Fourier Transform application, and discuss the results. Future work may include quantitative comparative studies of a range of different static schedulers. This has, to our knowledge, not been done previously.

No description available.

Thesis (MScEng)--Stellenbosch University, 2002. / ENGLISH ABSTRACT: This report describes the development of a Java Bytecode Compiler (JBC) for the 8051 micro-controller. Bytecodes are found in the class file generated when a Java source file is compiled with the java compiler (javac). On Java platforms, the Java Virtual Machine (JVM) interprets and executes the bytecodes. Currently existing Java platforms do not support programming the 8051 using Java. As an 8-bit micro-controller with only 64 KB of total memory, the 8051's word size and memory is too limited to implement a NM. Moreover, full applications of the 8051 require that it handles hardware interrupts and access 110 ports and special registers. This thesis proposes a JBC to compile the standard bytecodes found in the class file and generate equivalent assembly code that can run on the 8051. The JBC was tested on the 8051 compatible AT89C52*44 micro-controller with a program that simulates an irrigation controller. The code generated by the JBC executes correctly but is large in size and runs slower than code of a program written in assembly. Conclusions drawn are that the JBC can be used to compile Java programs intended for the 8051 and its family of micro-controllers. In particular, it is especially a good tool for people who prefer Java to other languages. The JBC is suitable for smaller programs that do not have efficiency as a major requirement. / AFRIKAANSE OPSOMMING: Hierdie tesis beskryf die ontwikkeling van 'n Java "Bytecode" samesteller (Java Bytecode Compiler, JBC) vir die 8051 mikro beheerder argitektuur. "Bytecodes" is die produk van die standaard Java samesteller "javac" en word deur 'n platform spesifieke Java Virtuele Masjien gelees en uitgevoer. Geen NM is huidig beskikbaar vir die 8051 argitektuur nie. Die gekose 8-bis 8051 mikro beheerder het 'n beperkte interne geheue van 64kB. Hierdie beperking maak dit nie geskik vir 'n IVM nie. Daar moet ook voorsiening gemaak word om hardeware onderbrekings te hantering en te kan kommunikeer met die poorte en spesiale registers van die mikro beheerder. JBC word ontwikkel wat die standaard "Bytecode" kompileer na geskikte masjien kode wat dan op die mikro beheerder gebruik kan word. Die JBC is ontwikkel en toets en 'n eenvoudige besproeiing program is geskryf om op 'n Atmel AT89C52*44 te loop. Die kode werk goed maar is nog nie geoptimeer nie en loop onnodig stadig. Optimerings metodes word aanbeveel en bespreek. Die gevolgtrekking is dat die huidige JBC kan gebruik word om Java kode te skryfvir die 8051 beheerder. Dit maak die hardeware platform nou beskikbaar aan Java programmeerders. Daar moet wel gelet word dat die JBC op die oomblik net geskik is vir klein programme en waar spoed nie die primêre vereiste is nie.

When distributing multiple TV programs on a fixed bandwidth channel, the bit rate of each video stream is often constant. Since video sent at a constant quality is typically wildly varying, this is a very unoptimal solution. By instead sharing the total bit rate among all programs, the video quality can be increased by allocating bit rate where it is needed. This thesis explores the statistical multiplexing problem for a specific hardware platform with the limitations and advantages of that platform. A solution for statistical multiplexing is proposed and evaluated using the major codecs used for TV distribution today. The main advantage of the statistical multiplexer is a lot more even quality and a higher minimum quality achieved across all streams. While the solution will need a faster method for bit rate approximation for a more practical solution in terms of performance, the solution is shown to work as intended.

The aim of this thesis is to analyze development of mobile software, specially the hybrid approach of mobile development. The theoretical part compares native and hybrid approach of development and on the basis of selected criteria compares technologies available for hybrid mobile development. The practical part of the thesis focuses on hybrid mobile application design, its development and the subsequent testing. At the conclusion there is a summarization of findings and experiences gained during the elaboration, design, development and testing of application.

Thesis MTech(Electrical Engineering)--Cape Technikon, Cape Town, 1996 / The development of the 8051 Evaluation and Training Board was in response to fulfill a need to have a training board available for students at the start of a micro-controller course. This board must be used to get hands-on experience in the internal architecture, programming and operation of the controller through the testing of sample programs and exercises. It can act as an example of a practical micro-controller application board, and also as part of, or as an aid in the design and application of own projects. The board had to be cheap enough so that each student can be issued with a personal board for the duration of the course. It had to be adequately selfsufficient to be portable and to operate independent of a host PC. In addition, it had to contain adequate "intelligence" to guide the student in the use of the board: have a quick re-programming turn-around cycle; and it must be possible to use the board for user program testing and debugging. After drawing up an initial set of objectives and investigating the economic viability of similar systems in industry, an outline of the required design was made. This included the selection of suitable communication between the onboard Operating System and a user; the easiest way to load user programs into the board memory; and methods to test and debug this program. All the normal support circuitry required by a micro-controller to accommodate a minimum system for operation was included into a single Field Programmable Gate Array. The execution of the project was therefore divided into three distinct sections, the hardware, the firmware (Programmable Array configuration) and the software. In the design, the harmony between these sections had to be consolidated to yield a successful final product. The simplicity and ergonomics of the operation and application from a user's point of view, had to be accentuated and kept in mind throughout. In a design of the complexity such as this, careful planning and the investigation of various methods of approach were essential. The use of many computer-aided design and other relevant computer packages was incorporated. Interaction between the user and the Operating System on the board was done through a standard 16-character by 1-line LCD Display Module and a 32-key keyboard. The main feature of the Operating System was to enable the inspection and editing of all the memory locations on the micro-processor.

With the advent of mass-market consumer multicore processors, the growing trend in the consumer off-the-shelf general purpose processor industry has moved away from increasing clock frequency as the classical approach for achieving higher performance. This is commonly attributed to the well-known problems of power consumption and heat dissipation with high frequencies and voltage. This paradigm shift has prompted research into a relatively new field of "many-core" processors, such as the Intel Single-chip Cloud Computer. The SCC is a concept vehicle, an experimental homogenous architecture employing 48 IA32 cores interconnected by a high-speed communication network. As similar multiprocessor systems, such as the Cell Broadband Engine, demonstrate a significantly higher aggregate bandwidth in the interconnect network than in memory, we examine the viability of a pipelined approach to sorting on the Intel SCC. By tailoring an algorithm to the architecture, we investigate whether this is also the case with the SCC and whether employing a pipelining technique alleviates the classical memory bottleneck problem or provides any performance benefits. For this purpose, we employ and combine different classic algorithms, most significantly, parallel mergesort and samplesort.