Probabilistic simultaneous polynomial reconstruction algorithm of Bleichenbacher-Kiayias-Yung is extended to the polynomials whose degrees are allowed to be distinct. Furthermore, it is observed that probability of the algorithm can be increased. Specifically, for a finite field $F$, we present a probabilistic algorithm which can recover polynomials $p_1,ldots, p_r in F[x]$ of degree less than $k_1,k_2,ldots,k_r$, respectively with given field evaluations $p_l(z_i) = y_{i,l}$ for all $i in I$, $|I|=t$ and $l in [r]$ with probability at least $1 - (n - t)/|F|$ and with time complexity at most $O((nr)^3)$. Next, by using this algorithm, we present a probabilistic decoder for interleaved Reed-Solomon codes. It is observed that interleaved Reed-Solomon codes over $F$ with rate $R$ can be decoded up to burst error rate $frac{r}{r+1}(1 - R)$ probabilistically for an interleaving parameter $r$. It is proved that a Reed-Solomon code RS$(n / k)$ can be decoded up to error rate $frac{r}{r+1}(1 - R&#039 / )$ for $R&#039 / = frac{(k-1)(r+1)+2}{2n}$ when probabilistic interleaved Reed-Solomon decoders are applied. Similarly, for a finite field $F_{q^2}$, it is proved that $q$-folded Hermitian codes over $F_{q^{2q}}$ with rate $R$ can be decoded up to error rate $frac{q}{q+1}(1 - R)$ probabilistically. On the other hand, it is observed that interleaved codes whose subcodes would have different minimum distances can be list decodable up to radius of minimum of list decoding radiuses of subcodes. Specifically, we present a list decoding algorithm for $C$, which is interleaving of $C_1,ldots, C_b$ whose minimum distances would be different, decoding up to radius of minimum of list decoding radiuses of $C_1,ldots, C_b$ with list size polynomial in the maximum of list sizes of $C_1,ldots, C_b$ and with time complexity polynomial in list size of $C$ and $b$. Next, by using this list decoding algorithm for interleaved codes, we obtained new list decoding algorithm for $qh$-folded Hermitian codes for $q$ standing for field size the code defined and $h$ is any positive integer. The decoding algorithm list decodes $qh$-folded Hermitian codes for radius that is generally better than radius of Guruswami-Sudan algorithm, with time complexity and list size polynomial in list size of $h$-folded Reed-Solomon codes defined over $F_{q^2}$.

Time-Interleaved Analog to Digital Converters (TI ADC) consist of several individual sub-converters operating at a lower sampling rate, working in parallel, and in a circular loop. Thereby, they are increasing the sampling rate without compromising on the resolution during conversion, at high sampling rates. The latter is the main requirement in the area of radio frequency sampling. However, they suffer from mismatches caused by the different characteristics in each sub-converter and the TI structure. The output of the TI ADC under consideration contains a lot of harmonics and spurious tones due to the non-linearities mismatch between the sub-converters. Therefore, previously extensive frequency planning was performed to avoid the input signal from coinciding with these harmonic bins. More importance has been given to digital calibration in recent years where algorithms are developed and implemented outside ADC in a Digital signal processor (DSP), whereas the compensation is done in real time. In this work, we model the distortions and the harmonics present in the TI ADC output to get a clear understanding of the TI ADC. A post-correction block is developed for the cancellation of the characterized harmonics. The suggested method is tested on the TI ADCs working at radio frequencies, but is valid also for other types of ADCs, such as pipeline ADCs and sigma-delta ADCs.

ITC/USA 2011 Conference Proceedings / The Forty-Seventh Annual International Telemetering Conference and Technical Exhibition / October 24-27, 2011 / Bally's Las Vegas, Las Vegas, Nevada / A novel type-II hybrid automatic repeat request (HARQ) algorithm using adaptive modulations and bit-interleaved coded modulation (BICM) is presented. The algorithm uses different optimized puncturing patterns for different transmissions of the same data packet. The proposed approach exploits mapping diversity through BICM with iterative decoding. The modulation order is changed in each transmission to keep the number of symbols transmitted constant. We present new bit error rate and frame error rate analytical results for the proposed technique showing good agreement with simulation results. We compare the throughput performance of our proposed HARQ technique with a reference HARQ technique that uses different mapping arrangements but keeps the modulation order fixed. By using optimized puncturing patterns and adaptive modulations, our method provides significantly better throughput performance over the reference HARQ method in the whole signalto- noise ratio (SNR) range, and achieves a gain of 12 dB in the medium SNR region.

The work explores extending time interleaving in A/D converters, by applying a high-level of parallelism to one of the slowest and simplest types of data-converters, the counter ADC. The motivation for the work is to realise high-performance re-configurable A/D converters for use in multi-standard and multi-PHY communication receivers with signal bandwidths in the 10s to 100s of MHz. The counter ADC requires only a comparator, a ramp signal, and a digital counter, where the comparator compares the sampled input against all possible quantisation levels sequentially. This work explores arranging counter ADCs in large time-interleaved arrays, building a Time Interleaved Counter (TIC) ADC. The key to realising a TIC ADC is distributed sampling and a global multi-phase ramp generator realised with a novel figure-of-8 rotating resistor ring. Furthermore Counter ADCs allow for re-configurability between effective sampling rate and resolution due to their sequential comparison of reference levels in conversion. A prototype TIC ADC of 128-channels was fabricated and measured in 0.13μm CMOS technology, where the same block can be configured to operate as a 7-bit 1GS/s, 8-bit 500MS/s, or 9-bit 250MS/s dataconverter. The ADC achieves a sub 400fJ/step FOM in all modes of configuration.

M. Tech. (Engineering: Electrical, Department Electronic Engineering, Faculty of Engineering and Technology), Vaal University of Technology, / “If we think oil is a problem now, just wait 20 years. It’ll be a nightmare.” — Jeremy Rifkin, Foundation of Economic Trends, Washington, D.C., August 2003. This statement harmonises with the reality that human civilisation faces today. As a result, humankind has been forced to look for alternatives to fossil fuels. Among possible solutions, fuel cell (FC) technology has received a lot of attention because of its potential to generate clean energy. Fuel cells have the advantage that they can be used in remote telecommunication sites with no grid connectivity as the majority of telecommunication equipment operates from a DC voltage supply. Power plants based on phosphoric acid fuel cell (PAFC) have been installed worldwide supplying urban areas, shopping centres and medical facilities with electricity, heat and hot water. Although these are facts regarding large scale power plants for on-site use, portable units have been explored as well. Like any other fuel cell, the PAFC output power is highly unregulated leading to a drastic drop in the output voltage with changing load value. Therefore, various DC–DC converter topologies with a wide range of input voltages can be used to regulate the fuel cell voltage to a required DC load. An interleaved synchronous buck converter intended for efficiently stepping down the energy generated by a PAFC was designed and developed. The design is based on the National Semiconductor LM5119 IC. A LM5119 evaluation board was redesigned to meet the requirements for the application. The measurements were performed and it was found that the converter achieved the expectations. The results showed that the converter efficiently stepped down a wide range of input voltages (22 to 46 V) to a regulated 13.8 V while achieving a 93 percent efficiency. The conclusions reached and recommendations for future research are presented. / Telkom Centre of Excellence, TFMC, M-Tech, THRIP.

Les convertisseurs analogique-numérique à entrelacement temporel (TIADC) semblent être une solution prometteuse dans le monde de la conversion analogique-numérique. Leur fréquence d’échantillonnage peut théoriquement être augmentée en augmentant le nombre de convertisseurs en parallèle. En réalité, des désappariements entre les convertisseurs peuvent fortement dégrader les performances, particulièrement à haute fréquence d’échantillonnage ou à haute résolution. Ces défauts d’appariement peuvent être réduits en utilisant des techniques de calibration en arrière-plan. La première partie de cette thèse est consacrée à l’étude des sources et effets des différents types de désappariements dans un TIADC. Des indicateurs de performance tels que le SNDR ou la SFDR sont exprimés en fonction du niveau des désappariements. Dans la deuxième partie, des nouvelles techniques de calibration sont proposées. Ces techniques permettent de réduire les effets des désappariements d’offset, de gain, d’instant d’échantillonnage et de bande passante. Les désappariements sont estimés en se basant sur des propriétés statistiques du signal et la reconstruction des échantillons de sortie se fait en utilisant des filtres numériques. La troisième partie démontre les performance d’un TIADC fonctionnant a une fréquence d’échantillonnage de 1.6 GE/s et comprenant les calibration d’offset, de gain et d’instant d’échantillonnage proposées. Les raies fréquentielles dues aux désappariements sont réduites à un niveau de -70dBc jusqu’à une fréquence d’entrée de 750 MHz. Ce circuit démontre une meilleure correction de désappariements que des circuits similaires récemment publiés, et ce avec une augmentation de puissance consommée et de surface relativement faible. / Time-interleaved analog-to-digital converters (TIADC) seem to be the holy grail of analog-to-digital conversion. Theoretically, their sampling speed can be increased, very simply, by duplicating the sub-converters. The real world is different because mismatches between the converters strongly reduce the TIADC performance, especially when trying to push forward the sampling speed, or the resolution of the converter. Using background digital mismatch calibration can alleviate this limitation. The first part of the thesis is dedicated to studying the sources and effects of mismatches in a TIADC. Performance metrics such as the SNDR and the SFDR are derived as a function of the mismatch levels. In the second part, new background digital mismatch calibration techniques are presented. They are able to reduce the offset, gain, skew and bandwidth mismatch errors. The mismatches are estimated by using the statistical properties of the input signal and digital filters are used to reconstruct the correct output samples. In the third part, a 1.6 GS/s TIADC circuit, implementing offset, gain and skew mismatch calibration, demonstrates a reduction of the mismatch spurs down to a level of -70 dBFS, up to an input frequency of 750 MHz. The circuit achieves the lowest level of mismatches among TIADCs in the same frequency range, with a reasonable power and area, in spite of the overhead caused by the calibration.

The growth of digital systems underscores the need to convert analog information to the digital domain at high speeds and with great accuracy. Analog-to-Digital Converter (ADC) calibration is often a limiting factor, requiring longer calibration times to achieve higher accuracy. The goal of this dissertation is to perform a fully digital background calibration using an arbitrary input signal for A/D converters. The work presented here adapts the cyclic "Split-ADC" calibration method to the time interleaved (TI) and successive approximation register (SAR) architectures. The TI architecture has three types of linear mismatch errors: offset, gain and aperture time delay. By correcting all three mismatch errors in the digital domain, each converter is capable of operating at the fastest speed allowed by the process technology. The total number of correction parameters required for calibration is dependent on the interleaving ratio, M. To adapt the "Split-ADC" method to a TI system, 2M+1 half-sized converters are required to estimate 3(2M+1) correction parameters. This thesis presents a 4:1 "Split-TI" converter that achieves full convergence in less than 400,000 samples. The SAR architecture employs a binary weight capacitor array to convert analog inputs into digital output codes. Mismatch in the capacitor weights results in non-linear distortion error. By adding redundant bits and dividing the array into individual unit capacitors, the "Split-SAR" method can estimate the mismatch and correct the digital output code. The results from this work show a reduction in the non-linear distortion with the ability to converge in less than 750,000 samples.

"This work describes the integrated circuit design of a 16-bit, 10Msample/sec, combination ‘split’ interleaved analog to digital converter. Time interleaving of analog to digital converters has been used successfully for many years as a technique to achieve faster speeds using multiple identical converters. However, efforts to achieve higher resolutions with this technique have been difficult due to the precise matching required of the converter channels. The most troublesome errors in these types of converters are gain, offset and timing differences between channels. The ‘split ADC’ is a new concept that allows the use of a deterministic, digital, self calibrating algorithm. In this approach, an ADC is split into two paths, producing two output codes from the same input sample. The difference of these two codes is used as the calibration signal for an LMS error estimation algorithm that drives the difference error to zero. The ADC is calibrated when the codes are equal and the output is taken as the average of the two codes. The ‘split’ ADC concept and interleaved architecture are combined in this IC design to form the core of a high speed, high resolution, and self-calibrating ADC system. The dual outputs are used to drive a digital calibration engine to correct for the channel mismatch errors. This system has the speed benefits of interleaving while maintaining high resolution. The hardware for the algorithm as well as the ADC can be implemented in a standard 0.25um CMOS process, resulting in a relatively inexpensive solution. This work is supported by grants from Analog Devices Incorporated (ADI) and the National Science Foundation (NSF). "

Les convertisseurs analogique-numérique à entrelacement temporel (TIADC) semblent être une solution prometteuse dans le monde de la conversion analogique-numérique. Leur fréquence d’échantillonnage peut théoriquement être augmentée en augmentant le nombre de convertisseurs en parallèle. En réalité, des désappariements entre les convertisseurs peuvent fortement dégrader les performances, particulièrement à haute fréquence d’échantillonnage ou à haute résolution. Ces défauts d’appariement peuvent être réduits en utilisant des techniques de calibration en arrière-plan. La première partie de cette thèse est consacrée à l’étude des sources et effets des différents types de désappariements dans un TIADC. Des indicateurs de performance tels que le SNDR ou la SFDR sont exprimés en fonction du niveau des désappariements. Dans la deuxième partie, des nouvelles techniques de calibration sont proposées. Ces techniques permettent de réduire les effets des désappariements d’offset, de gain, d’instant d’échantillonnage et de bande passante. Les désappariements sont estimés en se basant sur des propriétés statistiques du signal et la reconstruction des échantillons de sortie se fait en utilisant des filtres numériques. La troisième partie démontre les performance d’un TIADC fonctionnant a une fréquence d’échantillonnage de 1.6 GE/s et comprenant les calibration d’offset, de gain et d’instant d’échantillonnage proposées. Les raies fréquentielles dues aux désappariements sont réduites à un niveau de -70dBc jusqu’à une fréquence d’entrée de 750 MHz. Ce circuit démontre une meilleure correction de désappariements que des circuits similaires récemment publiés, et ce avec une augmentation de puissance consommée et de surface relativement faible. / Time-interleaved analog-to-digital converters (TIADC) seem to be the holy grail of analog-to-digital conversion. Theoretically, their sampling speed can be increased, very simply, by duplicating the sub-converters. The real world is different because mismatches between the converters strongly reduce the TIADC performance, especially when trying to push forward the sampling speed, or the resolution of the converter. Using background digital mismatch calibration can alleviate this limitation. The first part of the thesis is dedicated to studying the sources and effects of mismatches in a TIADC. Performance metrics such as the SNDR and the SFDR are derived as a function of the mismatch levels. In the second part, new background digital mismatch calibration techniques are presented. They are able to reduce the offset, gain, skew and bandwidth mismatch errors. The mismatches are estimated by using the statistical properties of the input signal and digital filters are used to reconstruct the correct output samples. In the third part, a 1.6 GS/s TIADC circuit, implementing offset, gain and skew mismatch calibration, demonstrates a reduction of the mismatch spurs down to a level of -70 dBFS, up to an input frequency of 750 MHz. The circuit achieves the lowest level of mismatches among TIADCs in the same frequency range, with a reasonable power and area, in spite of the overhead caused by the calibration.

A multilevel Space Vector PWM (SVPWM) technique is developed for a 3-level 3-phase PWM Voltage Source Inverter using a 3-phase coupled inductor to ensure high performance operation. The selection of a suitable PWM switching scheme for the Coupled Inductor Inverter (CII) topology should be based on the dual requirements for a high-quality multilevel PWM output voltage together with the need to minimize high frequency currents and associated losses in the coupled inductor and the inverter switches. Compared to carrier-based multilevel PWM schemes, the space vector techniques provide a wider variety of choices of the available switching states and sequences. The precise identification of pulse placements in the SVPWM method is used to improve the CII performance. The successful operation of the CII topology over the full modulation range relies on selecting switching states where the coupled inductor presents a low winding current ripple and a high effective inductance between the upper and lower switches in each inverter leg. In addition to these requirements, the CII operation is affected by the imbalance inductor common mode dc current. When used efficiently, SVPWM allows for an appropriate balance between the need to properly manage the inductor winding currents and to achieve harmonic performance gains. A number of SVPWM strategies are developed, and suitable switching states are selected for these methods. Employing the interleaved PWM technique by using overlapping switching states, the interleaved Discontinuous SVPWM (DSVPWM) method, compared to other proposed SVPWM methods, doubles the effective switching frequency of the inverter outputs and, as a result, offers superior performance for the CII topology by reducing the inductor losses and switching losses. The inverter operation is examined by means of simulation and experimental testing. The experimental performance comparison is obtained for different PWM switching patterns. The inverter performance is affected by high-frequency inductor current ripple; the excessive inductor losses are reduced by the DSVPWM method. Additional experimental test results are carried out to obtain the inverter performance as a variable frequency drive when operated in steady-state and during transient conditions. The CII topology is shown to have great potential for variable speed drives. / Power Engineering and Power Electronics