Coordenação de Aperfeiçoamento de Pessoal de Nível Superior / This work presents a detailed analysis about the interleaved buck converter applied to electronic ballasts to supply high power HID lamps, assuming the input voltage as a PFC stage output. As the output capacitor has a maximum value to be applied in parallel with the lamp, parallel operated converters are a suitable choice because the output current ripple cancellation characteristic. Besides, the output current ripple cannot be greater than 5% of the nominal current to avoid acoustic resonance phenomena. Also, interleaved converters allow magnetic and semiconductors losses reduction. The applied topology was the interleaved buck converter, because its inherent characteritstic of the output as a current source. A generalized model for the IBC operating in CCM was obtained, including inductors and semiconductors losses, besides an analysis to achieve the optimum point of design in terms of efficiency, size and complexity of implementation. To apply the IBC in CCM supplying HID lamps, it is necessary inductors current control, which means to guarantee a current source behavior of the converter. For that, two current control loop were designed, one for each inductor being measured via a shunt resistor located at the circuit input. Also, stability was analyzed based on impedance criterion. Finally, complete electronic ballast was presented, gathering a two-cell IBC, full-bridge inverter, measuring circuits for current and voltage and an external circuit for the correct delay of the IBC MOSFETs gate signals. Obtained experimental results were satisfatory, showing equal current sharing, once warm-up stage and closed-loop implementation were via an 8-bits microcontroller. / Este trabalho apresenta uma análise detalhada do conversor buck intercalado como reator eletrônico aplicado à alimentação de lâmpadas de descarga em alta pressão (HID) de alta potência, assumindo a entrada como a saída de uma etapa de correção de fator de potência (PFC). A característica de diminuição da ondulação da corrente de saída de conversores operando em paralelo é uma grande vantagem, pois o capacitor em paralelo com a lâmpada tem um valor limite a fim de garantir a estabilidade do sistema. Aliada a essa condição, a ondulação de corrente na lâmpada não pode ultrapassar 5% da corrente nominal para garantir que não ocorra o fenômeno da ressonância acústica de forma destrutiva. Além disso, permitem redução de perdas magnéticas e nos semicondutores, além de apresentar diminuição na ondulação da corrente de saída através da defasagem dos sinais de comando dos interruptores, diminuindo o capacitor de saída a ser empregado. Em termos de análise do conversor buck intercalado (IBC), foi obtida uma modelagem generalizada para o conversor operando em modo de condução contínua (CCM) incluindo as perdas nos interruptores, indutores e diodo. Também foi realizada uma análise de ponto ótimo de projeto contemplando tamanho, eficiência e complexidade de implementação. Para a utilização do IBC em CCM na alimentação de lâmpadas HID é necessário o controle de corrente dos indutores, ou seja, garantir que o conversor tenha o comportamento semelhante à uma fonte de corrente. Para tal, foram utilizadas duas malhas de controle de corrente, uma para cada indutor, sendo o sinal de controle medido através de um resistor shunt localizado na entrada do conversor. Ainda, foi apresentada uma análise de estabilidade baseada na relação entre as impedâncias da lâmpada e do conversor, com realimentação em modo corrente. Finalmente, o reator completo foi apresentado, constituído do IBC com duas células, inversor full-bridge, circuito inibidor para defasagem dos sinais de comando do IBC e o circuito de medição das correntes e tensão. Os resultados experimentais obtidos foram satisfatórios, com correntes equilibradas, uma vez que o IBC com malha fechada em ambos os indutores foi implementado com um microcontrolador de 8-bits, com frequência de barramento de 16 MHz.

This work presents a study and a comparative analysis of high power single-phase converter applied to power factor correctioii in according to the international standards IEC 61000-3-4 (harmonics limitation) and CISPR 22 (electromagnetic interference limitation) for high power applications. The converters studied were the conventional boost converter, the interleaved boost converter, with two cell operating with a delay angle of 180" between each other, and the dual boost converter. Such converters are used in front-end modules of information technology equipment. AI1 converters have the same input and output voltage and the same input current. The converters were projected to provide the same total input harmonic distortion (THD), with the idea of using the same input filter. Implementation of the control laws was performed through a digital control with the use of a 16 bits microcontroller. A11 converters were, first of all, studied and presented in this dissertation. The analyzed parameters for comparison were: power factor, total harmonic distortion (THD), semiconductor losses and magnetic losses, heat-sinks volume and magnetics volume, conducted electromagnetic interference, performance and costs. / Esse trabalho apresenta um estudo e uma análise comparativa de conversores monofásicos aplicados i correção de fator de potência que estejam de acordo com as normas internacionais IEC 61000-3-4 (limitação de harmônicos) e CISPR 22 (limitação dos níveis de interferência eletromagnética) para aplicações de alta potência. Os conversores estudados foram os conversores Boost, o conversor Boost Intercalado, com duas células operando com uma defasagem de 180" entre si, e o conversor Dual Boost. Tais conversores são utilizados como estágio de entrada em fontes de equipamentos da tecnologia da informação. Todos os conversores apresentam a mesma tensão de entrada e saída, e a mesma corrente de entrada. Os conversores foram projetados para apresentarem a mesma taxa de distorção harmônica da corrente de entrada (THD) para que, dessa forma, todos tenham o mesmo filtro de entrada. A implementação das leis de controle foi realizada através de um controlador digital com o uso de um microcontrolador de 16 bits. Todos os conversores foram primeiramente estudados e são apresentados nesta dissertação. Os parâmetros analisados para a comparação das topologias foram: fator de potência, taxa de distorção harmônica, perdas nos dispositivos semicondutores e magnéticos, volume dos dissipadores e materiais magnéticos, interferência eletromagnética conduzida, eficiência e custos.

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Les travaux présentés dans cette thèse s’inscrivent dans le cadre de l’électrification des sous-systèmes embarqués notamment pour des véhicules électriques/hybrides. Dans ce domaine, un des objectifs permanents est la réduction des coûts et des délais lors de la conception de chaînes d’actionnement mécatroniques. Pour y parvenir, il est nécessaire de doter le concepteur de méthodologies et d’outils adaptés lui permettant de fiabiliser sa démarche de conception et de lever le maximum de risques avant de réaliser les premiers prototypes. Ces systèmes mécatroniques embarqués mobilisent des briques technologiques essentielles dont fait partie le convertisseur d’électronique de puissance. Les performances de ce système reposent sur la capacité des méthodologies de conception à considérer les contraintes pluridisciplinaires liées à son environnement, l’adéquation des technologies, des topologies et des lois de commandes. Ces travaux de thèse montrent comment nous pouvons répondre à ces exigences et besoins à travers le développement d’une méthodologie de conception multi-physique et multi-niveau de convertisseurs multicellulaires (entrelacés) prédisposés par essence à une reconfiguration aisée. Cette méthodologie, basée sur une optimisation sous contraintes multi-physiques, permet des choix systématiques d’architecture optimale et des technologies de composants à partir d’une base de données constructeurs. Elle intègre l’aspect fiabilité dans la conception dès la phase de pré-dimensionnement au même niveau que les autres contraintes (électriques, rendement, thermiques, encombrement, compatibilité électromagnétique). Afin de bien profiter des avantages de ce type de convertisseurs entrelacés, cette intégration de la fiabilité dans la conception «fiabilisation par conception» est parachevée par l’élaboration d’une architecture de commande tolérante aux défauts «fiabilisation par la commande» permettant, une fois le convertisseur conçu, d’augmenter sa disponibilité par reconfiguration matérielle ou logicielle (loi de commande). / This PhD thesis work is in the context of electric/hybrid vehicle embedded subsystems electrification. In mechatronic design field, the permanent objectives are costs and delays reducing. To achieve this, there is need of design methodologies and appropriate tools to perform a reliable design approach and leave maximum of risks before making the first prototypes. Embedded mechatronic systems mobilize technological brick keys which include the power electronic converter. Their performances are based on the capacity of the design methodologies to consider the environment multi-disciplinary constraints, the adequacy of the technologies, topologies and control laws. This thesis work shows how we can meet these requirements and needs through the development of multi-physics and multi-level design methodology for multi-level converters (interleaved) predisposed to an easy reconfiguration. This methodology, based on optimization under multi-physics constraints allows systematic choice of optimal architecture and component technologies from manufacturer database. It integrates the reliability aspect in the design since the pre-sizing process in the same level as the other constraints (electric, efficiency, thermal, volume, electromagnetic compatibility). In order take advantages of such interleaved converters, the integration of reliability in the design "reliability by design" is completed by the development of fault tolerant control architecture "reliability by control" which increase the availability by reconfiguring hardware or software (control law) of the designed converter.

Photovoltaic panels are widely used to harvest solar energy. In the general application the panels are connected to an inverter that allows the power to be feed to the grid. The possibility to emulate a photovoltaic panel in a laboratory environment simplifies the development of inverters. Existing solutions are either expensive or not performing good enough. This thesis presents a real-time model that has fast enough transient response to be used with the future’s solar panel inverters. The solution is based on an interleaved synchronous buck converter with an analogue current control loop. A micro-controller is utilizing a look up table to steer the power stage to mimic the output of a real panel. The content of the look up table can be exchanged to emulate an arbitrary photovoltaic panel in different environmental conditions. The emulator output is stable in the load case with a typical inverter connected to it. It is oscillating with a limited amplitude under open circuit. A hardware implementation of the system confirms the functionality. The current controller can correct a load step in 20 μs. The output switching ripple is below 1 mA. / Fotovoltaiska paneler är ett väl etablerat sätt att ta tillvara på solenergi. Den vanligaste tillämpningen är att panelerna är anslutna till en växelriktare för att möjliggöra att energin matas ut på elnätet. Att kunna emulera en solcellspanel i laboratoriemiljö förenklar utvecklingen av växelriktare. Befintliga system är antingen dyra eller presterar inte bra nog. Denna avhandling presenterar en realtidsmodell som kan hantera transienta förlopp tillräckligt snabbt för att kunna användas med framtidens solpanelsväxelriktare. Lösningen är baserad på en tvåfas synkron buck-omvandlare med en analog strömreglering. En mikroprocessor använder uppslagstabell för att styra effektsteget till att efterlikna utsignalen från en verklig panel. Innehållet i uppslagstabellen kan bytas ut för att emulera en godtycklig solpanel i olika driftsförhållanden. Emulatorns utsignal är stabil med en typisk växelriktare ansluten som last. Utsignalen svänger med en begränsad amplitud under öppen krets. Experimentiella tester bekräftar funktionen. Strömregleringen kan korrigera ett belastningssteg inom 20 μs. Utgångens strömrippel är under 1 mA.

Demand for data communication capacity is rapidly increasing with more and more number of users and higher bandwidth services. As a result, a critical research issue is the implementation of wideband and flexible signal processing in communication and sensing applications. Although software defined radio (SDR) is a possible solution, it may not be practical due to the excessive requirements for analog-to-digital converter (ADCs) and digital filters for wideband signals. In this environment, discrete-time (DT) domain circuits are gaining attention in various architectures such as N-path filters, sampling mixers, and analog FIR/IIR/FFT filters. DT analog signal processing (DT-ASP) ahead of an ADC considerably relaxes the ADC requirements by flexible filtering, offers the potential for higher dynamic range performance, and provides robustness in the presence of digital CMOS scaling. The primary work presented in this dissertation is the design of wideband analog finite impulse response (AFIR) filters. Analog FIR filters have been used as low pass filters for out-of-band rejection in narrow-band applications. However, this work seeks to develop AFIR filters suitable for wideband applications, extending its possible applications. To achieve these performance goals, capacitive digital to analog converters (CDACs) have been introduced for the first time as wideband analog coefficient multipliers, which has led to high linearity analog multiplication with coefficient selection at the DAC resolution. A prototype 4th order DT FIR filter has been implemented in 32nm SOI CMOS technology and has achieved low-pass, band-pass, and high-pass filter (LPF, BPF and HPF) transfer functions corresponding to the programmed coefficient sets with IIP3>11dBm linearity and less than 2 mW/tap of power consumption. The AFIR filter is also utilized to demonstrate a proof-of-concept FIR-based beamforming. The beamforming network consisting of 4 antenna element inputs followed by AFIR filters was implemented with PCB modules with the previously fabricated AFIR filter chip. Behavioral simulations are used to verify the beamforming function with given coefficient sets. Based on the developed AFIR filter modules, FIR-based beamforming was demonstrated with measurement results matching well with the simulations. Further work presented is the design and optimization of multi-section CDAC (MS-CDAC) structures. The proposed MS-CDAC approach provides wide range of options to optimize the tradeoff between kT/C noise, linearity versus switching energy, speed and area. When the optimization approach is applied to a proof-of-concept 10-bit CDAC design, the selected MS-CDAC structure reduces total capacitance and switching energy by 97% and 98%, respectively for given linearity and noise limitations. The proposed MS-CDAC structures are applicable in both DT-ASP coefficient multiplier and SAR-ADC applications. / PHD / In communication systems, filter design is a fundamental task required to recover the signal of interest in the presence of interference. As upcoming communication systems, such as 5th generation (5G) mobile communications and future IEEE 802.11 standards (Wi-Fi), require higher speed and flexibility in signal processing due to the rapidly increasing number of users and data rates, it becomes more challenging to design such filters. In general, analog filters are useful for high-speed, digital filters features flexibility. To take advantage of both aspects, discrete-time (DT) domain filters have become a promising alternative, which can be used to implement digital signal processing functions in the analog domain. This dissertation presents the development of DT analog finite-impulse-response (AFIR) filter design for mixed-signal processing applications. The core idea in this work is to adopt the capacitive DAC (CDAC) as a coefficient multiplier, which enables digital code coefficient multiplication as well as high-speed and high-linearity performance while consuming low power. A prototype 4th order DT FIR filter implemented in 32nm SOI CMOS process is demonstrated with measurements. Based on the developed AFIR filters, proof-of-concept FIR-based beamforming is investigated as well. For this purpose, AFIR filter modules are built on printed-circuit-boards (PCBs) and coefficients are calculated by a simplified method. In addition, this dissertation also includes analysis and optimization of multi-section CDAC (MS-CDAC) structures. Traditional CDAC approaches have a fundamental trade-off between noise and linearity versus size, switching energy and speed. This work explores the characteristics of CDACs depending on the section segmentations and the optimal structure is selected based on the trade-off. Through comprehensive simulations and calculations, the selected structure for 10-bit MS-CDAC achieved 97% and 98% reduced total capacitance and switching energy, respectively.

Au sein d'un convertisseur la défaillance d'un composant de puissance est un événement critique tant par le risque d'explosion du boitier et sa propagation au sein du système (forte énergie stockée dans l'alimentation) que par l'interruption de service qui en découle (systèmes embarqués, systèmes de production en flux tendu). Ce mémoire de thèse propose un ensemble de solutions nouvelles portant sur la problématique de l'isolement ultime de défauts "derniers secours" d'une part, et sur la connexion "automatique" et à faible "coût" d'un circuit en secours. L'objectif de cette approche globale est de concilier "sécurité électrique absolue" et "continuité de service" pour les systèmes de conversion sensibles devant être intégrés au coeur des applications critiques. Le premier chapitre et son annexe permettent de rappeler les causes et les conséquences des défauts internes au sein d'une structure de base d'onduleur à deux niveaux de tension, laquelle fait l'objet de nombreuses simulations de modes dégradés en configuration variateur de vitesse sur machine synchrone. De cette analyse il ressort qu'une structure d'isolement symétrique à deux voies couplées, placées sur les pôles du bus DC, à déclenchement spontané (fusible) et/ou commande (rupteur), est à même de sécuriser toutes les mailles du circuit, de façon modulaire et non intrusive. / In all these traditional industries, or in more sensitive sectors and high technology, it appears that the safe operation of power systems becomes a critical and strategic area essential. In the area of application that focuses, design dependability and now rests primarily on an approach to reliability of components used, the use of close protection, monitoring alarms and management stop / reset / recovery. In our view, this approach is incomplete quickly when electrical safety and absolute continuity of a permanent mission should be carried out simultaneously in the presence of an internal failure of sensitive functions for low and medium power (eg, orders and bodies actuation of vehicles) or highly critical (nuclear). In this area, topologies and failure modes are at the heart of the problem. In this paper, we will focus primarily on the inverters and choppers structures at two levels of voltage (single-cell arm, <1kV), with simple configuration and multiphase parallel, although the concepts are presented, as examples, partially extrapolated to the structures of three voltage levels (arms multicellular) and rectifier (low-frequency phase control and high-frequency switching PWM). We will highlight the need to limit the intensity of these failures and to electrically isolate the defective cell and symmetrically of this inverter by multipole devices, passive or spontaneous breaking mixed cut ordered in the form of fuses integrated and distributed of multi-channel passive isolators, to imagine and develop. We will show that this process of isolation of the last backup is needed to connect, form series or parallel to the defective cell, a cell rescue in passive redundancy. The cell structure backup connection pooled by spontaneous (automatic) is especially promising as detailed in our eyes because of its simplicity and its integrability. Next, we present the isolation technologies fuse (not included, miniatures, CMS and multilayer chip fuse), their characteristics, their current limitations and operating in a switching cell test. A methodology and design of symmetrical two-way fuse (dual-fuse) on FR4 PCB - Copper will be presented in Comsol ™ and evaluated initially in static thermal IR. A passive two-way switch, relatively original material for integrating energy embedded in FR4 substrate, will be presented and fully dimensioned plans on electrical, thermal and mechanical also using finite element simulations in Comsol ™. Another aspect of exploratory analysis, mainly experimental, or to characterize the failure modes of bullets and casings ultimate power compared between the technologies of encapsulation by epoxy resin (standard discrete case) and a silicone gel (module) is provided under conditions of stress controlled and reproducible. This step is necessary to characterize the resistive mode of a chip based on faulty stresses and stability over time of the residual strength according to the nature of the encapsulant, ie the very sustainability of this failure mode. A mixed-encapsulant resin - gel will be presented and characterized, providing an excellent compromise for medium power applications. Positive results and little known today, will allow us to exploit in the next chapter, this property of stable ohmic mode of the chip failed in a structure to aid automated connection series interesting. In the end, we will detail the demonstrator prototype and introduced to the context with which we will validate the isolation structures and prototypes fuses the property of stable ohmic mode highlighted in the aspect of technological analysis of selected devices. These results allow us to refine the solutions adopted for specifications and guide future management strategy of defects whether internal or external to the topology. Supervisor digital device - sensor for the detection and reconfiguration of internal control orders will be assessed.

L'apparition de convertisseurs multicellulaires parallèles entrelacés et magnétiquement couplés a conduit ces dernières années à améliorer les performances des convertisseurs (en termes de densité de puissance, d'efficacité, de dynamique,...). Le pendant de ces améliorations successives résulte en une nécessité d'équilibrage précis des courants de phase, ce qui entraîne une complexification de la commande des ces convertisseurs. Une première étape de détermination de la fonction de transfert d'une boucle d'équilibrage des courants nous permet de déterminer la nature des correcteurs d'équilibrage de ces courants. Cette étude nous permet d'appréhender des systèmes plus complexes avec différentes topologies de couplage magnétique entre les bras du convertisseur parallèle. Suite à une étude bibliographique mettant en avant le manque de précision des techniques actuelles de mesure des courants de bras, nous proposons une technique d'émulation analogique précise de ces courants ne nécessitant qu'un seul capteur. Deux prototypes ont été réalisés et permettent de valider cette technique. Enfin, face à l'intérêt grandissant que portent les industriels pour des architectures modulaires, deux innovations permettant de s'affranchir d'un circuit spécifique de supervision sont proposées. Dans un premier temps, une technique modulaire d'équilibrage des courants est proposée et validée expérimentalement : elle permet, entre autres, une mesure différentielle précise des courants de bras. Ensuite, une méthode de génération modulaire de porteuses triangulaires auto-alignées est proposée et validée grâce à la réalisation d'une maquette de test. L'association de ces deux techniques nous permet de proposer une architecture entièrement modulaire ne nécessitant plus de circuit de commande superviseur. / Development of interleaved power converters with coupled inductors has enhanced converters performances (better power density, eciency, transient response. . .). Such improvements lead to the necessity of a precise current-sharing in the converter legs, and consequently to much more complex control strategy for those converters. First step is to determine current sharing loop transfer function in order to choose the kind of sharing corrector and calculate its parameters. State-space representation is used to consider any coupling topology. Because ux induced in coupled inductors must be controlled with accuracy, a bibliography study emphasizes the lack of precision in present current-sensing techniques. Then, a precise analogical emulation of currents in every leg, based on only one current sensor, is proposed. Two prototypes have been developed and validate this approach. Finally, because of growing interest of industrial in modular architectures, two innovations which avoid the use of central specic circuit are presented. First, a masterless and modular current sharing technique is proposed and tested : it allows a very precise dierential current measurement and regulation. Then a modular generation of self-aligned triangular carrier for interleaved converters is proposed and conrmed by test. The association of both techniques leads to a full masterless and modular approach for the control circuit of parallel converter with coupled inductors.

Cost reduction has been and will continue to be a primary driving force in the evolution of hardware design and associated technologies. The objective of this research is to design low-cost signal acquisition systems for characterizing wideband and high-speed signals. As the bandwidth and the speed of such signals increase, the cost of testing also increases significantly; therefore, innovative hardware and algorithm co-design are needed to relieve this problem. In Chapter 2, a low-cost multi-rate system is proposed for characterizing the spectra of wideband signals. The design is low-cost in the sense of the actual component cost, the system complexity, and the effort required for calibration. The associated algorithms are designed such that the hardware can be implemented with low-complexity yet be robust enough to deal with various hardware variations. A hardware prototype is built not only to verify the proposed hardware scheme and algorithms but to serve as a concrete example that shows that characterizing signals with sub-Nyqusit sampling rate is feasible. Chapter 3 introduces a low-cost time-domain waveform reconstruction technique, which requires no mutual synchronization mechanisms. This brings down cost significantly and enables the implementation of systems capable of capturing tens of Gigahertz (GHz) signals for significantly lower cost than high-end oscilloscopes found in the market today. For the first time, band-interleaving and incoherent undersampling techniques are combined to form a low-cost solution for waveform reconstruction. This is enabled by co-designing the hardware and the back-end signal processing algorithms to compensate for the lack of coherent Nyquist rate sampling hardware. A hardware prototype was built to support this work. Chapter 4 describes a novel test methodology that significantly reduces the required time for crosstalk jitter characterization in parallel channels. This is done by using bit patterns with coprime periods as channel stimuli and using signal processing algorithms to separate multiple crosstalk coupling effects. This proposed test methodology can be applied seamlessly in conjunction with the current test methodology without re-designing the test setup. More importantly, the conclusion derived from the mathematical analysis shows that only such test stimuli give unbiased characterization results, which are critical in all high-precision test setups. Hardware measurement results and analysis are provided to support this methodology. This thesis starts with an overview of the background and a literature review. Three major previously mentioned works are addressed in three separate chapters. Each chapter documents the hardware designs, signal processing algorithms, and associated mathematical analyses. For the purpose of verification, the hardware measurement setups and results are discussed at the end of these three chapters. The last chapter presents conclusions and future directions for work from this thesis.

There is an increasing demand for power converters with small size, light weight, high conversion efficiency and higher power density. Also, in many applications, there is a need for dc-to-dc converters to accept dc input voltage and provide regulated and/or isolated dc output voltage at a desired voltage level including telecommunications equipment, process control systems, and in industry applications. This thesis presents the analysis, design, simulation and experimental results of three-phase high-frequency transformer isolated resonant converters. The first converter presented is a three-phase LCC-type dc-dc resonant converter with capacitor output filter including the effect of the magnetizing inductance of the three-phase HF transformer. The equivalent ac load resistance is derived and the converter is analyzed by using approximation analysis approach. Base on this analysis, design curves have been obtained and a design example is given. Intusoft simulation results for the designed converter are given for various input voltage and for different load conditions. The experimental verification of the designed converter performance was established by building a 300 W rated power converter and the experimental results have been given. It is shown that the converter works in zero-voltage switching (ZVS) at various input voltage and different load conditions. A three-phase (LC)(L)-type dc-dc series-resonant converter with capacitive output filter has been proposed. Operation of the converter has been presented using the operating waveforms and equivalent circuit diagrams during different intervals. An approximate analysis approach is used to analyze the converter operation, and design procedure is presented with a design example. Intusoft simulation results for the designed converter are given for input voltage and load variations. Experimental results obtained in a 300 W converter are presented. Major advantages of this converter are the leakage and magnetizing inductances of the high-frequency transformer are used as part of resonant circuit and the output rectifier voltage is clamped to the output voltage. The converter operates in soft-switching for the inverter switches for the wide variations in supply voltage and load and it requires narrow switching frequency variation (compared to LCC-type) to regulate the output voltage. A three-phase high-frequency transformer isolated interleaved (LC)(L)-type dc-dc series-resonant converter with capacitive output filter using fixed frequency control is proposed. The converter operation for different modes is presented using the operating waveforms and equivalent circuit diagrams during different intervals. This converter is modeled and then analyzed using the approximate complex ac circuit analysis approach. Based on the analysis, design curves were obtained and the design procedure is presented with a design example. The designed converter is simulated using PSIM software to predict the performance of the converter for variations in supply voltage and load conditions. The converter operates in ZVS for the inverter switches with minimum input voltage and loses ZVS for two switches in each bridge for higher input voltages. / Graduate