Les besoins en débit d’information à transmettre ne cessent de croitre. Aussi la généralisation des émetteurs-récepteurs large-bande implique l’intégration de solutions sur une technologie silicium CMOS afin que leur cout soit compatible avec une application grand public. Si l’intégration massive des traitements numériques est facilitée par les dernières technologies CMOS, la fonction de conversion analogique-numérique est quant à elle plus difficile. En effet, afin d’optimiser l’étage frontal analogique, le convertisseur analogique-numérique (CAN) doit répondre à des contraintes très fortes en termes de largeur de bande (de l’ordre du GHz) et de résolution (de 10 à 14bits). Les convertisseurs analogique-numérique basés sur l’entrelacement temporel (CAN-ET) connaissent un essor remarquable car ce sont aujourd’hui les seuls à pouvoir répondre aux deux contraintes énoncées ci-dessus. Cependant, cette structure de CAN reste sensible aux défauts d’appariement entre ses différentes voies de conversion et voit ses performances limitées par la présence de raies parasites liées à des erreurs statiques (offset et gain) et dynamiques (skew et bande passante). Pour réduire l’impact des erreurs dynamiques, nous avons implémenté une calibration mixte en technologie FD-SOI 28nm. Dans une première partie, un état de l’art portant sur les différentes techniques de minimisation et de compensations analogiques des erreurs de skew et bande passante est réalisé. A partir de cette étude, nous proposons différentes techniques analogiques pour compenser les d´esappariements de bande passante et de skew. Pour compenser le skew, nous profitons des avantages de la technologie FD-SOI en modulant fortement la tension de la face arrière d’un ou plusieurs transistor(s) d’ échantillonnage. Concernant l’erreur de bande passante, nous proposons d’ajuster la résistance équivalente du T/H en adaptant la résistance à l’état passant des transistors d’échantillonnage de cinq manières différentes. Pour définir parmi toutes les compensations proposées celle qui est la plus adaptée à nos besoins, nous comparons différents critères de performance. Après avoir identifié la meilleure compensation de skew et de bande passante, nous avons, dans une dernière partie, implémenté une calibration mixte des erreurs statiques et dynamiques o`u l’estimation numérique est basée sur la méthode des Moindres Carrés. / Data transmission requirements are ever more stringent, with respect to more throughput, less power consumption and reduced cost. The cable TV market is where broadband transceivers must continuously innovate to meet these requirements. In these transceivers, the analog front-end part must be adapted to meet the increasingly tighter specifications of the newest standards. A key bottleneck is the Analogto- Digital Converter (ADC), which must reach a sampling rate of several Gigasamples per second at effective conversion resolutions in the range of 10 to 14 bits. Among the possible choices, converters based on Time-Interleaving (TI-ADC) are experiencing remarkable growth, and today they appear to be the best candidates to rmeet the two constraints set out above. However, TI-ADCs are hampered by mismatches between its different conversion channels, which result in degraded performance due to the appearance of mismatch spurs in the frequency domain, arising both from static errors (gain and offset mismatch) and dynamic (skew and bandwidth) errors. To reduce these errors, we have investigated a mixeddomain calibration strategy for TI-ADCS in 28nm FDSOI technology. We strongly focused the analog compensation of dynamic errors. This report begins with a review of the state-of-theart w.r.t. the mismatch reduction and analog compensation techniques for both dynamic errors. Based on these results, we then introduce a variety of analog techniques aimed at compensating the bandwidth and skew mismatches. In order to compensate for the skew, we make the most of the FD-SOI technology by tightly regulating the voltage of the back gate of one or several sampling transistors. For the bandwidth error, we recommend that the T/H equivalent resistor be adjusted, adapting the on-resistor of the sampling transistors using up to five different techniques. Once the most appropriate skew and bandwidth compensations were identified, we ultimately implemented a mixed calibration of static and dynamic errors along with a digital calculation based upon the "Least- Squares" method.

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Resultat från TIMS (Trends in International Mathematics and Science Study, 2019) visar att svenska elever presterar under genomsnittet i matematik både i årskurs fyra och i årskurs åtta. År 2020 sammanfattade Skolinspektionen tre områden som är avgörande för bättre kvalitet i skolan och som sammanfaller väl med bland annat testbaserat lärande. Skolinspektionens (2020) sammanfattning och testbaserat lärandets gemensamma nämnare är vikten av att ha tydliga lärandemål, skapa en varierad och anpassad undervisning som ger elever stimulans och utmaningar efter varje elevs förutsättningar, med stöd av läraren, samt betydelsen av elevers delaktighet och möjlighet till formativa återkoppling.  Mot den bakgrunden samt att det finns grundlig forskning kring testbaserat lärande som högeffektiv inlärningsstrategi analyserades sex lärares erfarenheter av implementeringsarbetet kring testbaserat lärande. Utöver det gjordes en kvantitativ studie inom testbaserat lärande i ämnet matematik. Studien utgår från kognitionsteori och har lärarperspektiv samt en teoretisk referensram i litteratur och artiklar från främst de senaste årtiondena. Efter implementeringen av testbaserat lärande intervjuades sex lärare på en F-6 skola vars undervisning (minst 75 procent av undervisningstillfällena) hade innehållit minst en testbaserad uppgift per lektion under sex veckor. Uppsatsens kvalitativa studie visade lärarnas reaktioner efter implementeringsperioden. De uttryckte en trygghet och motivation i implementeringsarbetet samt hur deras lektionsdesign hade förändrats genom återhämtningsaktiviteterna. De sex lärarna förmedlade också en överraskande positiv upplevelse kring den återkoppling som de testbaserade aktiviteterna gav eleven och läraren, med större möjlighet för läraren att justera sin undervisning för högre måluppfyllelse.Den kvantitativa studien som gjordes i ämnet matematik (aritmetik) i årskurs fyra och fem under en sex-veckors period var en mix av testbaserat lärande (retrieval practice) och delvis inflätat lärande (interleaved practice). Studien med de förutsättningar som gavs visade att testbaserade aktiviteter adderat till delvis inflätat lärande inte höjde resultaten i interventionsgruppen. Vid analysen framkom olika anledningar till resultatet som till exempel utformning och frekvens av de testbaserade aktiviteterna i planeringsschemat, lärarna och elevernas oerfarenhet inom området samt val av interventionsgrupp. / Results from TIMS (Trends in International Mathematics and Science Study, 2019) show that Swedish students perform below average in mathematics for, both in grade four and in grade eight. In 2020, the Skolinsepktionen summarized three areas that are crucial for better quality in schools and that coincide well with, among other things, retrieval practice. Skolverket's (2022) summary and retrieval practice common denominator is the importance of having clear learning goals, creating varied and adapted teaching that gives students stimulation and challenges according to each student's conditions, with the support of the teacher, as well as the importance of student participation and the opportunity for formative feedback. With that background and the fact that there is thorough research on retrieval practice as a highly effective learning method, six teachers' experiences of the implementation work of retrieval practice are analyzed in this essay. In addition to that, a quantitative study is carried out in test-based learning in the subject of mathematics. The study is based on cognitive theory and has a teacher's perspective as well as a theoretical frame of reference in literature and articles from mainly recent decades.  After the implementation of retrieval practice, six teachers were interviewed at an F-6 school whose instruction (at least 75% of the time) had included at least one retrieval practice activity per lesson for six weeks. The essay's qualitative study shows the teachers' positive reactions after the implementation period. They also express a sense of security and motivation in the implementation work and how their lesson design has changed through the recovery activities. The six teachers also convey a surprisingly positive experience regarding the feedback that the retrieval practice activities provide to the student and the teacher, with greater opportunity for the teacher to adjust their teaching for higher goal achievement. The quantitative study that is done in the subject of mathematics (arithmetic) in grades four and five during a six-week period is a mix of retrieval practice and interleaved practice. The study with the conditions provided showed that retrieval practice activities added to interleaved practice did not increase the results in the intervention group. During the analysis, various reasons emerged for the result, such as the design of the retrieval practices activities, frequency of the retrieval practices activities in the planning schedule, the teachers' and students' inexperience in the field, and the choice of intervention group.

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I det här arbetet har variationen av närliggande övningsuppgifter i svenska matematikläromedel för gymnasiet studerats, genom att framförallt betrakta förekomsten av inflätad övning och dess motsats, blockövning, men även SSDD-uppgifter. Detta gjordes genom att kategorisera uppgifternas yt- och djupstrukturer och definiera inflätad övning och SSDD-uppgifter utifrån likhet och olikhet av dessa. En diskussion av vilka konsekvenser den observerade variationen kan ha för lärande har också gjorts, genom teoretiska perspektiv av relevans för inflätad övning, vilka främst varit distribuerat lärande, kontrastering och motivation. Resultaten visar att blockövning dominerar med 65 % av lektionsuppgifterna, mot 14 % inflätad övning, men att denna uppdelning varierar mycket. Inflätad övning är koncentrerad till de blandade övningarna i slutet på varje kapitel, och till ett fåtal avsnitt, medan nästan hälften av avsnitten inte har några inflätade övningar. SSDD-uppgifter finns nästan inte alls. Konsekvenserna är främst ett kortsiktigt lärande som inte ger eleverna tillräckligt med övning i att välja strategi när de ska lösa uppgifter, jämfört med om en högre grad av inflätad övning hade använts.

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Impulse Ultra Wideband (UWB) communications is an emerging technology that promises a number of benefits over traditional narrowband or broadband signals: extremely high data rates, extremely robust operation in dense multipath environments, low probability of intercept/detection, and the ability to operate concurrently with existing users. Unfortunately, most currently available UWB systems are based on dedicated hardware, preventing researchers from investigating algorithms or architectures that take advantage of some of the unique properties of UWB signals. This dissertation outlines the development of a general purpose software radio transceiver testbed for UWB signals. The testbed is an enabling technology that provides a development platform for investigating ultra wideband communication algorithms (e.g., acquisition, synchronization, modulation, multiple access), ranging or radar (e.g., precision position location, intrusion detection, heart and respiration rate monitoring), and could potentially be used in the area of ultra wideband based medical imaging or vital signs monitoring. As research into impulse ultra wideband expands, the need is greater now than ever for a platform that will allow researchers to collect real-world performance data to corroborate theoretical and simulation results. Additionally, this dissertation outlines the development of the Time-Interleaved Analog to Digital Converter array which served as the core of the testbed, along with a comprehensive theoretical and simulation-based analysis on the effects of Analog to Digital Converter mismatches in a Time-Interleaved Sampling array when the input signal is an ultra wideband Gaussian Monocycle. Included in the discussion is a thorough overview of the implementation of both a scaled-down prototype as well as the final version of the testbed. This dissertation concludes by evaluating the of the transceiver testbed in terms of the narrowband dynamic range, the accuracy with which it can sample and reconstruct a UWB pulse, and the bit error rate performance of the overall system. / Ph. D.

Over the past ten years, there has been increased use of electronic power processing in alternative, sustainable, and distributed energy sources, as well as energy storage systems, transportation systems, and the power grid. Three-phase voltage source converters (VSCs) have become the converter of choice in many ac medium- and high-power applications due to their many advantages, such as high efficiency and fast response. For transportation applications, high power density is the key design target, since increasing power density can reduce fuel consumption and increase the total system efficiency. While power electronics devices have greatly improved the efficiency, overall performance and power density of power converters, using power electronic devices also introduces EMI issues to the system, which means filters are inevitable in those systems, and they make up a significant portion of the total system size and cost. Thus, designing for high power density for both power converters and passive components, especially filters, becomes the key issue for three-phase converters. This dissertation explores two different approaches to reducing the EMI filter size. One approach focuses on the EMI filters itself, including using advanced EMI filter structures to improve filter performance and modifying the EMI filter design method to avoid overdesign. The second approach focuses on reducing the EMI noise generated from the converter using a three-level and/or interleaving topology and changing the modulation and control methods to reduce the noise source and reduce the weight and size of the filters. This dissertation is divided into five chapters. Chapter 1 describes the motivations and objectives of this research. After an examination of the surveyed results from the literature, the challenges in this research area are addressed. Chapter 2 studies system-level EMI modeling and EMI filter design methods for voltage source converters. Filter-design-oriented EMI modeling methods are proposed to predict the EMI noise analytically. Based on these models, filter design procedures are improved to avoid overdesign using in-circuit attenuation (ICA) of the filters. The noise propagation path impedance is taken into consideration as part of a detailed discussion of the interaction between EMI filters, and the key design constraints of inductor implementation are presented. Based on the modeling, design and implementation methods, the impact of the switching frequency on EMI filter weight design is also examined. A two-level dc-fed motor drive system is used as an example, but the modeling and design methods can also be applied to other power converter systems. Chapter 3 presents the impact of the interleaving technique on reducing the system passive weight. Taking into consideration the system propagation path impedance, small-angle interleaving is studied, and an analytical calculation method is proposed to minimize the inductor value for interleaved systems. The design and integration of interphase inductors are also analyzed, and the analysis and design methods are verified on a 2 kW interleaved two-level (2L) motor drive system. Chapter 4 studies noise reduction techniques in multi-level converters. Nearest three space vector (NTSV) modulation, common-mode reduction (CMR) modulation, and common-mode elimination (CME) modulation are studied and compared in terms of EMI performance, neutral point voltage balancing, and semiconductor losses. In order to reduce the impact of dead time on CME modulation, the two solutions of improving CME modulation and compensating dead time are proposed. To verify the validity of the proposed methods for high-power applications, a 100 kW dc-fed motor drive system with EMI filters for both the AC and DC sides is designed, implemented and tested. This topology gains benefits from both interleaving and multilevel topologies, which can reduce the noise and filter size significantly. The trade-offs of system passive component design are discussed, and a detailed implementation method and real system full-power test results are presented to verify the validity of this study in higher-power converter systems. Finally, Chapter 5 summarizes the contributions of this dissertation and discusses some potential improvements for future work. / Ph. D.

AC and DC impedances of switching power converters are used for the stability analysis of modern power electronics systems at three-phase AC and single-phase DC interfaces. Therefore, a small-signal characterization algorithm for switching power converter, which is based on FFT, will be presented and explained. The presented extraction algorithm is general and can be used to obtain other small-signal transfer functions of arbitrary power converter switching simulation models. Furthermore, FFT algorithm is improved by using cross power spectral density functions for identification, resulting in an algorithm, which is more noise immune. Both small-signal identification algorithms are validated in simulations, and CPSD algorithm is used in experimental measurement procedure. Several wide bandwidth injection signals, among which are chirp, multi-tone, pulse and white noise, are compared and theoretically analyzed. Several hardware examples are included in the analysis. The second part of the dissertation will focus on the modeling of small-signal input dq admittance of multi-pulse diode rectifiers, providing comparison between well-known averaged value models (AVMs), parametric averaged value models (PAVM), the switching simulation model and hardware measurements. Analytical expressions for all four admittances present in the dq matrix are derived and analyzed in depth, revealing the accuracy range of the averaged models. Furthermore, a hardware set-up is built, measured and modeled, showing that the switching simulation model captures nonlinear sideband effects accurately. In the end, a multi-pulse diode rectifier feeding a constant power load is analyzed with modified AVM and through detailed simulations of switching model, proving effectiveness of the proposed modifications. The third part describes implementation and design of a single-phase multi-level single-phase shunt current injection converter based on cascaded H-bridge topology. Special attention is given toward the selection of inductors and capacitors, trying to optimize the selected component values and fully utilize operating range of the converter. The proposed control is extensively treated, including inner current, outer voltage loop and voltage balancing loops. The designed converter is constructed and integrated with measurement system, providing experimental verification. The proposed multi-level single-phase converter is a natural solution for single-phase shunt current injection with the following properties: modular design, capacitor energy distribution, reactive element minimization, higher equivalent switching frequency, capability to inject higher frequency signals, suitable to perturb higher voltage power systems and capable of generating cleaner injection signals. Finally, a modular interleaved single-phase series voltage injection converter, consisting of multiple paralleled H-bridges is designed and presented. The decoupling control is proposed to regulate ac injection voltage, providing robust and reliable strategy for series voltage injection. The designed converter is simulated using detailed switching simulation model and excellent agreement between theory and simulation results are obtained. The presented control analysis treats different loads, examining robustness of the circuit to load variations. Simulation model and hardware prototype results verify the effectiveness of the proposed wide-bandwidth identification of small-signal dq impedances via single-phase injections. / Ph. D.

Transients encountered by transformers in power stations during normal operation can have complex oscillatory overvoltages containing a large spectrum of frequency components. These transients can coincide with the natural frequencies of the transformers windings, leading to voltages that can be greater or more severe than the current factory proof tests. This may lead to insulation breakdown and catastrophic failures. Existing lumped parameter RLCG transformer models have been proven to be less accurate for very fast transient overvoltages (VFTO) with frequencies over 1 MHz. A white box model for transient analysis of transformer windings has been developed using Multiconductor Transmission Line (MTL) Theory. This model enables the simulation of natural frequencies of the transformer windings up to frequencies of several MHz, and can be used to compute voltages between turns by representing each turn as a separate transmission line. Both continuous and interleaved disk windings have been modelled and a comparison and validation of the results is presented. / May 2017