In the European research projects SIAM and 100GET, building blocks for 100Gbit Ethernet optical link have been implemented. Data are sent from a computer, modulated, converted to analog, mixed onto the RF-band, sent through an optical link, down-mixed, converted back to digital, demodulated and sent to a receiving computer. Signal Processing Devices Sweden AB is contributing to this project by their implementation PANDA. This thesis has been to study, as a proof of concept, and implement a prototype of PANDA as the component converting from digital to analog signal, the DAC, in 65nm SOI CMOS technology. The idea of the system is to use the concept of time interleaving, where two or more components interact by performing the same operations on a different set of data, ideally scaling the performance linearly with the amount of components used. This report presents design, implementation and verification at simulation level. It includes interfacing with off-chip components in low voltage specifications, clock generation, filtering and current-steered switches.

Power line communications (PLC) surfers performance degradation due mainly to impulsive noise interference generated by electrical appliances. This thesis studies coded modulation techniques to improve the spectral efficiency and error performance of PLC. Considered in the first part is the application of bit-interleaved coded modulation with iterative decoding (BICM-ID) in class-A impulsive noise environment. In particular, the optimal soft-output demodulator and its suboptimal version are presented for an additive class-A noise (AWAN) channel so that iterative demodulation and decoding can be performed at the receiver. The effect of signal mapping on the error performance of BICM-ID systems in impulsive noise is then investigated, with both computer simulations and a tight error bound on the asymptotic performance. Extrinsic information transfer (EXIT) chart analysis is performed to illustrate the convergence properties of different mappings. The superior performance of BICMID compared to orthogonal frequency-division multiplexing (OFDM) is also clearly demonstrated.<p>Motivated by the successes of both BICM-ID and OFDM in improving the error performance of communications systems in impulsive noise environment, the second part of this thesis introduces a novel scheme of bit-interleaved coded OFDM with iterative decoding (BI-COFDM-ID) over the class-A impulsive noise channel. Here, an iterative receiver composed of outer and inner iteration loops is first described in detail. Error performance improvements of the proposed iterative receiver with different iteration strategies are presented and discussed. Performance comparisons of BI-COFDM-ID, BICM-ID and iteratively decoded OFDM are made to illustrate the superiority of BI-COFDM-ID. The effect of signal mapping on the error performance of BI-COFDM-ID is also studied.

Σκοπός της διπλωματικής είναι η μελέτη ενός τηλεπικοινωνιακού συστήματος αποτελούμενου από συνελικτικό κωδικοποιητή, interleaver, qam διαμορφωτή, κανάλι με παρουσία συσχετισμένου Gaussian θορύβου, soft qam αποδιαμορφωτή, deinterleaver και αποκωδικοποιητή Viterbi. Ιδιαίτερη έμφαση δίνεται στην απόδοση του interleaving/symbol παρουσία συσχετισμένου θορύβου. Μελετάται η απόδοση στο BER, η πολυπλοκότητα, το κόστος υλικού καθώς και χρονική καθυστέρηση του παραπάνω συστήματος σε σχέση με ένα αντίστοιχο σύστημα που υλοποιεί interleaving/bit παρουσία συσχετισμένου θορύβου. / The aim of the thesis is to study a telecommunications system consisting of convolutional encoder, interleaver, qam modulator, channel in the presence of correlated Gaussian noise, soft qam demodulator, deinterleaver, and decoder Viterbi. Particular emphasis is placed on the performance of interleaving/symbol presence of correlated noise. Studied the performance of the BER, the complexity, cost of material and time delay of the above system with respect to a corresponding system that implements interleaving/bit presence of correlated noise.

Main goal of this dissertation is read over principal and properties of the OFDM modulation. Onward we become acquainted with basic methods for PAPR dynamics reduction in OFDM such as Clipping or Interleaving. Simulation of reduction methods will be realized in Scilab environment, in which are made basic functions for OFDM modulator and demodulator. Furthermore there are created functions for PAPR reduction methods. All established functions are implemented in the GUI.

Power density has become increasingly important for applications where weight and space are limited. Power density is a unique challenge requiring the latest transistor technology to push switching frequency to shrink passive filter size. Furthermore, while high efficiency is an important thermal handling strategy, it must be weighed against increases in component size. Google's Little Box Challenge shone light on these challenges in pushing the power density of a 2kW inverter. The rise in electric vehicle infrastructure and demand represents a unique application for power electronics: pushing the power handling capability and functionality of bi-directional, on-board electric vehicle chargers for faster charging while simultaneously shrinking them in size. New wide-bandgap (WBG) devices, combined with soft-switching, now allow inverters to shrink in size by pushing to higher switching frequencies while maintaining efficiency. Classic H-Bridge topologies have limited switching frequency due to hard switching. Soft switching allows inverters to operate at higher frequency while minimizing switching loss. Concurrently, interleaving can reduce current handling stress and conduction loss better than simply paralleling two transistors. A novel interleaved auxiliary resonant snubber for high-frequency soft-switching is introduced. The design of an auxiliary resonant snubber is discussed; this allows the main GaN MOSFETs to achieve zero voltage switching (ZVS). The auxiliary switches and SiC diodes achieve zero current switching (ZCS). This soft-switching strategy can be applied to any modulation scheme. Here, it is applied to an asymmetrical unipolar H-bridge with two high frequency legs interleaved. While soft-switching minimizes switching loss, conduction loss is simultaneously reduced for high-power applications by interleaving two high frequency legs. This topology is chosen for its conduction loss reduction and bi-directional capability. / Master of Science

La problématique traitée dans la thèse consiste à concevoir des convertisseurs très larges bandes pour les applications stations de base. Le choix d'une architecture à entrelacement temporel a été fait et permet d’augmenter la vitesse des convertisseurs tout en ayant un contrôle sur la consommation. Cependant, les canaux constituant cette architecture évoluent différemment à des variations d'environnement. En conséquence, des erreurs d’appariement entre les canaux dégradent les performances du convertisseur parallèle. Les erreurs les plus connues sont : l’offset, le gain, l’erreur de phase des horloges d’échantillonnage qui sont largement traitées dans la littérature et enfin, l'erreur de bande passantes entre les filtres d'entrées des convertisseurs. Les travaux de la thèse ont permis de proposer des solutions d'estimation et de correction de cette erreur de bande passante afin d'améliorer les performance en linéarité du convertisseur. De plus les techniques de calibrage proposées sont validées à l'aide de circuits réels. / Time-interleaved converter (ti-adc) is an efficient way to increase the speed while maintaining a good accuracy. it consists of the parallelization of several channels; each one running at lower speed. The benefit of this approach is to increase the conversion bandwidth without increasing the power. however, mismatches between the channels cause errors at the digital output and degrade the linearity and the resolution of the system. Gain, offset and clock skew errors are widely treated and we have been interested on bandwidth mismatch error which appears at high frequencies. The goal of the thesis is to develop and implement background calibration techniques for bandwidth mismatch error in a high speed ti-adc (up to 500 msps) in order to achieve a 90 db of sfdr for high input frequencies (up to 385mhz) and up to 94 db at low frequencies. An analog correction solution based on randomization was proposed and a new estimation technique based on gain extraction was implemented and validated for wideband signal.

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Three-phase voltage source converters(VSCs) have become the converter of choice in many ac medium and high power applications due to their many advantages, including low harmonics, high power factor, and high efficiency. Modular VSCs have also been a popular choice as building blocks to achieve even higher power, primarily through converter paralleling. In addition to high power ratings, paralleling converters can also provide system redundancy through the so-called (N+1) configuration for improved availability, as well as allow easy implementation of converter power management. Interleaving can further improve the benefit of paralleling VSCs by reducing system harmonic currents, which potentially can increase system power density. There are many challenges to implement interleaving in paralleled VSCs system due to the complicated relationships in a three-phase power converter system. In addition, to maximize the benefit of interleaving, current knowledge of symmetric interleaving is not enough. More insightful understanding of this PWM technology is necessary before implement interleaving in a real paralleled VSCs system. In this dissertation, a systematic methodology to analyze and design a paralleled three-phase voltage source converters with interleaving is developed. All the analysis and proposed control methods are investigated with the goal of maximizing the benefit of interleaving based on system requirement. The dissertation is divided into five sections. Firstly, a complete analysis studying the impact of interleaving on harmonic currents in ac and dc side passive components for paralleled VSCs is presented. The analysis performed considers the effects of modulation index, pulse-width-modulation (PWM) schemes, interleaving angle and displacement angle. Based on the analysis the method to optimize interleaving angle is proposed. Secondly, the control methods for the common mode (CM) circulating current of paralleled three-phase VSCs with discontinuous space-vector modulation (DPWM) and interleaving are proposed. With the control methods, DPWM and interleaving, which is a desirable combination, but not considered possible, can be implemented together. In addition, the total flux of integrated inter-phase inductor to limit circulating current can be minimized. Thirdly, a 15 kW three phase ac-dc rectifier is built with SiC devices. With the technologies presented in this dissertation, the specific power density can be pushed more than 2kW/lb. Fourthly, the converter system with low switching frequency is studied. Special issues such as beat phenomenon and system unbalance due to non-triplen carrier ratio is explained and solved by control methods. Other than that, an improved asymmetric space vector modulation is proposed, which can significantly reduce output current total harmonic distortion (THD) for single and interleaved VSCs system. Finally, the method to protect a system with paralleled VSCs under the occurrence of internal faults is studied. After the internal fault is detected and isolated, the paralleled VSCs system can continue work. So system reliability can be increased. / Ph. D.

Over the past ten years, there has been increased use of electronic power processing in alternative, sustainable, and distributed energy sources, as well as energy storage systems, transportation systems, and the power grid. Three-phase voltage source converters (VSCs) have become the converter of choice in many ac medium- and high-power applications due to their many advantages, such as high efficiency and fast response. For transportation applications, high power density is the key design target, since increasing power density can reduce fuel consumption and increase the total system efficiency. While power electronics devices have greatly improved the efficiency, overall performance and power density of power converters, using power electronic devices also introduces EMI issues to the system, which means filters are inevitable in those systems, and they make up a significant portion of the total system size and cost. Thus, designing for high power density for both power converters and passive components, especially filters, becomes the key issue for three-phase converters. This dissertation explores two different approaches to reducing the EMI filter size. One approach focuses on the EMI filters itself, including using advanced EMI filter structures to improve filter performance and modifying the EMI filter design method to avoid overdesign. The second approach focuses on reducing the EMI noise generated from the converter using a three-level and/or interleaving topology and changing the modulation and control methods to reduce the noise source and reduce the weight and size of the filters. This dissertation is divided into five chapters. Chapter 1 describes the motivations and objectives of this research. After an examination of the surveyed results from the literature, the challenges in this research area are addressed. Chapter 2 studies system-level EMI modeling and EMI filter design methods for voltage source converters. Filter-design-oriented EMI modeling methods are proposed to predict the EMI noise analytically. Based on these models, filter design procedures are improved to avoid overdesign using in-circuit attenuation (ICA) of the filters. The noise propagation path impedance is taken into consideration as part of a detailed discussion of the interaction between EMI filters, and the key design constraints of inductor implementation are presented. Based on the modeling, design and implementation methods, the impact of the switching frequency on EMI filter weight design is also examined. A two-level dc-fed motor drive system is used as an example, but the modeling and design methods can also be applied to other power converter systems. Chapter 3 presents the impact of the interleaving technique on reducing the system passive weight. Taking into consideration the system propagation path impedance, small-angle interleaving is studied, and an analytical calculation method is proposed to minimize the inductor value for interleaved systems. The design and integration of interphase inductors are also analyzed, and the analysis and design methods are verified on a 2 kW interleaved two-level (2L) motor drive system. Chapter 4 studies noise reduction techniques in multi-level converters. Nearest three space vector (NTSV) modulation, common-mode reduction (CMR) modulation, and common-mode elimination (CME) modulation are studied and compared in terms of EMI performance, neutral point voltage balancing, and semiconductor losses. In order to reduce the impact of dead time on CME modulation, the two solutions of improving CME modulation and compensating dead time are proposed. To verify the validity of the proposed methods for high-power applications, a 100 kW dc-fed motor drive system with EMI filters for both the AC and DC sides is designed, implemented and tested. This topology gains benefits from both interleaving and multilevel topologies, which can reduce the noise and filter size significantly. The trade-offs of system passive component design are discussed, and a detailed implementation method and real system full-power test results are presented to verify the validity of this study in higher-power converter systems. Finally, Chapter 5 summarizes the contributions of this dissertation and discusses some potential improvements for future work. / Ph. D.