International Telemetering Conference Proceedings / October 25-28, 1999 / Riviera Hotel and Convention Center, Las Vegas, Nevada / Most traditional approaches to TT&C have employed waveforms that are neither very power nor bandwidth efficient. A new approach to TT&C waveforms greatly improves these efficiencies. Binary Gaussian Minimum Shift Keying (GMSK) provides a constant envelope bandwidth efficient signal for applications above about 10 Kbps. The constant envelope preserves the spectrum through saturated amplifiers. It provides the best power efficiency when used with turbo coding. For protection against various kinds of burst errors it includes the hybrid interleaving for memory and delay efficiency and packet compatible operations in Time Division Multiple Access (TDMA) environments. Commanding, telemetry, mission data transmission, and tracking are multiplexed in TDMA format.

Recent portable electronic technologies require the power management circuit be efficient, small and cost effective. The switched-capacitor (SC) converter provides a trade-off between the efficiency, the size and the cost that is desirable in many of these new portable technologies. This dissertation investigates different circuit techniques and SC converter topologies to make the SC converters fully adapt to the portable system requirements. To make the SC converter efficient over a wide range of input and output voltages, a family of SC power stages with multiple gain ratio (GR) is developed. Multiple GR allows the converter to provide step-down or step-up voltage conversion while increasing the average efficiency of the converter. These power stages are also capable of providing interleaving regulation that has been proved to be effective in reducing the input and the output noise of the converter. Unlike conventional interleaving, the technique developed in this research uses fewer switches and capacitors. The research also contributes in developing circuit techniques such as charge recycling in the bottom plate parasitic capacitors, local gate driving and adaptive body biasing to reduce the power loss in monolithic SC converter implementation. To control the SC power stage for accurate regulation and fast transient response, a control scheme named adaptive gain/pulse control is developed. The research also investigates the use of multipath compensation scheme in SC converters for ultra fast and low noise performance. The techniques and the topologies developed for SC converters in this research can be effectively implemented in the portable devices to reduce cost, and improve efficiency which leads to longer battery life and circuit implementation using smaller areas.

Approved for public release; distribution is unlimited / In the past ten years reliable high-speed satellite systems have pushed slower less reliable communication systems to the bottom of the list for development programs. Concern over reduced budgets, vulnerability of expensive satellite systems, and recent advances in HF technology are creating new interest in upgrading existing HF communication systems. Nondevelopment Items (NDI) are defined as the use of off-the-shelf commercial items instead of costly, time-consuming conventional research and development programs. The Navy Department's current policies are designed to insure the maximum use of NDI to fulfill Navy requirements. The speed of HF systems can be improved using current signaling and modulation techniques, and reliability can be increased by error-correcting codes or error detection used in conjunction with automatic repeat request (ARQ) schemes. Improved HF systems not only provide survivable back-up capability, but increased capacity for present communication needs. / http://archive.org/details/longhaulcommunic00elli / Lieutenant, United States Navy

Este trabalho apresenta um novo algoritmo, denominado Intercalamento Temporal por Transformada de Fourier (FTI), desenvolvido para complementar sistemas de modulação digital. Com este processo, a informação é distribuida de forma difusa ao longo de um conjunto de símbolos, tanto no domínio do tempo como no da frequência. Constitui-se em um processo computacionalmente eficiente, especialmente adequado para operar em conjunto com a modulação OFDM, e que apresenta consideráveis ganhos de desempenho em algumas situações de degradação; por exemplo, é mais tolerante a ruídos impulsivos de longa duração do que a modulação OFDM convencional. Apresenta-se também um outro mecanismo, denominado de Realimentação de Erro, que melhora o desempenho do sistema em praticamente todas as situaçoes analisadas. Embora implique em aumento da carga computacional, este processo consiste de uma operação determinística, que dispensa etapas de iteração ou recursos computacionais distintos dos já disponíveis. Neste trabalho foi avaliada a utilização destas técnicas em um sistema OFDM com características similares ao sistema ISDB-T, adequado para radiodifusão de TV Digital . / This work introduces a new transform-based time interleaving algorithm: FTI-OFDM (Fourier Transform Interleaved OFDM), in which binary information is spread over several symbols, both in time and frequency domains. This process, designed to be included in digital modulation systems, is computationally efficient when used in conjunction with OFDM modulation. Simulations are used to show its superiority over the usual binary time interleaving used in ordinary OFDM under several impairment scenarios, that include long impulsive noise and deep fading. Also introduced in this work is the additional method of decision error feedback (ERF), that enhances the performance of FTI-OFDM in almost all situations. Furthermore, ERF is deterministic and non-iterative and employs the same computational resources found in OFDM systems. The performance of an FTI-OFDM system, similar to ISDB-T standard, is evaluated under several impairments, such as are found in Digital TV broadcasting environment.

Este trabalho apresenta um novo algoritmo, denominado Intercalamento Temporal por Transformada de Fourier (FTI), desenvolvido para complementar sistemas de modulação digital. Com este processo, a informação é distribuida de forma difusa ao longo de um conjunto de símbolos, tanto no domínio do tempo como no da frequência. Constitui-se em um processo computacionalmente eficiente, especialmente adequado para operar em conjunto com a modulação OFDM, e que apresenta consideráveis ganhos de desempenho em algumas situações de degradação; por exemplo, é mais tolerante a ruídos impulsivos de longa duração do que a modulação OFDM convencional. Apresenta-se também um outro mecanismo, denominado de Realimentação de Erro, que melhora o desempenho do sistema em praticamente todas as situaçoes analisadas. Embora implique em aumento da carga computacional, este processo consiste de uma operação determinística, que dispensa etapas de iteração ou recursos computacionais distintos dos já disponíveis. Neste trabalho foi avaliada a utilização destas técnicas em um sistema OFDM com características similares ao sistema ISDB-T, adequado para radiodifusão de TV Digital . / This work introduces a new transform-based time interleaving algorithm: FTI-OFDM (Fourier Transform Interleaved OFDM), in which binary information is spread over several symbols, both in time and frequency domains. This process, designed to be included in digital modulation systems, is computationally efficient when used in conjunction with OFDM modulation. Simulations are used to show its superiority over the usual binary time interleaving used in ordinary OFDM under several impairment scenarios, that include long impulsive noise and deep fading. Also introduced in this work is the additional method of decision error feedback (ERF), that enhances the performance of FTI-OFDM in almost all situations. Furthermore, ERF is deterministic and non-iterative and employs the same computational resources found in OFDM systems. The performance of an FTI-OFDM system, similar to ISDB-T standard, is evaluated under several impairments, such as are found in Digital TV broadcasting environment.

Dans la première partie de cette thèse, nous présentons une implémentation du langage fp2 ayant pour modèle les réseaux de Petri. Fp2 est un langage de programmation parallèle base sur la réécriture de termes et les spécifications algébriques. Nous donnons une nouvelle sémantique a fp2, de la famille des sémantiques du vrai parallélisme, et prouvons la correction de cette sémantique par rapport a la sémantique interleaving du langage. Le modèle utilise, les réseaux de Petri, et la nouvelle sémantique donnée au langage permettent une représentation plus compacte de programmes complexes, évitant les problèmes d'explosion combinatoire rencontres avec les implémentations précédentes. Nous évaluons le gain de notre approche, et proposons plusieurs schémas d'interprétation du langage, bases sur cette nouvelle sémantique. La seconde partie de ce travail concerne la définition d'une nouvelle famille d'équivalences comportementales pour les réseaux de Petri. Alors que les équivalences proposées jusqu'alors sont définies entre les marquages, c'est-a-dire entre les états globaux du réseau, nous définissons une relation entre les places du réseau, reprenant une idée proposée par olderog. De nouvelles équivalences, les bisimulations de places, sont proposées a partir de cette définition. Un algorithme efficace (polynomial) permettant de calculer la plus grande bisimulation de places sur un réseau est propose. Nous montrons comment simplifier un réseau en le quotientant par cette plus grande bisimulation, obtenant ainsi un représentant canonique d'une classe d'équivalence de réseaux bisimilaires de places. L'étude de ces équivalences est ensuite étendue aux réseaux avec actions internes

The purpose of this thesis is to demonstrate the effects of mismatch errors that occur in time-interleaved analog-to-digital converters (TI-ADC) and how these are compensated for by proprietary methods from Signal Processing Devices Sweden AB. This will be demonstrated by two different implementations, both based on the combined digitizer/generator SDR14. These demonstrations shall be done in a way that is easy to grasp for people with limited knowledge in signal processing. The first implementation is an analog video demo where an analog video signal is sampled by such an TI-ADC in the SDR14, and then converted back to analog and displayed with the help of a TV tuner. The mismatch compensation can be turned on and off and the difference on the resulting video image is clearly visible. The second implementation is a digital communication demo based on W-CDMA, implemented on the FPGA of the SDR14. Four parallel W-CDMA signals of 5 MHz are sent and received by the SDR14. QPSK, 16-QAM, and 64-QAM modulated signals were successfully sent and the mismatch effects were clearly visible in the constellation diagrams. Techniques used are, for example: root-raised cosine pulse shaping, RF modulation, carrier recovery, and timing recovery.

In this thesis a number of energy saving methods for a multiplier on algorithmic level are investigated. For the investigation a multiplier is constructed in VHDL, after which the circuit's performance is investigated. A number of techniques for reduced power consumption are introduced in the circuit and are then evaluated. The conclusions are that all investigated methods, pipelining, interleaving and voltage scaling, should be maximally made use of in order to minimize the power consumption. / I detta arbete undersöks ettantal energibesparande metoder för en multiplikator på algoritmnivå. För undersökningen konstrueras en multiplikator i VHDL, varefter kretsens prestanda undersöks. Ett antal tekniker för minskad effektförbrukning införs i kretsen och utvärderas därefter. Slutsatsen är att samtliga undersökta metoder, pipelining, interleaving och spänningsskalning, bör utnyttjas maximalt för att minimera effektförbrukningen.

<p>In this thesis a number of energy saving methods for a multiplier on algorithmic level are investigated. For the investigation a multiplier is constructed in VHDL, after which the circuit's performance is investigated. A number of techniques for reduced power consumption are introduced in the circuit and are then evaluated. The conclusions are that all investigated methods, pipelining, interleaving and voltage scaling, should be maximally made use of in order to minimize the power consumption.</p> / <p>I detta arbete undersöks ettantal energibesparande metoder för en multiplikator på algoritmnivå. För undersökningen konstrueras en multiplikator i VHDL, varefter kretsens prestanda undersöks. Ett antal tekniker för minskad effektförbrukning införs i kretsen och utvärderas därefter. Slutsatsen är att samtliga undersökta metoder, pipelining, interleaving och spänningsskalning, bör utnyttjas maximalt för att minimera effektförbrukningen. </p>

With the rapid growth of servers and applications spurred by the Internet economy, power consumption in today's data centers is reaching unsustainable limits. This has led to an imminent financial, technical and environmental crisis that is impacting the society at large. Hence, it has become critically important that power consumption be efficiently managed in these computing power-houses of today. In this work, we revisit the issue of adaptive power and performance management of data center server platforms. Traditional data center servers are statically configured and always over-provisioned to be able to handle peak load. We transform these statically configured data center servers to clairvoyant entities that can sense changes in the workload and dynamically scale in capacity to adapt to the requirements of the workload. The over-provisioned server capacity is transitioned to low-power states and they remain in those states for as long as the performance remains within given acceptable thresholds. The platform power expenditure is minimized subject to performance constraints. This is formulated as a performance-per-watt optimization problem and solved using analytical power and performance models. Coarse-grained optimizations at the platform-level are refined by local optimizations at the devices-level namely - the processor & memory subsystems. Our adaptive interleaving technique for memory power management yielded about 48.8% (26.7 kJ) energy savings compared to traditional techniques measured at 4.5%. Our adaptive platform power and performance management technique demonstrated 56.25% energy savings for memory-intensive workload, 63.75% savings for processor-intensive workload and 47.5% savings for a mixed workload while maintaining platform performance within given acceptable thresholds.