Important considerations of a photovoltaic (PV) source are achieving a high voltage and drawing currents with very little ripple component from it. Furthermore, the output from such a source is variable depending on irradiation and temperature. In this research, literature review of prior methods employed to boost the output voltage of a PV source is examined and their limitations identified. This research then proposes a multi-phase tapped-coupled inductor boost DC-DC converter that can achieve high voltage boost ratios, without adversely compromising performance, to be used as an interface to a PV source. The proposed converter achieves minimal current and voltage ripple both at the input and output. The suitability of the proposed converter topology for variable input voltage and variable power operation is demonstrated in this dissertation. The proposed converter is also shown to have good performance at high power levels, making it very suitable for high power applications. Detailed analysis of the proposed converter is done. Advantages of the proposed converter are explained analytically and confirmed through simulations and experimentally. Regulation of the converter output voltage is also explained and implemented using a digital controller. The simulation and experimental results confirm that the proposed converter is suitable for high power as well as variable power, variable voltage applications where high voltage boost ratios are required. / Dissertation (MEng)--University of Pretoria, 2013. / gm2014 / Electrical, Electronic and Computer Engineering / Unrestricted

Hamid Ghasemirahni, et al. have shown that the order of the network packets arrival at a datacenter, equipped with commodity servers, plays a significant role in the latency of processing these packets. The larger the burst of packets that are part of a flow and hence will be processed using the same instructions and data, the greater the utilization of the system’s caches and subsequently the lower the latency of their processing. However, there are many reason for the packets to not arrive in a burst. One of the main reason that is examined in this project is packet interleaving that takes place in the routers and switches along the path that the packets take from a computer to/from the datacenter. This project take a more general look at traffic arriving at a server via a tree of network devices on the uplink path to the server. The focus is to use scripts to create a tree of switches and conduct experiments with them by scripting Mininet. From these experiments we learned that the different algorithms that control the output queues of the network nodes across the network path play a significant role in packet interleaving. Furtheromore, experiments on Mininet host connectivity explained how with the Openflow protocol, Mininet controller set up rules in the switches of the network topology. Finally, experiments in TCP throughput showed the limiting factors of a TCP connection between the server and a host while many provided traffic flows illustrate common behaviors of packet interleaving that occurs due to the switches. / Hamid Ghasemirahni, et al. har visat att ordningen på nätverkspaketens ankomst till ett datacenter, utrustat med varuservrar, spelar en betydande roll i fördröjningen av bearbetningen av dessa paket. Ju större burst av paket som är en del av ett flöde och därför kommer att behandlas med samma instruktioner och data, desto större utnyttjande av systemets cacheminne och därefter desto lägre fördröjning för deras bearbetning. Det finns dock många anledningar till att paketen inte kommer fram i en skur. En av huvudorsakerna som undersöks i detta projekt är paketinterfoliering som sker i routrarna och switcharna längs vägen som paketen tar från en dator till/från datacentret. Detta projekt tar en mer allmän titt på trafik som kommer till en server via ett träd av nätverksenheter på upplänksvägen till servern. Fokus är att använda skript för att skapa ett träd av switchar och utföra experiment med dem genom att skripta Mininet. Från dessa experiment lärde vi oss att de olika algoritmerna som styr utgångsköerna för nätverksnoderna över nätverksvägen spelar en betydande roll i paketinterfoliering. Dessutom förklarade experiment på Mininet-värdanslutning hur med Openflow-protokollet, Mininet-styrenheten satte upp regler i switcharna i nätverkstopologin. Slutligen visade experiment i TCP-genomströmning de begränsande faktorerna för en TCP-anslutning mellan servern och en värd medan många tillhandahållna trafikflöden illustrerar vanliga beteenden för paketinterfoliering som uppstår på grund av switcharna.

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<p>The increasing data rates in digital television networks increase the demands on data capacity of the current transmission channels. Through new standards, the capacity of exisiting channels is increased with new methods of error correction coding and modulation.</p><p>This thesis presents the design and implementation of a modulator for transmission of digital terrestrial television according to the Chinese DTMB standard.</p><p>The system is written in VHDL and is intended for implementation on an FPGA.</p>

With the advances in video compression and networking techniques, the last ten years have witnessed an explosive growth of video applications over the Internet. However, the service model of the current best-effort network was never engineered to handle video traffic and, as a result, video applications still suffer from varying and unpredictable network conditions, in terms of bandwidth, packet loss and delay. To address these problems, a lot of innovative techniques have been proposed and researched. Among them, scalable video coding is a promising one to cope with the dynamics of the available bandwidth and heterogeneous terminals. This work aims at improving the efficacy of scalable video transport over IP networks. In this work, we first propose an optimal interleaving scheme combined with motion-compensated fine granularity scalability video source coding and unequal loss protection schemes, under an imposed delay constraint. The network is modeled as a packet-loss channel with random delays. The motion compensation prediction, ULP allocation and the depth of the interleaver are jointly optimized based on the network status and the delay constraint. We then proceed to investigate the multiple path transport technique. A unified approach which incorporates adaptive motion compensation prediction, multiple description coding and unequal multiple path allocation, is proposed to improve both the robustness and error resilience property of the video coding and transmission system, while the delivered video quality is improved simultaneously. To analytically investigate the efficacy of error resilient transport schemes for progressively encoded sources, including unequal loss protection, best-effort and FEC transport schemes, we develop evaluation and optimization approaches for these transport schemes. In this part of the work, the network is modeled as an M/D/1/K queue, and then a comprehensive queueing analysis is provided. Armed with these results, the efficacy of these transport schemes for progressively encoded sources are investigated and compared.

The goals for most of today’s receiver system are sampling at high-speed, with high resolution and with as few errors as possible. This master thesis describes the design of a high-speed sampling system with"state-of-the-art"components available on the market. The system is designed with a parallel Analog-to-digital converter (ADC) architecture, also called time interleaving. It aims to increase the sampling speed of the system. The system described in this report uses four 12-bits ADCs in parallel. Each ADC can sample at 125 MHz and the total sampling speed will then theoretically become 500 Ms/s. The system has been implemented and manufactured on a printed circuit board (PCB). Up to four boards can be connected in parallel to get 2 Gs/s theoretically. In an approach to increase the systems performance even further, a timing error estimation algorithm will be used on the sampled data. This algorithm estimates the timing errors that occur when sampling with non-uniform time interval between samples. After the estimations, the sampling clocks can be adjusted to correct the errors. This thesis is concerning some ADC theory, system design and PCB implementation. It also describes how to test and measure the system’s performance. No measurement results are presented in this thesis because measurements will be done after this project. The last part of the thesis discusses future improvementsto achieve even higher performance.

The increasing data rates in digital television networks increase the demands on data capacity of the current transmission channels. Through new standards, the capacity of exisiting channels is increased with new methods of error correction coding and modulation. This thesis presents the design and implementation of a modulator for transmission of digital terrestrial television according to the Chinese DTMB standard. The system is written in VHDL and is intended for implementation on an FPGA.

In this thesis a two-stage AC/DC/DC power converter is designed and implemented. The AC/DC input stage of the converter consists of the two&amp / #8211 / phase interleaved boost topology employing the average current mode control principle. The output stage consists of a zero voltage switching phase shifted full bridge (ZVS&amp / #8211 / PS&amp / #8211 / FB) DC/DC converter. For the input stage, main design goals are obtaining high input power factor, low input current distortion, and well regulated output dc voltage, and obtaining these attributes in a power converter with high power density. For the input stage, the interleaved structure has been chosen in order to obtain reduced line current ripple and EMI, reduced power component stresses, and improved power density. The control of the pre&amp / #8211 / regulator is provided by utilizing a new commercial monolithic integrated circuit, which provides interleaved continuous conduction mode power factor correction (PFC). The output stage is formed by utilizing the available prototype hardware of a ZVS&amp / #8211 / PS&amp / #8211 / FB DC/DC converter and mainly the system integration and controller design and implementation studies have been conducted. The converter small signal model is derived and utilizing its transfer function and employing voltage loop control, the output voltage regulator has been designed. The output voltage controller is implemented utilizing a digital signal processor (DSP). Integrating the AC/DC preregulator and DC/DC converter, a laboratory AC/DC/DC converter system with high overall performance has been obtained. The overall system performance has been verified via computer simulations and experimental results obtained from laboratory prototype.

<p>The goals for most of today’s receiver system are sampling at high-speed, with high resolution and with as few errors as possible. This master thesis describes the design of a high-speed sampling system with"state-of-the-art"components available on the market. The system is designed with a parallel Analog-to-digital converter (ADC) architecture, also called time interleaving. It aims to increase the sampling speed of the system. The system described in this report uses four 12-bits ADCs in parallel. Each ADC can sample at 125 MHz and the total sampling speed will then theoretically become 500 Ms/s. The system has been implemented and manufactured on a printed circuit board (PCB). Up to four boards can be connected in parallel to get 2 Gs/s theoretically. </p><p>In an approach to increase the systems performance even further, a timing error estimation algorithm will be used on the sampled data. This algorithm estimates the timing errors that occur when sampling with non-uniform time interval between samples. After the estimations, the sampling clocks can be adjusted to correct the errors. </p><p>This thesis is concerning some ADC theory, system design and PCB implementation. It also describes how to test and measure the system’s performance. No measurement results are presented in this thesis because measurements will be done after this project. The last part of the thesis discusses future improvementsto achieve even higher performance.</p>

A widespread and persistent memory error that people commit on a daily basis is the post-completion error (PCE; i.e., forgetting to complete the final step of a procedural task). PCEs occur in the railroad industry when a locomotive conductor changes the direction of a rail switch but fails to report this change. This particular error could contribute to unsafe conditions as another train traveling on the same track could derail. Although training can help reduce some of the factors leading to unsafe conditions on the rail, research has demonstrated that PCEs are different from other errors of omission in that they cannot be eliminated through training, which makes them a difficult problem to address. Therefore, there is a need to explore new remedial actions designed to reduce PCEs. The current study investigated the effectiveness of a theoretically motivated intervention at reducing PCEs in trainyard operations, where making these errors could be life-threatening. Twenty-eight undergraduates completed trainyard tasks within a high-fidelity simulator. Each participant received the behavioral intervention in one block and no intervention in another. Specifically, participants were required to perform an additional task designed to remind participants of the post-completion (PC) step. The intervention significantly reduced PCE rates in the context of trainyard operations, on average, by 65%. We discuss implications of these results on reducing trainyard accidents, and how this outcome can contribute to the literature on the cause of PCEs.