This thesis presents an examination of the jitter performance of different oscillator types in the presence of flicker noise, white noise and power supply noise. Key results are achieved using time domain simulations to determine cycle jitter of several different oscillator architectures, semiconductor processes and component features. In the end, a design procedure is developed for creating a low-jitter oscillator in a TSMC .25mm CMOS semiconductor process.

An alternate method for mitigating the depredating physiological affects of a soldiers marksmanship due to combat stressors can be achieved through the design and implementation of a active stabilization system for small arms weapons. The INSTAR system is an innovative active stabilization system designed to decouple the shooter's disturbance effects from the barrel movement. The INSTAR system uses an piezoelectric actuator separating the barrel of the rifle from its stock to stabilize barrel movement. This paper uses various control techniques to develop control algorithms for simulation. The level of performance for each control algorithm is based on how well each they measure up to the criteria developed from the INSTAR system. This paper furthers research on INSTAR by developing and comparing four control designs that may be implemented within the INSTAR system. / Master of Science

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In the design of voltage-controlled oscillators (VCOs) for communication systems, timing jitter is of major concern since it is the largest contributor to the bit-error rate. The latest deep submicron processes provide the possibility of higher oscillator speed at the cost of increased device noise and a higher 1/f noise corner. Therefore it is crucial to characterize the upconverted 1/f noise for practical applications. This dissertation presents a simple model to relate the time domain jitter and frequency domain phase noise in the presence of non-negligible 1/f noise sources. It will simplify the design, simulation, and testing of the PLL, since with this technique only the open loop VCO needs to be considered. Design methodologies for white noise dominated ring oscillators and PLLs are also developed by analyzing the upconverted thermal noise in time domain using a LTI model. The trade-off and relationship between jitter, speed, power dissipation and VCO geometry are evaluated for different applications. This model is supported by the measured data from 24 ring oscillators with different geometry fabricated in TSMC 0.18um process. The theory developed in this dissertation is applied to the design of PLL- and DLL- based true random number generators (TRNG) for application in the area of“smart cards". New architectures of dual-oscillator sampling and delay-line sampling are proposed for random number generation, which has the advantage of lower power dissipation and lower cost over traditional approaches. Both structures are implemented in test chips fabricated in AMI 1.5um process. The PLL-based TRNG passed the NIST SP800-22 statistical test suite and the DLL-based TRNG passed both the NIST SP800-22 statistical test suite and the Diehard battery of tests.

This dissertation proposes new methods for measuring jitter of high-speed digital signals. The proposed techniques are twofold. First, a low-speed jitter measurement environment is realized by using a jitter expansion sensor. This sensor uses a low-frequency reference signal as compared to high-frequency reference signals required in standard high-speed signal jitter measurement instruments. The jitter expansion sensor generates a low-speed signal at the output, which contains jitter content of the original high-speed digital signal. The low-speed sensor output signal can be easily acquired with a low-speed digitizer and then analyzed for jitter. The proposed low-speed jitter measurement environment using the jitter expansion sensor enhances the reliability of current jitter measurement approaches since low-speed signals used as a reference signal and a sensor output signal can be generated and applied to measurement systems with reduced additive noise. The second approach is direct digitization without using a sensor, in which a high-speed digital signal with jitter is incoherently sub-sampled and then reconstructed in the discrete-time domain by using digital signal reconstruction algorithms. The core idea of this technique is to remove the hardware required in standard sampling-based jitter measurement instruments for time/phase synchronization by adopting incoherent sub-sampling as compared to coherent sub-sampling and to reduce the need for a high-speed digitizer by sub-sampling a periodic signal over its many realizations. In the proposed digitization technique, the signal reconstruction algorithms are used as a substitute for time/phase synchronization hardware. When the reconstructed signal is analyzed for jitter in digital post-processing, a self-reference signal is extracted from the reconstructed signal by using wavelet denoising methods. This digitally generated self-reference signal alleviates the need for external analog reference signals. The self-reference signal is used as a timing reference when timing dislocations of the reconstructed signal are measured in the discrete-time domain. Various types of jitter of the original high-speed reference signals can be estimated using the proposed jitter analysis algorithms.

Long distance repeaterless optical fiber communications systems are currently used to transmit most internet and telephone information worldwide. The growth of photonic telecommunications technology has produced systems with very high bit-rate per fiber, but this still falls short of its potential capacity. Currently systems that are able to transmit even higher bit-rates are being developed utilizing dense wavelength-division-multiplexing (WDM) to maximally utilize the bandwidth potential of optical fibers. One of the most important factors that limits the bit-rate achievable in a such a WDM optical communications system is the cross-talk between channels caused by pulse collisions. In this thesis a consistent mathematical theory is used to analyze the frequency and timing shifts caused collisions between two WDM channels. This theory is applied to the systems currently most promising for next-generation photonic telecommunications; the dispersion managed (DM) soliton and 'quasi-linear' systems. Self-contained formulae are obtained which accurately predict the timing shifts suffered in these systems with a wide range of parameters. These formulae require an order of magnitude less computational time that direct numerical simulations. Several mathematical techniques are introduced to obtain computationally efficient formulae for complete and incomplete collisions in both systems. For complete collisions we use the Poisson sum transform to change the calculation to a sum in the Fourier domain. For incomplete collisions we use asymptotic integration to obtain approximate formulae. For quasi-linear systems we simplify the Laplace method even further to obtain elementary formulae. We show that using a combination of these methods the timing shift for incomplete and complete collisions in a wide range of system configurations can be obtained in comparatively small computational times. We find that for systems with small DM map strength the timing shift from widely separated channels is significant. For quasi-linear systems with large DM map strength this is negligable and the timing shift decreases with the square of the channel frequency separation. We also find the timing shift from closely spaced channels is higher for quasi-linear systems than for DM soliton systems operating at the same average dispersion.

<p>Technological advancements in video technology have placed stringent requirements on video analog front ends (AFEs) to deliver high resolutions crisp images while consuming low power to deliver optimal performance.</p><p>One of the vital parts of an AFE is a delay locked loop (DLL). The DLL is a first order system that aligns  a delayed signal with respect to a reference signal while working in a feedback manner. DLLs find their applications in many electronic devices that deal with clocks in their operation. They are used to improve timing margins and clock delays in microprocessors, memory elements and other such applications. The vital function of a DLL is to delay the input clock (one period delay), by passing it through delay line and aligning the input clock and the delayed clock of the DLL through phase detector. Once this is done multiple phases canbe derived from various stages of the delay line with each providing a stable clock signal that is a delayed version of the input clock. Due to the increasing clock speeds this task of deriving multiple phases has become quite cumbersome. The task may become complicated due to noise generated from switching activity in digital circuits thus resulting in jitter at DLL output. As the design of analog circuits becomes quite exigent especially below the 100 nm mark, the goal hereis to design an all digital DLL to take advantage of the 65 nm process and a simplified design cycle.</p><p>The aim of this thesis is to implement an all digital delay locked loop with an input frequency range of 60 MHz to 300 MHz with a worst case jitter of 66 ps.The DLL provides 32 uniformly spaced phases between input and output clocks.The DLL operation is divided in to two stages. In the first step the first delayline quantizes input clock period with the help of a binary time to digital converter.Based on this quantization information second delay line introduces actual delay between input and output clocks with 32 intermediate phases in between.The entire process takes up to 9 clock cycles until a lock state is achieved. These 32 phases provide a greater phase resolution enhancing the sync processing characteristics of the video AFE thus improving the one screen display characteristics.</p>

Methods for performing response time analysis of real-timesystems are important, not only for their use in traditionalschedulability testing, but also for deriving bounds on outputtiming variations in control applications. Automatic controlsystems are inherently sensitive to variations in periodicityand end-to-end delays. Therefore, real-time performance needsto be considered during control design. For this purpose, anyreal-time analysis of a potential control implementation shouldproduce results that can easily be used to examine how theimplementation affects control performance. To find the maximumresponse time variation for a task, bounds on both minimum andmaximum response times are needed. A tight bound on thismaximum variation is useful in the analysis of controlperformance and can also be used to improve the results of someiterative response time analysis methods. In this thesis, threemethods for response time analysis are developed. While earlier research has focused on bounding maximumresponse times, one of the analysis methods in this thesisallows a computation of the minimum response times ofindependent fixed priority scheduled tasks. The analysis findsthe largest lower bound of response times for such tasks, whichleads to a tighter bound on the response time variations. Asecond analysis method allows exact computation of maximumresponse times for tasks whose arrival times are related byoffsets. The method is a complement to schedule simulationbased analysis, which it outperforms for systems with tasksthat may experience release jitter. A common design principle for distributed real-time systemsis to let the completion of one task trigger the start of oneor more successors. A third method supporting the analysis oftasks in such systems is described. The method extends andimproves earlier methods as it allows a generalized systemmodel and also results in tighter bounds than the originalmethods. This method has been implemented as part of a toolsetthat enables an integrated approach to the design and analysisof control systems and their implementation as distributedreal-time systems. As part of the thesis, models for describingdistributed control systems have been developed. The toolset,which is based on these models, uses the derived response timebounds in a control system performance analysis based onsimulation. The use of the toolset is exemplified in a smallcase study. <b>Keywords:</b>real-time systems, scheduling, response time,fixed priority, control, jitter, offset, schedulabilityanalysis

Inter-chip input-output (I/O) communication bandwidth demand, which rapidly scaled with integrated circuit scaling, requires high performance I/O links to achieve a per pin data rate as high as multi-Gb/s. The design of high-speed links employing forwarded-clock architecture enables jitter tracking between data and clock from low to high frequencies. Considering the impact of clock to data skew, high frequency sampling clock jitter and data jitter become out of phase at receiver, which reduces the timing margin and limits the data rate. The jitter tracking bandwidth (JTB) between data and clock should be optimized to compensate the clock to data skew. System level analysis shows that the wide tunable range of JTB is needed to compensate different amounts of skews. The implementation of bandpass filtering on forwarded-clock path is able to control the JTB through the controlling of Q. This work introduces a method using bandpass filtering to optimize the JTB in high-speed forwarded-clock transceivers, followed by the implementation of active-inductor-based bandpass filter as clock receiver, which has advantages of low-voltage operation, low power as well as low area consumption. Simulation results shows that the designed filter provides controllable JTB over 40 - 600MHz. The bandpass filter is implemented in IBM 90nm CMOS process.

In a DiffServ networks, edge and core router classify traffic flows into different PHBs and provide different QoS for the classified flows. In order to achieve satisfactory QoS guarantee, many packet schedulers were proposed. However IETF have not formally standardized an appropriate and effective packet scheduler to minimize the jitter for real-time traffic. In RFC, EF flows are characterized with low-latency, low packet loss rate, and low jitter. Therefore, real-time traffic is often classified into EF flow. By considering the characteristics of real-time traffic, it is not appropriate to forward packets either too fast or too slow. Hence, in this Thesis, we propose a mechanism in which each packet is attached with its own per-hop queuing delay. If a packet is forwarded within its own per-hop queuing delay, we say the packet may arrive too early (credit accumulation). If a packet is forwarded beyond its own per-hop queuing delay, we say the packet has late arrival (deficit accumulation). The Credit/Deficit information can be stored in the IPv6 optional header so that it can pass through the whole networks. If we can minimize the Credit/Deficit, the jitter can be minimized too. Our design is based on a modified WFQ by adding functions such as estimated queuing delay and dynamic class changes. The dynamic class changes allow EF packets to switch among queues to achieve lower jitter and constant delay. We first implement the traditional WFQ scheduler on Linux platform and then followed by the implementation of the Credit/Deficit WFQ (CDWFQ). The experimental results have shown that CDWFQ can provide nearly constant queuing delay, lower packet loss rate, and lower jitter for EF traffic flows.