<p>Methods for performing response time analysis of real-timesystems are important, not only for their use in traditionalschedulability testing, but also for deriving bounds on outputtiming variations in control applications. Automatic controlsystems are inherently sensitive to variations in periodicityand end-to-end delays. Therefore, real-time performance needsto be considered during control design. For this purpose, anyreal-time analysis of a potential control implementation shouldproduce results that can easily be used to examine how theimplementation affects control performance. To find the maximumresponse time variation for a task, bounds on both minimum andmaximum response times are needed. A tight bound on thismaximum variation is useful in the analysis of controlperformance and can also be used to improve the results of someiterative response time analysis methods. In this thesis, threemethods for response time analysis are developed.</p><p>While earlier research has focused on bounding maximumresponse times, one of the analysis methods in this thesisallows a computation of the minimum response times ofindependent fixed priority scheduled tasks. The analysis findsthe largest lower bound of response times for such tasks, whichleads to a tighter bound on the response time variations. Asecond analysis method allows exact computation of maximumresponse times for tasks whose arrival times are related byoffsets. The method is a complement to schedule simulationbased analysis, which it outperforms for systems with tasksthat may experience release jitter.</p><p>A common design principle for distributed real-time systemsis to let the completion of one task trigger the start of oneor more successors. A third method supporting the analysis oftasks in such systems is described. The method extends andimproves earlier methods as it allows a generalized systemmodel and also results in tighter bounds than the originalmethods. This method has been implemented as part of a toolsetthat enables an integrated approach to the design and analysisof control systems and their implementation as distributedreal-time systems. As part of the thesis, models for describingdistributed control systems have been developed. The toolset,which is based on these models, uses the derived response timebounds in a control system performance analysis based onsimulation. The use of the toolset is exemplified in a smallcase study.</p><p><b>Keywords:</b>real-time systems, scheduling, response time,fixed priority, control, jitter, offset, schedulabilityanalysis</p>

Previous research has indicated aperiodicity in the positions of tip vortices emitted from a helicopter rotor blade in hover. The objective of the current study is to develop an analysis of the tip vortex aperiodicity in hover and to validate it with measurements on a reduced-scale, 1m diameter, four-bladed rotor. A “vortex ring emitter model” (VREM) was developed to study the statistics of the tip vortices emitted from a rotor blade during hover. In order to better model the rotor wake, a number of independent vortex blobs were used to describe a vortex ring. An empirical model for viscosity was also considered which helped model the core radius growth of the vortex ring with vortex age. A parametric analysis was then performed to obtain a comprehensive qualitative and quantitative convergence study of the time step, viscosity parameter, initial core size, number of rings shed, number of blobs and overlap factor. It was observed that the solution converged rapidly for all the parameters used. The locations of tip vortex cores for vortex ages ranging from 0◦ to 260◦ were measured on the reduced-scale rotor using a stereo PIV system. The blade loading for the reduced scaled rotor was Ct /σ = 0.044 and the blade rotational speed was 1520 RPM, which corresponds to a tip Reynolds number of 248,000. The 95 % confidence region for the position of tip vortex cores exhibited an anisotropic, aperiodic pattern, approximating an ellipse. It was seen that the principal axis of this ellipse appeared to be aligned perpendicular to the slipstream boundary. The analytical model showed good correlation with experimental data in terms of the orientation and extent of the anisotropy. Moreover, an estimate of the total thrust produced and spanwise loading along the rotor blade was also obtained and compared with Blade Element Momentum Theory (BEMT). It was seen that by using more blobs to represent a vortex ring, the solution converged to the BEMT estimate. / text

Jitter is generally defined as a time deviation of the clock waveform from its desired position. The deviation which occurs can be on the leading or lagging side and it can be bounded (deterministic) or unbounded (random). Jitter is a critical specification in the digital system design. There are various techniques to measure the jitter. The straightforward approach is based on spectrum analyzer or oscilloscope measurements. In this thesis an on-chip jitter measurement technique is investigated and the respective circuit is designed using 65 nm CMOS technology. The work presents the high level model and transistor level model, both implemented using Cadence software. Based on the Vernier concept the circuit is composed of an edge detector, two oscillators, and a phase detector followed by a binary counter, which provides the measurement result. The designed circuit attains resolution of 10ps and can operate in the range of 100 - 500 MHz Compared to other measurement techniques this design features low power consumption and low chip area overhead that is essential for built-in self-test (BIST) applications.

Ring oscillators provide a central role in timing circuits for today?s mobile devices and desktop computers. Increased integration in these devices exacerbates switching noise on the supply, necessitating improved supply resilience. Furthermore, reduced voltage headroom in submicron technologies limits the number of stacked transistors available in a delay cell. Hence, conventional single-loop oscillators offer relatively few design options to achieve desired specifications, such as supply rejection. Existing state-of-the-art supply-rejection- enhancement methods include actively regulating the supply with an LDO, employing a fully differential or current-starved delay cell, using a hi-Z voltage-to-current converter, or compensating/calibrating the delay cell. Multiloop ring oscillators (MROs) offer an additional solution because by employing a more complex ring-connection structure and associated delay cell, the designer obtains an additional degree of freedom to meet the desired specifications. Designing these more complex multiloop structures to start reliably and achieve the desired performance requires a systematic analysis procedure, which we attack on two fronts: (1) a generalized delay-cell viewpoint of the MRO structure to assist in both analysis and circuit layout, and (2) a survey of phase-noise analysis to provide a bank of methods to analyze MRO phase noise. We distill the salient phase-noise-analysis concepts/key equations previously developed to facilitate MRO and other non-conventional oscillator analysis. Furthermore, our proposed analysis framework demonstrates that all these methods boil down to obtaining three things: (1) noise modulation function (NMF), (2) noise transfer function (NTF), and (3) current-controlled-oscillator gain (KICO). As a case study, we detail the design, analysis, and measurement of a proposed multiloop ring oscillator structure that provides improved power-supply isolation (more than 20dB increase in supply rejection over a conventional-oscillator control case fabricated on the same test chip). Applying our general multi-loop-oscillator framework to this proposed MRO circuit leads both to design-oriented expressions for the oscillation frequency and supply rejection as well as to an efficient layout technique facilitating cross-coupling for improved quadrature accuracy and systematic, substantially simplified layout effort.

Jitter and noise on package and printed circuit board interconnects are limiting factors in the performance of high speed digital channels. The simultaneous switching noise (SSN) induced by the return path discontinuities (RPDs) is a major source of noise and jitter on the signal interconnects of these channels. Therefore, optimal design of the power delivery network (PDN) is required to reduce SSN induced noise and jitter and improve the performance of high speed channels. The design of PDN is done in frequency domain whereas jitter and noise are time domain events. As a result, multiple iterations between frequency domain design of PDN and time domain analysis of noise and jitter are required before a design is taped out. A new methodology to correlate PDN impedance with jitter and voltage margin is presented in this thesis. Using this methodology, it would be possible to estimate jitter and noise from the PDN impedance and reduce the iterations involved in freezing the PDN design. The SSN induced at a given RPD is proportional to the PDN impedance at that RPD. As a result, the jitter and the noise can be correlated to the PDN impedance. The PDN impedance is a function of frequency and has alternate local minima and local maxima at resonances and anti-resonances respectively. The anti-resonances in the PDN impedance at the RPD cause significant increase in the insertion loss of signal whose return current is disrupted at that RPD. The increase in the insertion loss attenuates significant harmonics of the signal degrading its rise/fall times and voltage levels. This results in reduction of timing and voltage margins of the signal. Thus, based on the insertion loss profile and harmonic content of the signal, an estimate of jitter and noise on the signal can be made. Passive test vehicles consisting of microstrips with RPDs have been designed and fabricated to demonstrate the proof of concept through both simulations and measurements. Suitable placement of decoupling capacitors is suggested to reduce the PDN impedance below the target impedance and to minimize coupling between two noise ports on the PDN. Genetic algorithm to optimize the selection and placement of decoupling capacitors has been implemented. The efficacy of the algorithm has been demonstrated by testing it on a power delivery networks consisting of a simple power/ground plane pair.

Techn. University, Diss., 2002--Berlin.

Arbetet ger en omfattande bakgrund till vilka problem som måste hanteras i utvecklandet av flerspelarspel som ska spelas över internet. Arbetet fokuserar främst på de problem som uppstår på grund av nätverksfördröjning och jitter. Olika tekniker presenteras för att hantera dessa problem men arbetet fokuserar på tekniken lokal fördröjning. Arbetet utvärderar om det går att anpassa den lokala fördröjningen mot att matcha nuvarande nätverksegenskaper utan att påverka spelarens spelupplevelse negativt. För att utveckla denna hypotes utvecklades ett utvärderingsspel som har använts i en dubbelblind kvantitativ undersökning där spelarens spelupplevelse utvärderades. Resultaten från den undersökning som genomfördes var att dynamisk lokal fördröjning är att föredra då spel spelas över instabila nätverk som påverkas kraftigt av jitter.

The Voice over Internet Protocol (VoIP) is on its way to surpassing toll quality. Although VoIP shares its transmission channel with other communication traffic, today internet has a wider bandwidth than the legacy Digital Loop Carrier and voice could be digitized higher than traditional 8 kbps, to say 16 kbps. Thus, VoIP should not be limited by the toll quality. However, VoIP quality could go down, as a result of unpredictable traffic congestion and network imperfections. These two situations cause delay jitter and packet loss of VoIP. To overcome these challenges, there are ongoing works for service providers including but not limited to optimizing routing and adding more bandwidth. There are also works by developers at the user’s end, which includes compressing voice packet size and processing playout delay adapted to the network condition. While VoIP planning or off-line quality monitoring and control use overall quality measurements such as mean opinion score (MOS) or R-factor, the real-time quality supervision typically uses the network condition factors only. The control mechanism that is based on network quality could adjust the channel parameter by changing Codec and its parameters, and changing playout delay, etc. to minimize the loss of voice quality. As bandwidth plays a prominent role in IP traffic congestion, compressing the packet header is a possible solution to minimize congestion. Replacing a completed packet header with a smaller header will significantly reduce the packet header size. For instance, with a context, a compressed header will not consist of RTP header and, thus, could reduce 16 bytes from each packet. However, the primary question is how to deal with delay jitter calculation without time stamping. In this research, a delay jitter calculation for VoIP packet without timestamp has been provided. Compressing payload or using high compressing Codecs, is another major solution for preventing quality downgrade with limited bandwidth. The challenge with many Codec and the tradeoff between Codec quality and packet loss due to limited bandwidth has been addressed in this research with a summary of Codec quality evaluation and a bandwidth planning calculation. Although the E-model and its R-factor has been proposed by the International Telecommunication Union (ITU) for VoIP quality measurement, with many network and Codec parameters, it could only be used for offline quality control. Since accessing a live traffic for monitoring live quality is somewhat impossible, at the client side, only packet loss and delay jitter matters. In this research, more in-depth investigation of adaptive playout delay based on jitter prediction has been carried out and recommended as the end user solution for quality improvement. An adaptive playout delay based on Markov model also has been developed in detail and tested with real VoIP network. This development has closed the gap between research and engineering. Therefore, the Markov model could be evaluated and implemented.

Nowadays, Multi-GHz analog-to-digital converters (ADCs) are becoming more and more popular in radar systems, software-de ned radio (SDR) and wideband communications, because they can realize much higher operation speed through using many interleaved sub-ADCs to relax ADC sampling rates. Although the time interleaved ADC has some issues such as gain mismatch, o set mismatch and timing skew between each ADC channel, these deterministic errors can be solved by previous works such as digital calibration technique. However, time-interleaved ADCs require a precise sample clock to achieve an acceptable e ective-numberof- bits (ENOB) which can be degraded by jitter in the sample clock. The clock generation circuits presented in this work achieves sub-picosecond jitter performance in 180nm CMOS which is suitable for time-interleaved ADC. Two di erent test chips were fabricated in 180nm CMOS to investigate the low jitter design technique. The low jitter delay line in two chips were designed in two di erent ways, but both of them utilized the low jitter design technique. In rst test chip, the measured RMS jitter is 0.1061ps for each delay stage. The second chip uses the proposed low jitter Delay-Locked Loop can work from 80MHz to 120MHz, which means it can provide the time interleaved ADC with 2.4GHz to 3.6GHz low jitter sample clock, the measured delay stage jitter performance in second test chip is 0.1085ps.

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