The fifth and sixth generations of mobile communications and the internet of things (IoT) demand high-performance electronic devices made at low cost over a large area. Unlike the conventional Si-based electronics, the emerging large-area electronics (LAE) require flexible, stretchable, and lightweight devices that are printable and able to mass manufacture without compromising the performance of state-of-the-art electronic devices. Hence, there is a quest to find alternative fabrication routes and conventional photolithography. In this research work, we explored the adhesion lithography (a-Lith) to further simplify the process steps by adapting bi-layer metals to induce intrinsic stress in the bi-layer and hence facilitate the self-peeling of metal layers which results in more uniform and smaller nanogap between two metals than the previously established a-Lith fabricated nanogaps. The nanogap metal electrodes are further used to fabricate radio frequency (RF) Schottky diodes made using a printable metal oxide semiconductor and flashlight annealing over wafer-scale and demonstrate the operation frequencies above 100 GHz/47 GHz (intrinsic/extrinsic). Notably, for the first time, photonic annealing on such an ultra-small (< 20 nm) nanoscale channel was demonstrated, and the rapid manufacturing of RF diodes from the solution route was achieved. On the other hand, for the first time, organic diodes made using a-Lith fabricated nanogap metal electrodes, and high mobility polymer semiconductors with molecular dopants showed an extrinsic cut-off frequency well above 14 GHz. Finally, the nanogap metal electrodes were explored as a mold and shadow mask to fabricate nano-feature soft stamp and nano-fluidic channels (NFC), respectively. The soft stamp can replicate the high aspect ratio nanoscale features on any arbitrary substrates using available soft lithography routes, and the NFC is further envisioned for bio-molecules detection and sensing applications.

The development of functional flexible electronics is essential to enable applications such as conformal medical imagers, wearable health monitoring systems, and flexible light-weight displays. Intensive research on thin-film transistors (TFTs) is being conducted with the goal of producing high-performance devices for improved backplane electronics. However, there are many challenges regarding the performance of devices fabricated at low temperatures that are compatible with flexible plastic substrates. Prior work has reported on the change in TFT characteristics due to mechanical strain, with especially extensive data on the effect of strain on field-effect mobility. This thesis investigates the effect of gate-bias stress and elastic strain on the long-term stability of flexible low-temperature hydrogenated amorphous silicon (a-Si:H) TFTs, as the topic has yet to be explored systematically. An emphasis was placed on bias-stress measurements over time in order to obtain information on the physical mechanisms of instability. Drain current was measured over various intervals of time to track the degradation of devices due to metastability, and results were then compared across devices of various sizes under tensile, compressive, and zero strain. Transfer characteristics of the TFTs were also measured under the different conditions, to allow for extraction of parameters that would provide insight into the instability mechanisms. In addition to parameter extraction, the degradation and recovery of TFT output current was quantitatively compared for various bias-stress times across the different levels of strain. Finally, the instability mechanisms are modelled with a Markov system to further examine the effect of strain on long-term TFT operation. From the analysis of results, it was found that shallow charge trapping in the dielectric is the main mechanism of instability for short bias stress times, and did not seem to be greatly affected by strain. For longer bias stress times of over 10000 seconds, defect creation in the a-Si:H becomes a more significant contributor to instability. Both tension and compression increased defect creation compared to TFTs with zero applied strain. Compression appeared to cause the greatest increase in the rate of defect formation, likely by weakening Si-Si bonds in the a-Si:H. Tension appeared to cause a less significant increase, possibly due to a strengthening of some proportion of the Si-Si bonds caused by the slight elongation of bond length or because the applied tension relieves intrinsic compressive stress in a-Si:H film. A longer conduction path and greater dielectric area appears to increase the bias-stress and strain-related effects. Therefore reducing device size should increase the reliability of flexible TFTs.

The prospect of producing nanometer channel-length thin film transistors (TFTs) for active matrix addressed pixelated arrays opens up new high-performance applications in which the most amenable device topology is the vertical thin film transistor (VTFT) in view of its small area. The previous attempts at fabricating VTFTs have yielded devices with a high drain leakage current, a low ON/OFF current ratio, and no saturation behaviour in the output current at high drain voltages, all induced by short channel effects. To overcome these adversities, particularly dominant as the channel length approaches the nano-scale regime, the reduction of the gate dielectric thickness is essential. However, the problems with scaling the gate dielectric thickness are the high gate leakage current and early dielectric breakdown of the insulator, deteriorating the device performance and reliability. A novel ultra-thin SiNx film suitable for the application as the gate dielectric of short channel TFTs and VTFTs is developed. The deposition is performed in a standard 13.56MHz PECVD system with silane and ammonia precursor gasses diluted in nitrogen. The deposited 50nm SiNx films demonstrate excellent electrical characteristics in terms of a leakage current of 0.1 nA/cm?? and a breakdown electric field of 5.6MV/cm. Subsequently, the state of the art performances of 0.5??m channel length VTFTs with 50 and 30nm thick SiNx gate dielectrics are presented in this thesis. The transistors exhibit ON/OFF current ratios over 10^9, the subthreshold slopes as sharp as 0.23 V/dec, and leakage currents in the fA range. More significantly, a high associated yield is obtained for the fabrication of these devices on 3-inch rigid substrates. Finally, to illustrate the tremendous potential of the VTFT for the large area electronics, a 2.2-inch QVGA AMOLD display with in-pixel VTFT-based driver circuits is designed and fabricated. An outstanding value of 56% compared to the 30% produced by conventional technology is achieved as the aperture ratio of the display. Moreover, the initial measurement results reveal an excellent uniformity of the circuit elements.

The development of functional flexible electronics is essential to enable applications such as conformal medical imagers, wearable health monitoring systems, and flexible light-weight displays. Intensive research on thin-film transistors (TFTs) is being conducted with the goal of producing high-performance devices for improved backplane electronics. However, there are many challenges regarding the performance of devices fabricated at low temperatures that are compatible with flexible plastic substrates. Prior work has reported on the change in TFT characteristics due to mechanical strain, with especially extensive data on the effect of strain on field-effect mobility. This thesis investigates the effect of gate-bias stress and elastic strain on the long-term stability of flexible low-temperature hydrogenated amorphous silicon (a-Si:H) TFTs, as the topic has yet to be explored systematically. An emphasis was placed on bias-stress measurements over time in order to obtain information on the physical mechanisms of instability. Drain current was measured over various intervals of time to track the degradation of devices due to metastability, and results were then compared across devices of various sizes under tensile, compressive, and zero strain. Transfer characteristics of the TFTs were also measured under the different conditions, to allow for extraction of parameters that would provide insight into the instability mechanisms. In addition to parameter extraction, the degradation and recovery of TFT output current was quantitatively compared for various bias-stress times across the different levels of strain. Finally, the instability mechanisms are modelled with a Markov system to further examine the effect of strain on long-term TFT operation. From the analysis of results, it was found that shallow charge trapping in the dielectric is the main mechanism of instability for short bias stress times, and did not seem to be greatly affected by strain. For longer bias stress times of over 10000 seconds, defect creation in the a-Si:H becomes a more significant contributor to instability. Both tension and compression increased defect creation compared to TFTs with zero applied strain. Compression appeared to cause the greatest increase in the rate of defect formation, likely by weakening Si-Si bonds in the a-Si:H. Tension appeared to cause a less significant increase, possibly due to a strengthening of some proportion of the Si-Si bonds caused by the slight elongation of bond length or because the applied tension relieves intrinsic compressive stress in a-Si:H film. A longer conduction path and greater dielectric area appears to increase the bias-stress and strain-related effects. Therefore reducing device size should increase the reliability of flexible TFTs.

Since the discovery of graphene, substantial effort has been put toward the synthesis and production of 2D materials. Developing scalable methods for the production of high-quality exfoliated nanosheets has proved a significant challenge. To date, the most promising scalable method for achieving these materials is through the liquid-based exfoliation (LBE) of nanosheetsin solvents. Thin films of nanosheets in dispersion can be modified with additives to produce 2D inks for printed electronics using inkjet printing. This is the most promising method for the deposition of such materials onto any substrate on an industrial production level. Although well-developed metallic and organic printed electronic inks exist on the market, there is still a need to improve or develop new inks based on semiconductor materials such as transition metal dichalcogenides (TMDs) that are stable, have good jetting conditions and deliver good printing quality.The inertness and mechanical properties of layered materials such as molybdenum disulfide (MoS2) make them ideally suited for printed electronics and solution processing. In addition,the high electron mobility of the layered semiconductors, make them a candidate to become a high-performance semiconductor material in printed electronics. Together, these features make MoS2 a simple and robust material with good semiconducting properties that is also suitable for solution coating and printing. It is also environmentally safe.The method described in this thesis could be easily employed to exfoliate many types of 2D materials in liquids. It consists of two exfoliation steps, one based on mechanical exfoliation of the bulk powder utilizing sand paper, and the other inthe liquid dispersion, using probe sonication to liquid-exfoliate the nanosheets. The dispersions, which were prepared in surfactant solution, were decanted, and the supernatant was collected and used for printing tests performed with a Dimatix inkjetprinter. The printing test shows that it is possible to use the MoS2 dispersion as a printed electronics inkjet ink and that optimization for specific printer and substrate combinations should be performed. There should also be advances in ink development, which would improve the drop formation and break-off at the inkjet printing nozzles, the ink jetting and, consequently, the printing quality. / Sedan upptäckten av grafen har mycket arbete lagts på framställning och produktion av 2D-material. En viktig uppgift har varit att ta fram skalbara metoder för produktion av högkvalitativa  nanosheets via exfoliering. Den mest lovande skalbarametoden hittills har varit vätskebaserad exfoliering av nanosheets i lösningsmedel. Tunna filmer av nanosheets i dispersion kan anpassas med hjälp av tillsatser och användas för tillverkning av halvledare strukturer med inkjet-skrivare, vilket är den mest lovande metoden för på en industriell produktions nivå beläggaden typen av material på substrat. Även om det finns välutvecklade metalliska och organiskabläck för tryckt elektronik, så finns det fortfarande ett behov av att förbättra eller utveckla nya bläck baserade på halvledarmaterial som t.ex. TMD, som är stabila, har goda bestryknings  egenskaper och ger bra tryckkvalitet. Den inerta naturen tillsammans med de mekaniska egenskaperna som finns hosskiktade material, som t.ex. molybdendisulfid (MoS2), gör demlämpliga för flexibel elektronik och bearbetning i lösning. Dessutom gör den höga elektronmobiliteten i dessa 2D-halvledaredem till en stark kandidat som halvledarmaterial inom trycktelektronik. Det betyder att MoS2 är ett enkelt och robust material med goda halvledaregenskaper som är lämpligt för bestrykning från lösning och tryck, och är miljömässigt säker.Den metod som beskrivs här kan med fördel användas föratt exfoliera alla typer av 2D-material i lösning. Exfolieringensker i två steg; först mekanisk exfoliering av torr bulk med sandpapper, därefter används ultraljudsbehandling i lösning för att exfoliera nanosheets. De dispersioner som framställts i lösning med surfaktanter dekanterades och det övre skiktetanvändes i trycktester med en Dimatix inkjet-skrivare.Tryckprovet visar att det är möjligt att använda MoS2 -dispersion som ett inkjet-bläck och att optimering för särskildaskrivar- och substratkombinationer borde göras, såsom förbättringav bläcksammansättningen med avseende på droppbildning och break-off vid skrivarmunstycket, vilket i sin tur skulleförbättra tryckkvaliteten. / KM2 / Paper Solar Cells

A Voltage Controlled Oscillator (VCO) based pixel and array architecture is reported using amorphous silicon (a-Si) technology for large area digital imaging applications. The objectives of this research are to (a) demonstrate photon quantum noise limited pixel operation of less than 30 input referred noise electrons, (b) theoretically explore the use of the proposed VCO pixel architecture for photon quantum noise limited large area imaging applications, more specifically protein crystallography using a-Si, (c) to implement and demonstrate experimentally a quantum noise limited (VCO) pixel, a small prototype of quantum noise limited (VCO) pixelated array and a quantum noise limited (VCO) pixel integrated with direct detection selenium for energies compatible with a protein crystallography application. Electronic noise (phase noise) and metastability performance of VCO pixels in low cost, widely available a-Si technology will be theoretically calculated and measured for the first time in this research. The application of a VCO pixel architecture in thin film technologies to large area imaging modalities will be examined and a small prototype a-Si array integrated with an overlying selenium X-ray converter will be demonstrated for the first time. A-Si and poly-Si transistor technologies are traditionally considered inferior in performance to crystalline silicon, the dominant semiconductor technology today. This work v aims to extend the reach of low cost, thin film transistor a-Si technology to high performance analog applications (i.e. very low input referred noise) previously considered only the domain of crystalline silicon type semiconductor. The proposed VCO pixel architecture can enable large area arrays with quantum noise limited pixels using low cost thin film transistor technologies.

A Voltage Controlled Oscillator (VCO) based pixel and array architecture is reported using amorphous silicon (a-Si) technology for large area digital imaging applications. The objectives of this research are to (a) demonstrate photon quantum noise limited pixel operation of less than 30 input referred noise electrons, (b) theoretically explore the use of the proposed VCO pixel architecture for photon quantum noise limited large area imaging applications, more specifically protein crystallography using a-Si, (c) to implement and demonstrate experimentally a quantum noise limited (VCO) pixel, a small prototype of quantum noise limited (VCO) pixelated array and a quantum noise limited (VCO) pixel integrated with direct detection selenium for energies compatible with a protein crystallography application. Electronic noise (phase noise) and metastability performance of VCO pixels in low cost, widely available a-Si technology will be theoretically calculated and measured for the first time in this research. The application of a VCO pixel architecture in thin film technologies to large area imaging modalities will be examined and a small prototype a-Si array integrated with an overlying selenium X-ray converter will be demonstrated for the first time. A-Si and poly-Si transistor technologies are traditionally considered inferior in performance to crystalline silicon, the dominant semiconductor technology today. This work v aims to extend the reach of low cost, thin film transistor a-Si technology to high performance analog applications (i.e. very low input referred noise) previously considered only the domain of crystalline silicon type semiconductor. The proposed VCO pixel architecture can enable large area arrays with quantum noise limited pixels using low cost thin film transistor technologies.

The pixel element which is an integrated combination of a p-i-n diode with a thin film transistor (TFT) is used to produce image sensor arrays in scanning and displays technologies, necessitating the deposition of hydrogenated silicon based semiconducting and insulating thin films such as a-Si:H, a-SiNx:H over large area. The widely used techniques to achieve this goal is the plasma enhanced chemical vapor deposition (PECVD) due to its large area and low temperature (&amp / #61603 / 300 &amp / #61616 / C) abilities. In particular, PECVD has proved to be able to deposit both high quality insulator (a-SiNx:H) and active layer of p-i-n diode (intrinsic hydrogenated amorphous silicon carbide, a-SiCx:H) and by sequential deposition, it is possible to minimize the interface related problems, which play an important role in metal insulator semiconductor (MIS) and TFT structures. PECVD deposited a-SiCx:H films over p-type crystal Si and metal substrates (MIS and MIM) were investigated by both admittance spectroscopy (Capacitance or conductance vs. voltage, temperature or frequency measurements) and Deep Level Transient spectroscopy (DLTS) to investigate the interface related problems. In this respect, instability phenomena (due to the creation of metastable states and charge injection into the gate electrode) were studied via the c-Si/a-SiCx:H (and/or a-SiNx:H) heterojunction. Specially, capacitance voltage kinetics were worked out and then the enrolled trap energies were identified with temperature mode DLTS. The expertise gathered as a result of these studies were used in the fabrication and characterization of TFT&amp / #65533 / s. In this respect, inverted gate staggered type Thin Film Transistor produced and characterized for the first time after Combo-251 Pattern Generator was implemented.

The innovative design of flat panel volume computed tomography (CT) systems has recently led to the emergence of a wide spectrum of new applications for both diagnostic and interventional purposes, such as ultra-high resolution bone imaging, image guided interventions, dynamic CT angiography, and interventional neuroradiology. Most of these applications require low X-ray dose to limit potential harm to the patient. One of the main challenges of low dose imaging is to maintain a quantum noise limited system to achieve the highest possible signal to noise ratio (SNR) at a given dose. One potential method to achieve a quantum noise limited system is to employ a high gain detector. Current flat panel CT technology is based on indirect conversion detectors that contain a scintillator and hydrogenated amorphous silicon (a-Si:H) p-i-n photodetectors which have a gain below unity and require a specialized p-layer. In this thesis, an alternative detector to the p-i-n photodetector, which can achieve gain above unity and thus aid in achieving quantum noise limited systems is investigated for large area flat panel imaging. The proposed detector is based on amorphous selenium (a-Se). Amorphous selenium is the most highly developed photoconductor for large area direct conversion X-ray imaging and is still the only commercially available large area direct conversion flat panel X-ray detector. However, the use of a-Se for indirect conversion imaging has not been significantly explored. Amorphous selenium has field dependent mobility and conversion efficiency, which increase with increasing electric field. It is also the only large area compatible avalanche-capable material; a property that was discovered more than 30 years ago. This unique property could be leveraged to provide the gain necessary for low dose medical imaging applications. The only current commercial avalanche capable a-Se optical detector uses electron beam readout in vacuum, which is not large area compatible and makes integration with pixelated readout electronics challenging. The detector structure proposed in this research seeks to address the challenges associated with integration of an avalanche capable a-Se detector with large area X-ray imager. One important aspect in the development of a-Se avalanche detectors is reducing the dark current and preventing a-Se breakdown as the electric field across the device is increased. A high dark current reduces the dynamic range of the detector, it increases the noise level, and it can lead to crystallization of the detector due to joule heating. To overcome the dark current problem, different blocking layers that allow for integration with large area flat panel imagers were investigated. Experimental results from fabricated devices provided the basis for the choice of the most suitable blocking layer. Two device structures are proposed using the selected blocking layer, a vertical structure and a lateral structure, each having associated benefits and drawbacks. It was shown that introducing a polyimide blocking layer brought down the dark current more than four orders of magnitude at high electric fields and does not deteriorate the charge transport properties of the detectors. The polyimide blocking layer also greatly minimizes physical stress related crystallization in a-Se improving reliability. Gain above unity was observed in the vertical structure and the initiation of impact ionization was verified by performing time-of-flight experiments. Although impact ionization was not verified in the lateral structure, this device structure was found to be highly sensitive to ultraviolet light due to the absence of a top contact layer. Devices were fabricated on several different substrates, including a CMOS substrate, to demonstrate their integration compatibility with large area readout electronics. The exhibited performance of the vertical device structure demonstrates that it is a suitable alternative to the p-i-n photodetector for low dose imaging applications.

This work studies the influence of field effect on large area 2 dimensional ribbons of fluids. A fluid of choice is confined in the channel of a metal-insulator-channel-insulator-metal architecture and is subjected to constant (d.c) or alternating (a.c) fields (de-pending on the application) along with a pressure drive flow. A general fluid would be composed of molecules having certain polarizability and be a dispersion of non-ionic and ionic particulates. The field effect response under pressure driven flow for this fluid would result in electrophoresis, electro osmosis, dielectrophoresis, dipole-dipole interaction and inverse electro osmosis phenomena. Using some of these phenomena we study applications related to desalination and energy harvesting with saline water as the ex-ample fluid for the former case, and solution processed poly vinyldene fluoride (PVDF) for the latter case. The geometrical features of \large area" and the \ribbon shape" can be taken advantage of to influence the design and performance for both applications. With regards to desalination, it is shown via experiments and theoretical models that the presence of alternating electric fields aid in ion separation along the flow when the saline water is subjected to laminar flow. Moreover, the power consumption is low due to the presence of the insulator. An average of 30% ion removal efficiency and 15% throughput is observed in the systems fabricated. Both performance parameters are discussion can be improved upon with larger channel lengths. The \2-D ribbon" and alternating field effect aid in achieving this by patterning the randomly distributed ions in the bulk into a smooth sheet charge and then repelling this sheet charge back into the bulk. The electric field exhibited by this sheet charge helps trap more ion sheets near the interface, thereby converting a surface ion trapping phenomena (when d.c is used) to a bulk phenomena and thereby improving efficiency. With regards to energy harvesting, a solution of PVDF in methyl ethyl ketone and 1-methyl-2-pyrollidone is confined to the \2-D ribbon" geometry and subject to high d.c fields. This aids in combining the fabrication, patterning and poling process for PVDF into one setup. Since the shape of the ribbon is defined by the shape of the channel, the ribbons (straight or serrated) can be used to sense forces of various magnitudes. More importantly experiments and theoretical models are studied for energy harvesting. Since the ribbon geometry defines the resonant frequency, large PVDF ribbon can be used to harvest energy from low frequency vibrations. Experiments show that up to 60 microwatt power can be harvested at 200 Hz and is sufficient to supplement the power for ICs.