Práce popisuje průběh realizace námořní přepravy, charakterizuje nejčastěji používané dokumenty tohoto oboru a vysvětluje jejich užití a funkce, které plní. Dále práce popisuje problémy, se kterýmí se mohou smluvní strany při realizaci námořní přepravy setkat, a chyby, kterých se mohou dopustit, včetně uvedení případných následků. Součástí práce je i rozbor konkrétních sporů z praxe.

A series of Basic Assembler Language subroutines were developed and made available to the FORTRAN IV language processor which makes list processing possible in a flexible and easily understood way. The subroutine will create and maintain list structures in the computer's core storage. The subroutines are sufficiently general to permit FORTRAN programmers to tailor list processing routines to their own individual requirements. List structure sizes are limited only by the amount of core storage available. (61 pages)

<p>We study the problem of list decoding with focus on the case when we have a list size limited to two. Under this restriction we derive general lower bounds on the maximum possible size of a list-of-2-decodable code. We study the set of correctable error patterns in an attempt to obtain a characterization. For a special family of Reed-Solomon codes - which we identify and name 'class-I codes' - we give a weight-based characterization of the correctable error patterns under list-of-2 decoding. As a tool in this analysis we use the theoretical framework of Sudan's algorithm. The characterization is used in an exact calculation of the probability of transmission error in the symmetric channel when list-of-2 decoding is used. The results from the analysis and complementary simulations for QAM-systems show that a list-of-2 decoding gain of nearly 1 dB can be achieved.</p><p>Further we study Sudan's algorithm for list decoding of Reed-Solomon codes for the special case of the class-I codes. For these codes algorithms are suggested for both the first and second step of Sudan's algorithm. Hardware solutions for both steps based on the derived algorithms are presented.</p>

<p>This degree project concludes the Innovation and Design Engineering programme at Karlstad University. The project was carried out by David Brocker, Erik Hallberg and Andreas Hertzman during the spring of 2006 and corresponded to 15 weeks of work per student. Assigner was Martin Larsson at Arexor and instructor at Karlstad University was Monica Jakobsson.</p><p>Arexor has a patent to a construction of an electrical skirting board with moveable wall sockets, called Electrical Track System. The lowest parts of the interior walls along the floor are today almost always covered by a conventional skirting board. Arexors patented product replaces that with the possibility to move and increase the number of wall sockets by choice along an electrical skirting board. Conventional wall sockets are limited due to fixed positions and are not transferable. It causes a problem when the number of fixed wall sockets controls the possibilities and not the users demand.</p><p>The assignment commissioned by Arexor to the students was to improve and develop the Electrical Track System because the patent did not fulfil the requirements for CE certification. The project results were to be used by Arexor as the basic data when the product was tested by ETL SEMKO.</p><p>The objective of the project was to present directions for production to a functioning prototype of the Electrical Track System, within the estimated time period. The prototype was to be shown at the exhibition for degree projects at Karlstad University in May 2006. The objective also included to create a product brochure and a display case.</p><p>The development method were divided into five phases: preparation phase, research phase, idea generating phase, conception development phase and concretisation phase. They were carried out linear up to the conception development phase. Then iteration between the research phase, idea generating phase, conception development phase was repeated until satisfied result was achieved.</p><p>The result included a number of functioning prototypes, a display case, a product brochure, CAD drawings, renderings and this academic report. The prototypes were manufactured by Modellteknik in Eskilstuna, Sweden.</p><p>Parts of the result cannot be presented due to that the solutions was not, at the time, protected by the patent. Arexor announced in the end of the project that they would apply for a new patent that included our solutions. Because of that these solutions could not be shown in public. Some parts in the report therefore refer to secrecy.</p> / <p>Detta examensarbete var avslutningen på Innovations- och designingenjörsprogrammet vid Karlstads universitet på fakulteten för teknik- och naturvetenskap. Arbetet genomfördes av David Brocker, Erik Hallberg och Andreas Hertzman under våren 2006 på uppdrag av Arexor och omfattade 15 högskolepoäng per student. Uppdragsgivare på Arexor var Martin Larsson och handledare var Monica Jakobsson från Karlstads universitet.</p><p>Arexor har patenterat en konstruktion av en elektrisk golvlist med flyttbara vägguttag, kallat Electrical Track System. Längs med golvet utmed väggarna sitter i fastigheter i dag nästan alltid en golvlist. Arexors patenterade produkt ersätter golvlisten och ger möjlighet att bland annat flytta, montera och öka antalet vägguttag längs med listen efter eget behov. Traditionella uttag begränsas av att de har fasta positioner och inte kan omplaceras. Det innebär problem då antalet fasta uttag styr möjligheterna och inte behovet.</p><p>Uppdraget som Arexor gav projektgruppen var att vidareutveckla Electrical Track System, då patentet inte uppfyllde kraven för CE-certifiering. Resultatet av arbetet skulle sedan användas av Arexor som underlag vid test hos ETL SEMKO.</p><p>Målet var att ta fram tillverkningsunderlag för en slutgiltig, fungerande prototyp av ETS inom tidsramen för projektet. Den skulle sedan visas på examensutställningen vid Karlstads universitet den 30 maj 2006. Delmål var även att ta fram en produktbroschyr och en utställningsmonter.</p><p>Arbetet delades in i stegen arbetsplan, förstudie, idégenerering, konceptutveckling och konkretisering. De genomfördes linjärt upp till konceptutvecklingen, sedan skedde en iteration mellan stegen förstudie, idégenerering och konceptutveckling. Det betyder att processen upprepades tills det att önskat resultat uppnåddes.</p><p>Resultatet blev en mängd olika fungerande prototyper, en utställningsmonter, en produktbroschyr, CAD-ritningar, renderingar och denna akademiska rapport. Prototyperna tillverkades i samarbete med Modellteknik i Eskilstuna.</p><p>Delar av resultatet redovisas inte på grund av att lösningarna inte vid tidpunkten skyddades av rådande patent. Arexor meddelande i slutet av projektet att företaget skulle ansöka om ett nytt patent där dessa lösningar inkluderades. Det medförde att lösningarna inte fick offentliggöras innan patentansökan hade lämnats in. Därför hänvisas till sekretess i vissa delar av rapporten.</p>

We study the problem of list decoding with focus on the case when we have a list size limited to two. Under this restriction we derive general lower bounds on the maximum possible size of a list-of-2-decodable code. We study the set of correctable error patterns in an attempt to obtain a characterization. For a special family of Reed-Solomon codes - which we identify and name 'class-I codes' - we give a weight-based characterization of the correctable error patterns under list-of-2 decoding. As a tool in this analysis we use the theoretical framework of Sudan's algorithm. The characterization is used in an exact calculation of the probability of transmission error in the symmetric channel when list-of-2 decoding is used. The results from the analysis and complementary simulations for QAM-systems show that a list-of-2 decoding gain of nearly 1 dB can be achieved. Further we study Sudan's algorithm for list decoding of Reed-Solomon codes for the special case of the class-I codes. For these codes algorithms are suggested for both the first and second step of Sudan's algorithm. Hardware solutions for both steps based on the derived algorithms are presented.

Thomassen proved that there are only finitely many 6-critical graphs embeddable on a fixed surface. He also showed that planar graphs are 5-list-colorable. This thesis develops new techniques to prove general theorems for 5-list-coloring graphs embedded in a fixed surface. Indeed, a general paradigm is established which improves a number of previous results while resolving several open conjectures. In addition, the proofs are almost entirely self-contained. In what follows, let S be a fixed surface, G be a graph embedded in S and L a list assignment such that, for every vertex v of G, L(v) has size at least five. First, the thesis provides an independent proof of a theorem of DeVos, Kawarabayashi and Mohar that says if G has large edge-width, then G is 5-list-colorable. Moreover, the bound on the edge-width is improved from exponential to logarithmic in the Euler genus of S, which is best possible up to a multiplicative constant. Second, the thesis proves that there exist only finitely many 6-list-critical graphs embeddable in S, solving a conjecture of Thomassen from 1994. Indeed, it is shown that the number of vertices in a 6-list-critical graph is at most linear in genus, which is best possible up to a multiplicative constant. As a corollary, there exists a linear-time algorithm for deciding 5-list-colorability of graphs embeddable in S. Furthermore, we prove that the number of L-colorings of an L-colorable graph embedded in S is exponential in the number of vertices of G, with a constant depending only on the Euler genus g of S. This resolves yet another conjecture of Thomassen from 2007. The thesis also proves that if X is a subset of the vertices of G that are pairwise distance Omega(log g) apart and the edge-width of G is Omega(log g), then any L-coloring of X extends to an L-coloring of G. For planar graphs, this was conjectured by Albertson and recently proved by Dvorak, Lidicky, Mohar, and Postle. For regular coloring, this was proved by Albertson and Hutchinson. Other related generalizations are examined.

The title Savage Ballet came into being because, so far as I articulate, it aptly describes the beauty and horror that are borne from combining art and instruction. Poetry, itself, is a ballet. And poetry, itself, is savage. It is a ballet of words carefully choreographed and practiced and spun into being. Poetry is the body politic of the ballet. It is beautiful and often fancy when the curtain rises, but behind the scenes and tucked into toe shoes is the instruction – the gnashing of teeth and blisters and broken nails. Thus, the savage side of poetry presents itself. And, may it also be said, graduate school is a savage beast. It wrestles and tests and knocks down to build up. And, if the dancer is lucky, they will rise.

This thesis discusses cache oblivious data structures. These are structures which have good caching characteristics without knowing Z, the size of the cache, or L, the length of a cache line. Since the structures do not require these details for good performance they are portable across caching systems. Another advantage of such structures isthat the caching results hold for every level of cache within a multilevel cache. Two simple data structures are studied; the array used for binary search and the linear list. As well as being cache oblivious, the structures presented in this thesis are space efficient, requiring little additional storage. We begin the discussion with a layout for a search tree within an array. This layout allows Searches to be performed in O(log n) time and in O(log n/log L) (the optimal number) cache misses. An algorithm for building this layout from a sorted array in linear time is given. One use for this layout is a heap-like implementation of the priority queue. This structure allows Inserts, Heapifies and ExtractMaxes in O(log n) time and O(log nlog L) cache misses. A priority queue using this layout can be builtfrom an unsorted array in linear time. Besides the n spaces required to hold the data, this structure uses a constant amount of additional storage. The cache oblivious linear list allows scans of the list taking Theta(n) time and incurring Theta(n/L) (the optimal number) cache misses. The running time of insertions and deletions is not constant, however it is sub-polynomial. This structure requires e*n additional storage, where e is any constant greater than zero.

Modern architectures allow multiple instructions to be issued at once and have other complex features. To account for this, compilers perform instruction scheduling after generating the output code. The instruction scheduling problem is to find an optimal schedule given the limitations and capabilities of the architecture. While this can be done optimally, a greedy algorithm known as list scheduling is used in practice in most production compilers. <br /><br /> List scheduling is generally regarded as being near-optimal in practice, provided a good choice of heuristic is used. However, previous work comparing a list scheduler against an optimal scheduler either makes the assumption that an idealized architectural model is being used or uses too few test cases to strongly prove or disprove the assumed near-optimality of list scheduling. It remains an open question whether or not list scheduling performs well when scheduling for a realistic architectural model. <br /><br /> Using constraint programming, we developed an efficient optimal scheduler capable of scheduling even very large blocks within a popular benchmark suite in a reasonable amount of time. I improved the architectural model and optimal scheduler by allowing for an issue width not equal to the number of functional units, instructions that monopolize the processor for one cycle, and non-fully pipelined instructions. I then evaluated the performance of list scheduling for this more realistic architectural model. <br /><br /> I found that when scheduling for basic blocks when using a realistic architectural model, only 6% or less of schedules produced by a list scheduler are non-optimal, but when scheduling for superblocks, at least 40% of schedules produced by a list scheduler are non-optimal. Furthermore, when the list scheduler and optimal scheduler differed, the optimal scheduler was able to improve schedule cost by at least 5% on average, realizing maximum improvements of 82%. This suggests that list scheduling is only a viable solution in practice when scheduling basic blocks. When scheduling superblocks, the advantage of using a list scheduler is its speed, not the quality of schedules produced, and other alternatives to list scheduling should be considered.

This degree project concludes the Innovation and Design Engineering programme at Karlstad University. The project was carried out by David Brocker, Erik Hallberg and Andreas Hertzman during the spring of 2006 and corresponded to 15 weeks of work per student. Assigner was Martin Larsson at Arexor and instructor at Karlstad University was Monica Jakobsson. Arexor has a patent to a construction of an electrical skirting board with moveable wall sockets, called Electrical Track System. The lowest parts of the interior walls along the floor are today almost always covered by a conventional skirting board. Arexors patented product replaces that with the possibility to move and increase the number of wall sockets by choice along an electrical skirting board. Conventional wall sockets are limited due to fixed positions and are not transferable. It causes a problem when the number of fixed wall sockets controls the possibilities and not the users demand. The assignment commissioned by Arexor to the students was to improve and develop the Electrical Track System because the patent did not fulfil the requirements for CE certification. The project results were to be used by Arexor as the basic data when the product was tested by ETL SEMKO. The objective of the project was to present directions for production to a functioning prototype of the Electrical Track System, within the estimated time period. The prototype was to be shown at the exhibition for degree projects at Karlstad University in May 2006. The objective also included to create a product brochure and a display case. The development method were divided into five phases: preparation phase, research phase, idea generating phase, conception development phase and concretisation phase. They were carried out linear up to the conception development phase. Then iteration between the research phase, idea generating phase, conception development phase was repeated until satisfied result was achieved. The result included a number of functioning prototypes, a display case, a product brochure, CAD drawings, renderings and this academic report. The prototypes were manufactured by Modellteknik in Eskilstuna, Sweden. Parts of the result cannot be presented due to that the solutions was not, at the time, protected by the patent. Arexor announced in the end of the project that they would apply for a new patent that included our solutions. Because of that these solutions could not be shown in public. Some parts in the report therefore refer to secrecy. / Detta examensarbete var avslutningen på Innovations- och designingenjörsprogrammet vid Karlstads universitet på fakulteten för teknik- och naturvetenskap. Arbetet genomfördes av David Brocker, Erik Hallberg och Andreas Hertzman under våren 2006 på uppdrag av Arexor och omfattade 15 högskolepoäng per student. Uppdragsgivare på Arexor var Martin Larsson och handledare var Monica Jakobsson från Karlstads universitet. Arexor har patenterat en konstruktion av en elektrisk golvlist med flyttbara vägguttag, kallat Electrical Track System. Längs med golvet utmed väggarna sitter i fastigheter i dag nästan alltid en golvlist. Arexors patenterade produkt ersätter golvlisten och ger möjlighet att bland annat flytta, montera och öka antalet vägguttag längs med listen efter eget behov. Traditionella uttag begränsas av att de har fasta positioner och inte kan omplaceras. Det innebär problem då antalet fasta uttag styr möjligheterna och inte behovet. Uppdraget som Arexor gav projektgruppen var att vidareutveckla Electrical Track System, då patentet inte uppfyllde kraven för CE-certifiering. Resultatet av arbetet skulle sedan användas av Arexor som underlag vid test hos ETL SEMKO. Målet var att ta fram tillverkningsunderlag för en slutgiltig, fungerande prototyp av ETS inom tidsramen för projektet. Den skulle sedan visas på examensutställningen vid Karlstads universitet den 30 maj 2006. Delmål var även att ta fram en produktbroschyr och en utställningsmonter. Arbetet delades in i stegen arbetsplan, förstudie, idégenerering, konceptutveckling och konkretisering. De genomfördes linjärt upp till konceptutvecklingen, sedan skedde en iteration mellan stegen förstudie, idégenerering och konceptutveckling. Det betyder att processen upprepades tills det att önskat resultat uppnåddes. Resultatet blev en mängd olika fungerande prototyper, en utställningsmonter, en produktbroschyr, CAD-ritningar, renderingar och denna akademiska rapport. Prototyperna tillverkades i samarbete med Modellteknik i Eskilstuna. Delar av resultatet redovisas inte på grund av att lösningarna inte vid tidpunkten skyddades av rådande patent. Arexor meddelande i slutet av projektet att företaget skulle ansöka om ett nytt patent där dessa lösningar inkluderades. Det medförde att lösningarna inte fick offentliggöras innan patentansökan hade lämnats in. Därför hänvisas till sekretess i vissa delar av rapporten.