Data conversion is the crucial interface between the real world and digital processing systems. Analogue-to-digital converters and digital-to-analogue converters are two key conversion devices and used as the interface. Up to now, the conventional ADCs based on Nyquist sampling theorem are facing a critical challenge: the resolution and the sampling rate must be radically increased when some applications such as radar detection and ultra-wideband communication emerge. The offset of comparators and the setup time of sample-and-hold circuits, however, limit the resulution and clock rate of ADCs. Alternatively, in some applications such as speech, temperature sensor, etc. signals remain possibly unchanged for prolonged periods with brief bursts of significant activity. If trational ADCs are employed in such circumstances a higher bandwidth is required for transmitting the converted samples. On the other hand, sampling signals with an extremely high clock rate are also required for converting the signals with the feature of sparsity in time domain. The level-crossing sampling scheme (LCSS) is one of the data conversions suitable for converting signals with the sparsity feature and brief bursts of signigicant activity. due to the traditional LCSS with a fixed clock rate being limited in applications a novel irregular data conversion scheme called analogue-to-information system (AIS) is proposed in this thesis. The AIS is typically based upon LCSS, but an adjustable clock generator and a real time data compression scheme are applied to it. As the system-level simulations results of AIS show it can be seen that a data transmission saving rate nearly 30% is achieved for different signals. PLLs with fast pull-in and locking schemes are very important when they are applied in TDMA systems and fequency hopping wireless systems. So a novel triple path nonlinear phase frequency detector (TPNPFD) is also proposed in this thesis. Compared to otherPFDs, the pll-in and locking time in TPNPFD is much shorter. A proper transmission data format can make the recreation of the skipped samples and the reconstruction of the original signal more efficient, i.e. they can be achieved in a minimum number of the received data without increasing much more hardware complexity. So the preliminary data format used for transmitting the converted data from AIS is also given in the final chapter of this thesis for future works.

This thesis presents a systematic top-down methodology for simulating a phase-locked loop using a macro model in Verilog-A. The macromodel has been used to evaluate the jitter due to supply noise, thermal noise, and ground bounce. The noise simulation with the behavioral model is roughly 310 times faster (best case) and 125 times faster (worst case). The accuracy of the model depends on the accurate evaluation of the non-linear transfer function from the various noisy nodes to the output. By modeling the noise transfer function of the circuit as closely as possible, 100% accuracy for the behavioral noise simulations compared with the HSPICE noise simulations is obtained. The macro model is written for a charge-pump phase-locked loop, but can be easily extended to other architectures. The simulations are completed using SpectreS in Cadence. The designer can use the model to estimate the jitter at the output of the PLL in a top-down design methodology or cross verify the performance of an existing chip in a bottom-up approach. / Graduation date: 2001

Graduation date: 2006 / Digital phase-locked loops (PLLs) have been receiving increasing attention recently due to their ease of integration, scalability and performance comparable to their analog counterparts. In digital PLLs, increased resolution in time-to-digital conversion is desirable for improved noise performance. This work describes the design and simulation of a stochastic time-to-digital converter (STDC) for a digital PLL to attain high resolution. The converter is intended to comprise the fine loop of the phase-frequency detector, whose coarse loop would be comprised of a time-to-digital converter designed using the conventional delay-chain approach. The STDC is designed, simulated and sent for fabrication in a 0.35μm SOI CMOS process. System level simulations in MATLAB are verified by device level simulations in Spectre on circuits extracted from layout. The results support the viability of using the proposed circuit for high resolution time-to-digital conversion.

Thesis (Ph.D.)--University of Texas at Arlington, 2009.

Thesis (Ph. D.)--University of Washington, 2001. / Vita. Includes bibliographical references (leaves 68-72).

Thesis (M.Phil.)--Hong Kong University of Science and Technology, 2003. / Includes bibliographical references. Also available in electronic version. Access restricted to campus users.

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published_or_final_version / Electrical and Electronic Engineering / Master / Master of Philosophy

Thesis (M. App. Sc.)--Carleton University, 2003. / Includes bibliographical references (p. 103-105). Also available in electronic format on the Internet.