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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
41

Phase alignment of asynchronous external clock controllable devices to periodic master control signal using the Periodic Event Synchronization Unit

Ostrander, Charles Nicholas. January 2009 (has links) (PDF)
Thesis (MS)--Montana State University--Bozeman, 2009. / Typescript. Chairperson, Graduate Committee: Brock LaMeres. Includes bibliographical references (leaves 64-66).
42

Frequency dividers design for multi-GHz PLL systems

Barale, Francesco January 2008 (has links)
Thesis (M. S.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2008. / Committee Chair: Laskar Joy; Committee Member: Cressler John; Committee Member: Tentzeris Emmanouil
43

Design techniques for radiation hardened phase-locked loops /

Nemmani, Anantha Nag. January 1900 (has links)
Thesis (M.S.)--Oregon State University, 2006. / Printout. Includes bibliographical references (leaves 47-48). Also available on the World Wide Web.
44

A fractional N frequency synthesizer for an adaptive network backplane serial communication system

Rangan, Giri N. K., January 1900 (has links) (PDF)
Thesis (Ph. D.)--University of Texas at Austin, 2005. / Vita. Includes bibliographical references.
45

Low-noise and high-frequency clock generation core for VLSI CMOS integration

Robinson, Moises Emanuel, January 1900 (has links) (PDF)
Thesis (Ph. D.)--University of Texas at Austin, 2005. / Vita. Includes bibliographical references.
46

On real time digital phase locked loop implementation with application to timing recovery : a thesis submitted in partial fulfillment of the requirements for the degree of Master of Engineering in Electrical and Electronic Engineering at the University of Canterbury, Christchurch, New Zealand /

Kippenberger, Roger. January 1900 (has links)
Thesis (M.E.)--University of Canterbury, 2006. / Typescript (photocopy). "November 2006." Includes bibliographical references (leaves 121-124). Also available via the World Wide Web.
47

Analysis and Design of Phase Locked Loops with insight into Wavelet Analysis

Barat, Aakriti 18 May 2017 (has links)
No description available.
48

UHF Frequency Synthesizer

Shenefelt, Christopher W. 01 January 1985 (has links) (PDF)
This thesis describes the design, implementation and testing of a UHF frequency synthesizer. The synthesizer is designed to provide a sine wave output programmable from 400 MHz to 500 MHz in 0.1 MHz increments. The synthesis technique utilized is Digital Coherent Indirect Synthesis. This technique uses phase locking to provide a range of stable output frequencies all derived from a single crystal reference. Component design and system level analysis are presented in detail.
49

Extending the Flexibility of an RFIC Transceiver Through Modifications to the External Circuit

Marshall, Scott D. 09 June 1999 (has links)
The recent trend in the RF and microwave industry has been a move towards increasing the number of components realized on one radio frequency integrated circuit (RFIC) (or microwave integrated circuit (MIC)). This trend has resulted in complex RFICs which often require reactive as well as other circuit components to be supplied in the form of an external circuit. Because the manufacturer's suggested circuit is often developed with a specific application in mind, the same circuit may not satisfy the demands of another application. Provided the necessary functionality and connections are possible, the external circuit may be altered such that the requirements of the other application can be met, thus extending the flexibility of the RFIC. The work presented here is focused on investigating modifications to RF Microdevices' suggested external circuit for the RF29X5 family of low cost, half duplex, FM/AM/ASK/FSK RFIC transceivers originally intended for operation in the 433, 868, or 902-928 MHz industrial, scientific, and measurement (ISM) bands. Examinations of the operating principles of the transceiver components were performed which facilitated the identification of suitable modifications. Among the modifications identified were implementation of a phase locked detector, various methods for extending the FSK data rate limitations of the transmitter, improving the phase noise of the VCO, and the implementation of a fractional-N synthesizer using the RF2905 internal phase-locked loop (PLL) components and external inexpensive logic circuits. In addition to these modifications to the external circuit, the investigation of the oscillators of the RF2905 resulted in a potentially improved implementation of the VCO by modifying the internal active circuitry as well. / Master of Engineering
50

Design of a phase locked loop clock recovery and data re-timing circuit for 50 to 800 mbps NRZ-L data

Eisenhauer, Nancy L. 01 July 2000 (has links)
No description available.

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