Thesis (M.App.Sc.) - Carleton University, 2007. / Includes bibliographical references (p. 111-113). Also available in electronic format on the Internet.

Thesis (M. Eng.)--Carleton University, 1992. / Also available in electronic format on the Internet.

Thesis (Ph. D.)--Carleton University, 1999. / Also available in electronic format on the Internet.

Thesis (Ph. D.)--University of Washington, 2006. / Vita. Includes bibliographical references (leaves 152-157).

Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2006. / Swaminathan, Madhavan, Committee Chair ; Cressler, John D., Committee Co-Chair ; Kenney, Stevenson J., Committee Member ; Peterson, Andrew, Committee Member ; Durgin, Gregory, Committee Member ; Sitaraman, Suresh, Committee Member.

Thesis (Ph. D.)--Oregon State University, 2007. / Printout. Includes bibliographical references (leaves 107-110). Also available online.

O presente trabalho propõe-se a oferecer respostas à questão de como a informação é preservada num sistema, focalizando-se na distinção entre os papéis desempenhados pelos constituintes elementares e pelos estruturais na preservação da memória desse sistema. Os sistema simulados circunscreveram-se a malhas, com diferentes graus de regularidade, compostas pelo acoplamento de osciladores não-lineares que apresentam comportamento coerente no estado de equilíbrio. Malhas de Sincronismo de Fase, também conhecidas por PLLs (Phase Locked Loops), foram adotadas como elementos constituintes básicos dos sistemas analisados. Para tanto, utilizou-se a plataforma de cálculo MATLAB-SIMULINK, acompanhando-se as evoluções dos diversos sistemas e de seus parâmetros dinâmicos associados, possibilitando o estabelecimento da correspondência entre os valores dos referidos parâmetros dinâmicos com parâmetros gráficos \"sensíveis\" à estrutura das malhas. Os resultados obtidos indicam a coexistência/cooperação das componentes estrutural e elementar na determinação dos valores dos parâmetros dinâmicos no estado de equilíbrio do sistema. No entanto, evidencia-se que tais componentes apresentam importâncias distintas na determinação dos diferentes parâmetros dinâmicos. / This work was conceived aiming to present some answers to how the information is preserved in a system. The focus was laid on the distinction between the tasks played by the elementary components and the structure of the system. The simulated systems were composed by coupled oscillators, more precisely by PLLs (Phase Locked Loops), arranged in networks of different regularities. Simulations were performed using Matlab-Simulink software to build a correlation between the final state dynamical parameters of the system and its degree of regularity. Results show the influence of both elementary and structural components on the system attained state. However the responses of characteristics parameters of the system to changes in the regularity of the structured network may greatly differ from one parameter to another. This behavior may suggest different strategies to preserve information of the system according to the information to be kept.

In recent years, neuromorphic architectures have been an increasingly effective tool used to solve big data problems. Hardware neural networks have not been able to fully exploit the power efficient properties of the neural paradigm, however, due to limitations in standard CMOS. One of the largest challenges is the quadratic scaling of the synapses in a neural network. There has been some work in using post CMOS technology as synapses to overcome this limitation, but systems to date have not been scalable due to the design of their neurons. This dissertation aims to design and build scalable neural network architectures that can use emerging resistive memory technology as synapses. Using analog computing techniques to build networks is promising, especially due to the development of dense, CMOS compatible analog resistive memories. Building functional analog networks in advanced technology nodes, however, is challenging due to the relatively poor performance of analog components in these nodes. This work explores oscillatory neural networks (ONNs), which use phase as the analog state variable instead of voltage or current, reducing the number of traditional analog components required and making the networks better-suited for advanced nodes. This thesis develops additional ONN theory with regard to hardware networks, since previous work did not consider the effect of transmission delay on network dynamics. Transmission delay is proven to cause desynchronization in unmodified ONNs, and the theoretical analysis suggests ways to build networks which do synchronize. Conclusions from the theoretical development are used to build a PLL-based ONN in hardware. The PLL-based ONN is more energy efficient than comparable systems implemented in digital CMOS, although the neuron area is somewhat larger. The measurement of the PLL-based ONN also reveals additional poorly-studied facets of ONN dynamics. Using the knowledge gained from the PLL-based ONN, a larger, PLL-free ONN is built in the same technology. Removing the PLL in each neuron reduces the power and area consumption without sacrificing any functionality.This dissertation demonstrates that ONNs are well-suited to take advantage of emerging resistive memory technology to build efficient hardware neural networks.

Thesis: M.S., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 1976 / Includes bibliographical references. / M.S. / M.S. Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science

Phase Synthesis is a fundamental operation in Smart Antennas and other Phased Array systems based on beamforming. There are increasing commercial applications for Integrated Phased Arrays due to their low cost, size and power and also because the RF and digital signal processing can be performed on the same chip. These low cost beamforming applications have augmented interest in Coupled Phase Locked Loop (CPLL) systems for Phase Synthesis. Previous work on the implementation of Phase Synthesis systems using Coupled PLLs for low cost beamforming had the constraint of a limited phase range of ±90°. The idea behind the thesis is that this phase synthesis range can be increased to ±180° through the use of PLLs employing Phase Frequency Detectors(PFDs), which is a significant improvement over conventional coupled-PLL systems. This work presents the detailed design and measurement results for a phase synthesizer using Coupled PLLs for achieving phase shift in the range of ±180°. Several Coupled PLL architectures are investigated and their advantages and limitations are evaluated in terms of frequency controllability, phase difference synthesis control and phase noise of the systems. A two-PLL system implementation using off the shelf components is presented, which generates a steady-state phase difference in the range ±180° using an adjustable DC control current. This is the proof of concept for doing an IC design for a Coupled Phase Locked Loop system. Commercial applications in the Wireless Medical Telemetry Service (WMTS) band motivate the design of a CPLL system in the 608-614 MHz band. The design methodology is presented which shows the flowchart of the IC design process from the system design specifications to the transistor level design. MATLAB simulations are presented to model the system performance quickly. VerilogA modeling of the CPLL system is performed followed by the IC design of the system and each block is simulated under different process and temperature corners. The transistor level design is then evaluated for its performance in terms of phase difference synthesis and phase noise and compared with the initial MATLAB analysis and improved iteratively. The CPLL system is implemented in IBM 130nm CMOS process and consumes 40mW of power from a 1.2V supply with a phase noise performance of -88 dBc/Hz for 177° phase generation.