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Within recent years, interest in the installation of solar-based, wind-based, and various other renewable Distributed Energy Resources (DERs) and Energy Storage (ES) systems has risen; in part due to rising energy costs, demand for cleaner power generation, increased power quality demands, and the need for additional protection against brownouts and blackouts. A viable solution for these requirements consists of installation of small-scale DER and ES systems at the single-phase (1Φ) distribution level to provide ancillary services such as peak load shaving, Static-VAr Compensation (STATCOM), ES, and Uninterruptable Power Supply (UPS) capabilities through the creation of microgrid systems. To interconnect DER and ES systems, power electronic converters are needed with not only control systems that operate in multiple modes of operation, but with islanding detection and resynchronization capabilities for isolation from and reclosure to the grid. The proposed system includes control architecture capable of operating in multiple modes, and with the ability to smoothly transfer between modes. Phase-Locked Loops (PLLs), islanding detection schemes, and resynchronization protocols are developed to support the control functionality proposed. Stationary frame PLL developments proposed in this work improve upon existing methods by eliminating steady-state noise/ripple without using Low-Pass Filters (LPFs), increasing frequency/phase tracking speeds for a wide range of disturbances, and retaining robustness for weakly interconnected systems. An islanding detection scheme for the stationary frame control is achieved through the stability of the PLL system interaction with the converter control. The proposed detection method relies upon the conditional stability of the PLL controller which is sensitive to grid-disconnections. This method is advantageous over other methods of active islanding detection mainly due to the need for those methods to perturb the output to test for islanding conditions. The PLL stability method does not inject signal perturbations into the output of the converter, but instead is designed to be stable while grid-connected, but inherently unstable for grid-disconnections. Resynchronization and reclosure to the grid is an important control aspect for microgrid systems that have the ability to operate in stand-alone, backup modes while disconnected from the grid. The resynchronization method proposed utilizes a dual PLL tracking system which minimizes voltage transients during the resynchronization process; while a logic-based reclosure algorithm ensures minimal magnitude, frequency, and phase mismatches between the grid and an isolated microgrid system to prevent inrush currents between the grid and stand-alone microgrid system. / Ph. D.

Networked wireless sensor systems have the potential to play a major role in critical applications including: environmental monitoring of chemical/biological attacks; condition-based maintenance of vehicles, ships and aircraft; real-time monitoring of civil infrastructure including roads, bridges etc.; security and surveillance for homeland defense systems; and battlefield surveillance and monitoring. Such wireless sensor networks can provide remote monitoring and control of operations of large-scale systems using low-power, low-cost, "throw-away" sensor nodes. This thesis focuses on two aspects of wireless sensor node development: (1) post-IC assembly of nanosensor devices onto prefabricated complementary-metal-oxide-semiconductor (CMOS) integrated circuits using a technique called dielectrophoretic (DEP) assembly; and (2) design of a low-power SiGe BiCMOS multi-band ultra-wideband (UWB) transmitter for wireless communications with other nodes and/or a central control unit in a wireless sensor network. For the first part of this work, a DEP assembly test chip was designed and fabricated using the five-metal core CMOS platform technology of Motorola's HiP6W low-voltage 0.18_m Si/SiGe BiCMOS process. The CMOS chip size was 2.5mm x 2.5 mm. The required AC signal for assembling nanowires is provided to the bottom electrodes defined in the Metal 4 (M4) layer of the IC process. This signal is then capacitively coupled to the top/assembly electrodes defined in the top metal (M5) layer that is also interconnected to appropriate readout circuitry. The placement and alignment of the nanowires on the top electrodes are defined by dielectrophoretic forces that act on the nanowires. For proof of concept purposes, metallic rhodium nanowires ((length = 5μm and diameter = 250 nm) were used in this thesis to demonstrate assembly onto the prefabricated CMOS chip. The rhodium nanowires were manufactured using a nanotemplated electroplating technique. In general, the DEP assembly technique can be used to manipulate a wider range of nanoscale devices (nanowire sensors, nanotubes, etc.), allowing their individual assembly onto prefabricated CMOS chips and can be extended to integrate diverse functionalized nanosensors with sensor readout, data conversion and data communication functionalities in a single-chip environment. In addition, this technique provides a highly-manufacturable platform for the development of multifunctional wireless sensor nodes based on assembled nano-sensor devices. The resistances of the assembled nanowires were measured to be on the order of 110 Ω consistent with prior prototype results. Several issues involved in achieving successful assembly of nanowires and good electrical continuity between the nanowires and metal layers of IC processes are addressed in this thesis. The importance of chemical/mechanical planarization (CMP) technique in modern IC processes and considerations for electrical isolation of readout circuit from the assembly sites are discussed. For the second part of this work, a multi-band hopping ultrawideband transmitter was designed to operate in three different frequency bands namely, 4.8 GHz, 6.4 GHz and 8.0 GHz. As a part of this effort, this thesis includes the design of a CMOS phase/frequency detector (PFD), a CMOS pseudo-random code generator and an on-chip passive loop filter, which were designed for the multi-band PLL frequency synthesizer. The CMOS PFD provided phase tracking over a range of -2π to +2π radians. The on-chip passive loop filter was designed for a 62_ phase margin, 250 μA-charge pump output current and 4 MHz-PLL loop-bandwidth. The CMOS pseudorandom code generator provided a two-bit output that helped switch the frequency bands of the UWB transmitter. With all these components, along with a BiCMOS VCO, a CMOS charge pump and a CMOS frequency divider, the simulated PLL frequency synthesizer locked within a relatively short time of 700ns in all three design frequency bands. The die area for the multi-band UWB transmitter as laid out was 1.5 mm x 1.0 mm. Future work proposed by this thesis includes sequential assembly of diverse functionalized gas/chemical nanosensor elements into arrays in order to realize highly sensitive "electronic noses". With integration of such diverse functionalized nano-scale sensors with low-power read-out and data communication system, a versatile and commercially viable low-power wireless sensor system can be realized. / Master of Science

Continuous Phase Frequency Shift Keying (CPFSK) is a constant amplitude modulation of growing popularity in low earth orbit satellites (LEOSAT) because of its spectral efficiency. This thesis compares the error rate performance of CPFSK demodulation using quadrature detectors and phase-locked loops under varying carrier to noise ratios and simulated Doppler shifts, as might be expected for a low earth orbit satellite downlink. Experimental comparison between a quadrature detector and a phase-locked loop demodulator shows that phase-locked loop demodulators and quadrature detectors offer equivalent performance as demodulators at low carrier to noise ratios for narrowband FM/CPFSK systems. This contrasts with earlier work that shows that phase-locked loops can provide threshold extension for wideband FM systems. / M.S.

Cheng Sin-hang. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2002. / Includes bibliographical references (leaves 90-92). / Abstracts in English and Chinese. / Chapter Chapter 1 --- Introduction --- p.1 / Chapter Chapter 2 --- Theory of Oscillator Design --- p.4 / Chapter 2.1 --- Open-loop approach --- p.4 / Chapter 2.2 --- One-port approach --- p.6 / Chapter 2.3 --- Two-port approach --- p.9 / Chapter 2.4 --- Voltage controlled oscillator (VCO) design --- p.10 / Chapter 2.4.1 --- Active device selection and biasing --- p.11 / Chapter 2.4.2 --- Feedback circuit design --- p.15 / Chapter 2.4.3 --- Frequency tuning circuit --- p.20 / Chapter Chapter 3 --- Noise in Oscillators --- p.23 / Chapter 3.1 --- Origin of phase noise --- p.23 / Chapter 3.2 --- Impact of phase noise in communication system --- p.28 / Chapter 3.3 --- Phase noise consideration in VCO design --- p.30 / Chapter Chapter 4 --- Low Temperature Co-Fired Ceramic --- p.31 / Chapter 4.1 --- LTCC process --- p.31 / Chapter 4.1.1 --- LTCC fabrication process --- p.32 / Chapter 4.1.2 --- LTCC materials --- p.34 / Chapter 4.1.3 --- Advantages of LTCC technology --- p.35 / Chapter 4.2 --- Passive components realization in LTCC --- p.37 / Chapter 4.2.1 --- Capacitor --- p.37 / Chapter 4.2.2 --- Inductor --- p.42 / Chapter Chapter 5 --- High-Q LTCC Resonator Design --- p.47 / Chapter 5.1 --- Definition of Q-factor --- p.47 / Chapter 5.2 --- Stripline --- p.50 / Chapter 5.3 --- Power losses --- p.52 / Chapter 5.4 --- Laminated stripline resonator design --- p.53 / Chapter 5.4.1 --- λ/4 resonator structure --- p.57 / Chapter 5.4.2 --- Meander-line resonator structure --- p.60 / Chapter 5.4.3 --- Bi-metal-layer resonator structure --- p.63 / Chapter Chapter 6 --- LTCC Voltage Controlled Oscillator Design --- p.67 / Chapter 6.1 --- Circuit design --- p.67 / Chapter 6.2 --- Output filter --- p.68 / Chapter 6.3 --- Embedded capacitor --- p.71 / Chapter 6.4 --- VCO layout and simulation --- p.72 / Chapter Chapter 7 --- Experimental Setup and Results --- p.77 / Chapter 7.1 --- Measured Result: LTCC resonators --- p.77 / Chapter 7.1.1 --- Experimental results --- p.79 / Chapter 7.2 --- Measured results: LTCC voltage controlled oscillators --- p.83 / Chapter Chapter 8 --- Conclusion and Future Work --- p.88 / Reference List --- p.90 / Appendix A: TRL calibration method --- p.93 / Appendix B: Q measurement --- p.103 / Appendix C: Q-factor extraction program listing --- p.109 / Chapter 1. --- Function used to calculate Q from s-parameter --- p.109 / Chapter 2. --- Function used to calculate Q from z-parameter --- p.111

Yip Kim-fung. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2002. / Includes bibliographical references (leaves 95-100). / Abstracts in English and Chinese. / Abstract --- p.I / Acknowledgement --- p.III / Table of Contents --- p.IV / Chapter Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Motivation --- p.1 / Chapter 1.2 --- Objective --- p.6 / Chapter Chapter 2 --- Theory of Oscillators --- p.7 / Chapter 2.1 --- Oscillator Design --- p.7 / Chapter 2.1.1 --- Loop-Gain Method --- p.7 / Chapter 2.1.2 --- Negative Resistance-Conductance Method --- p.8 / Chapter 2.1.3 --- Crossed-Coupled Oscillator --- p.10 / Chapter Chapter 3 --- Noise Analysis --- p.15 / Chapter 3.1 --- Origin of Noise Sources --- p.16 / Chapter 3.1.1 --- Flicker Noise --- p.16 / Chapter 3.1.2 --- Thermal Noise --- p.17 / Chapter 3.1.3 --- Noise Model of Varactor --- p.18 / Chapter 3.1.4 --- Noise Model of Spiral Inductor --- p.19 / Chapter 3.2 --- Derivation of Resonator --- p.19 / Chapter 3.3 --- Phase Noise Model --- p.22 / Chapter 3.3.1 --- Leeson's Model --- p.23 / Chapter 3.3.2 --- Phase Noise Model defined by J. Cranincks and M Steyaert --- p.24 / Chapter 3.3.3 --- Non-linear Analysis of Phase Noise --- p.26 / Chapter 3.3.4 --- Flicker-Noise Upconversion Mechanism --- p.31 / Chapter 3.4 --- Phase Noise Reduction Techniques --- p.33 / Chapter 3.4.1 --- Conventional Tank Circuit Structure --- p.33 / Chapter 3.4.2 --- Enhanced Q tank circuit Structure --- p.35 / Chapter 3.4.3 --- Tank Circuit with parasitics --- p.37 / Chapter 3.4.4 --- Reduction of Up-converted Noise --- p.39 / Chapter Chapter 4 --- CMOS Technology and Device Modeling --- p.42 / Chapter 4.1 --- Device Modeling --- p.42 / Chapter 4.1.1 --- FET model --- p.42 / Chapter 4.1.2 --- Layout of Interdigitated FET --- p.46 / Chapter 4.1.3 --- Planar Inductor --- p.48 / Chapter 4.1.4 --- Circuit Model of Planar Inductor --- p.50 / Chapter 4.1.5 --- Inductor Layout Consideration --- p.54 / Chapter 4.1.6 --- CMOS RF Varactor --- p.55 / Chapter 4.1.7 --- Parasitics of PMOS-type varactor --- p.57 / Chapter Chapter 5 --- Design of Integrated CMOS VCOs --- p.59 / Chapter 5.1 --- 1.5GHz CMOS VCO Design --- p.59 / Chapter 5.1.1 --- Equivalent circuit model of differential LC VCO --- p.59 / Chapter 5.1.2 --- Reference Oscillator Circuit --- p.61 / Chapter 5.1.3 --- Proposed Oscillator Circuit --- p.62 / Chapter 5.1.4 --- Output buffer --- p.63 / Chapter 5.1.5 --- Biasing Circuitry --- p.64 / Chapter 5.2 --- Spiral Inductor Design --- p.65 / Chapter 5.3 --- Determination of W/L ratio of FET --- p.67 / Chapter 5.4 --- Varactor Design --- p.68 / Chapter 5.5 --- Layout (Cadence) --- p.69 / Chapter 5.6 --- Circuit Simulation (SpectreRF) --- p.74 / Chapter Chapter 6 --- Experimental Results and Discussion --- p.76 / Chapter 6.1 --- Measurement Setup --- p.76 / Chapter 6.2 --- Measurement results: Reference Oscillator Circuit --- p.81 / Chapter 6.2.1 --- Output Spectrum --- p.81 / Chapter 6.2.2 --- Phase Noise Performance --- p.82 / Chapter 6.2.3 --- Tuning Characteristic --- p.83 / Chapter 6.2.4 --- Microphotograph --- p.84 / Chapter 6.3 --- Measurement results: Proposed Oscillator Circuit --- p.85 / Chapter 6.3.1 --- Output Spectrum --- p.85 / Chapter 6.3.2 --- Phase Noise Performance --- p.86 / Chapter 6.3.3 --- Tuning Characteristic --- p.87 / Chapter 6.3.4 --- Microphotograph --- p.88 / Chapter 6.4 --- Comparison of Measured Results --- p.89 / Chapter 6.4.1 --- Phase Noise Performance --- p.89 / Chapter 6.4.2 --- Tuning Characteristic --- p.90 / Chapter Chapter 7 --- Conclusion and Future Work --- p.93 / Chapter 7.1 --- Conclusion --- p.93 / Chapter 7.2 --- Future Work --- p.94 / References --- p.95 / Author's Publication --- p.100 / Appendix A --- p.101 / Appendix B --- p.104 / Appendix C --- p.106

Digital communication systems invariably employ an underlying analog communication channel. At the transmitter, data is modulated to obtain an analog waveform which is input to the channel. At the receiver, the output of the channel needs to be mapped back into the discrete domain. To this effect, the continuous-time received waveform is sampled at instants chosen by the timing recovery block. Therefore, timing recovery is an essential component of digital communication systems. A widely used timing recovery method is based on a phase-locked loop (PLL), which updates its timing estimates based on a decision-directed device. Timing recovery performance is a strong function of the reliability of decisions, and hence, of the channel signal-to-noise ratio (SNR). Iteratively decodable error-control codes (ECCs) like turbo codes and LDPC codes allow operation at SNRs lower than ever before, thus exacerbating timing recovery. We propose iterative timing recovery, where the timing recovery block, the equalizer and the ECC decoder exchange information, giving the timing recovery block access to decisions that are much more reliable than the instantaneous ones. This provides significant SNR gains at a marginal complexity penalty over a conventional turbo equalizer where the equalizer and the ECC decoder exchange information. We also derive the Cramer-Rao bound, which is a lower bound on the estimation error variance of any timing estimator, and propose timing recovery methods that outperform the conventional PLL and achieve the Cramer-Rao bound in some cases. At low SNR, timing recovery suffers from cycle slips, where the receiver drops or adds one or more symbols, and consequently, almost always the ECC decoder fails to decode. Iterative timing recovery has the ability to corrects cycle slips. To reduce the number of iterations, we propose cycle slip detection and correction methods. With iterative timing recovery, the PLL with cycle slip detection and correction recovers most of the SNR loss of the conventional receiver that separates timing recovery and turbo equalization.

A Delay-Locked Loop (DLL) for the generation of multiple clock phases/delays is proposed. Several new techniques are used to help enhance the DLLs performance, specifically, to achieve wide lock range, short locking time, and reduced jitter. The DLL can be used for a variety of applications which require precise time intervals or phase shifts. The phase detector (PD), charge pump (CP), and voltage-controlled delay line (VCDL) are the three most important blocks in a DLL. In our research, we have proposed a novel structure which integrates the functionality of both the PD and CP. By using this structure, a fast switching speed can be achieved. Moreover, the combined PD and CP also lead to reduced chip area and better jitter performance. A novel phase detection algorithm is developed and implemented in the combined PD and CP structure. This algorithm also involves a start-control circuit to avoid locking failure or false lock to harmonics. With the help of this algorithm, the proposed DLL is able to achieve lock as long as the minimum VCDL delay is less than one reference clock cycle, which is the largest possible lock range that can be achieved by the DLL. The VCDL uses fully differential signaling to minimize jitter. The delay stage of the VCDL is built with a differential topology using symmetrical loads and replica-feedback biasing, which provides a low sensitivity to supply and substrate noise as well as a wide tuning range. In addition, a shift-averaging technique is used to improve the matching between delay stages and thus to equalize the delay of each individual stage.

The object of this research is to develop robust wire-line systems which demonstrate high performance while simultaneously consuming low power. The main focus of this work is the Clock and Data Recovery (CDR) system, which is the primary circuit of any modern wire-line transceiver. Different techniques starting from circuit-level to system-level have been investigated in this work to improve the performance of multi-gigabit CDRs. A 62 GHz bandwidth amplifier has been presented to address the need for a scalable amplifier for CDR needs. A new technique has been proposed to improve the radiation immunity of latches, to reduce the BER in CDRs occurring due to package radiations. An injection-lock based clock recovery method was investigated as an alternative to PLL based CDRs as they can be used for burst-mode wire-line communication. The investigation yielded the vulnerability of the method to jitter (false-locking and high jitter transfer), the attenuation of which is critical to commercial CDRs. A novel false-lock detector system has been proposed and demonstrated for the first time as a robust solution to the issue of false-locking of CDRs due to repetitive patterns. The implementation of the final CDR system required the use of an L-C tank VCO, the components of which are generic for all commercial CDRs. A new systematic layout technique for the VCO has been proposed and demonstrated in this work to substantially improve the layout area and the associated parasitics, approximately by 70 %. This new layout addresses a critical yet often neglected part of VCO design. Furthermore, a new concept has been proposed to optimize static dividers with respect to their power consumption and number of devices.

A frequency synthesizer plays a critical role in defining the performance of wireless systems in terms of measures such as operating frequency range, settling time, phase noise and spur performance, and area/power consumption. As the trend in mobile system design has changed from single-standard systems to multi-standard/multi-application systems, the role of frequency synthesizers has become even more important. As the most popular architecture, a phase-locked loop (PLL)-based frequency synthesizer has been researched over the last several decades; however, many unsolved problems related to the PLL-based synthesizer are still waiting for answers. This dissertation addresses key challenges related to fully integrated PLL-based frequency synthesizers, including the problem of large area consumption of passive components, the inherent reference-spur problem, and the problem of trade-offs between integer-N PLLs and fractional-N PLLs. In this dissertation, new techniques and architectures are presented and developed to address those challenges. First, a low-phase-noise ring oscillator and a capacitor multiplier with a high-multiplication factor efficiently minimize the silicon area of sub-components, and a compact programmable delay-locked loop (DLL)-based frequency multiplier is developed to replace the PLL-based frequency synthesizer. Second, the charge-distribution mechanism for suppressing reference spurs is theoretically analyzed, and an edge interpolation technique for implementing the mechanism is developed. Finally, the concept and the architecture of sub-integer-N PLL is proposed and implemented to remove trade-offs between conventional integer-N PLLs and fractional-N PLLs.