Thesis (M.App.Sc.) - Carleton University, 2002. / Includes bibliographical references (p. 93-95). Also available in electronic format on the Internet.

Στα πλαίσια της παρούσας διπλωματικής εργασίας μελετήθηκαν οι βασικές αρχές λειτουργίας και θορύβου στα Phase Locked Loops. Στη συνέχεια σχεδιάστηκε το σχηματικό και το layout ενός PLL μικτού σήματος στο λογισμικό σχεδίασης ολοκληρωμένων κυκλωμάτων, Cadence IC5141. Το κύκλωμα αυτό λειτουργεί σαν συνθέτης συχνοτήτων στην περιοχή των 5GHz, από μία συχνότητα αναφοράς 50MHz, έχει θόρυβο φάσης περίπου 88dBc στο 1MHz από το φορέα και μέση κατανάλωση λιγότερο από 30mW. / Analysis of basic operation principles and noise performance of Phase Locked Loops. Design of a PLL (schematic and layout) in Cadence IC5141.

Desire for low-power, high performance computing has been at core of the symbiotic union between digital circuits and CMOS scaling. While digital circuit performance improves with device scaling, analog circuits have not gained these benefits. As a result, it has become necessary to leverage increased digital circuit performance to mitigate analog circuit deficiencies in nanometer scale CMOS in order to realize world class analog solutions. In this thesis, both circuit and system enhancement techniques to improve performance of clock generators are discussed. The following techniques were developed: (1) A digital PLL that employs an adaptive and highly efficient way to cancel the effect of supply noise, (2) a supply regulated DPLL that uses low power regulator and improves supply noise rejection, (3) a digital multiplying DLL that obviates the need for high-resolution TDC while achieving sub-picosecond jitter and excellent supply noise immunity, and (4) a high resolution TDC based on a switched ring oscillator, are presented. Measured results obtained from the prototype chips are presented to illustrate the proposed design techniques. / Graduation date: 2013 / Access restricted to the OSU Community at author's request from July 16, 2012 - July 16, 2014

The objective of this dissertation is to propose circuit architectures and techniques for built-in test and calibration of phase-locked loops. The design of phase-locked loops is first investigated to achieve a robust performance over process, temperature, voltage corners with minimum overhead. Different design techniques including adding loop programmability, increasing area efficiency, reducing noise immunity, and increasing frequency coverage are discussed. Secondly, built-in testing of phase-lock loops using sensors are proposed for loop dynamic parameters and reference spur. An integrator is designed to extract the subtle response from the system so that target parameters can be predicted. Different testing methodologies are applied different specification testing as well. Finally, an on chip phase-locked loop design is implemented for reference spur calibration. The phase-locked loop is designed with a programmable reference spur range. A static phase offset detector is included to identify the optimal setting of reference spur in the feedback system. The integrated jitter performance is improved by the calibration mechanism. The results of this thesis serve as an on-chip built-in self-test and self-calibration solution for embedded phase-locked loops in a high integration system.

Apresenta-se a evolução dos sitemas de comunicação, com ênfase especial nos sistemas com tecnologia óptica. Discute-se a necessidade contínua do aumento de capacidade de tais sistemas de comunicação, e a consequente repercussão sobre os futuros sistemas ópticos. Em vista da necessidade do aumento de capacidade dos futuros sistemas de comunicação óptica, apresentam-se em seguida duas propostas recentes da literatura, sendo uma referente à realização de um gerador de pulsos ópticos estreitos, e a outra referente à implementação de um extrator de relógio realizado com técnicas ópticas. Apresenta-se um breve resumo da teoria das malhas de sincronismo de fase, ou PLLs, mostrando como as duas propostas discutidas realizam funções típicas desses sistemas. Ressalta-se a necessidade dos PLLs de sistemas ópticos possuirem ganhos de malha (parâmetro K) elevados. Após a caracterização dos requisitos necessários para PLLs de futuros sistemas ópticos, e após um resumo de alguns conceitos necessários da teoria de redes e filtros elétricos, apresentam-se dois tipos de projeto de filtros para aqueles PLLs. As duas formas de projeto tem como objetivo viabilizar o uso de filtros de tipo e ordem arbitrários. Um tipo de projeto visa a realização da função de transferência do PLL com a curva de resposta igual à de um filtro escolhido. O outro tipo de projeto parte da realização do filtro de loop do PLL com as características de um tipo de filtro escolhido, e define métodos para ajustar a função de transferência resultante para esse PLL. Apresentam-se algoritmos para o cálculo de parâmetros importantes nos dois procedimentos. Após a discussão dos dois pontos de vista de projeto, apresentam-se exemplos de realização de PLLs de acordo com as técnicas apresentadas. Para cada exemplo, mostram-se as curvas de resposta em frequência tanto do PLL como do correspondente filtro de loop, bem como o lugar das raízes e a resposta de captura do PLL obtido. O processo de captura foi estudado por simulações que procuram reproduzir o mais fielmente possível as condições reais de implementação, sem entretanto considerar efeitos de ruído. Finalmente, mencionam-se brevemente possíveis linhas de pesquisa futuras, sendo o foco principal o uso de filtros com pólos e zeros finitos. / The evolution of communication systems is discussed, with emphasis on optical technology. Special consideration is given to the continuous need for increasing the capacity of such systems, and the impact over future optical communication. In view of the great demands imposed over the capacity of future optical systems, an overview is presented of two recent proposals found in the literature, one of such proposals being the implementation of a generator of short optical pulses, and the other being a clock extractor device realized through the use of optical techniques. A brief review is made of phase-locked loop (or PLL) theory, to show how the discussed proposals could be used to realize tipical functions found in these systems. The very high loop gains (the so-called parameter K) that must be used in PLLs of optical communication systems are emphasized. After discussion of the necessary characteristics for PLLs of future optical systems, and also after a review of some concepts of the theory of electrical networks and filters, two design procedures for filters to be used in such PLLs are presented. Both designs have the goal of allowing the use of loop filters with any type and order. The first type of design has the objective to realize a PLL transfer function that has a frequency response identical to the response of a chosen type of filter. The other design starts with a chosen type of filter for a PLL loop filter, arriving to an suitable PLL transfer function. Some algorithms for determination of important design parameters are also presented. After the discussion of the two types of design, some examples of PLLs obtained by such methods are presented. For each example, frequency response curves are presented for the PLL and the respective loop filter, as well as the root locus and the capture response for the PLL so obtained. The capture process was studied through the use of simulations with parameters intended to approximate real implementation conditions, although noise effects are not considered. Finally, some possible research lines are discussed, whose main focus is on filters with finite poles and zeros.

Neste trabalho, são estudados os problemas de sincronismo de fase nas redes mestre-escravo de via única (OWMS), nas topologias Estrela Simples, Cadeia Simples e mista, através da Teoria Qualitativa de Equações Diferenciais, com ênfase no Teorema da Variedade Central. Através da Teoria das Bifurcações, analisa-se o comportamento dinâmico das malhas de sincronismo de fase (PLL) de segunda ordem que compõem cada rede, frente às variações nos seus parâmetros constitutivos. São utilizadas duas funções de excitação muito comuns na prática: o degrau e a rampa de fase, aplicadas pelo nó mestre. Em cada caso, discute-se a existência e a estabilidade do estado síncrono. A existência de pontos de equilíbrio não-hiperbólicos, não permite uma aproximação linear, e nesses casos é aplicado o Teorema da Variedade Central. Através dessa rigorosa técnica de simplificação de sistemas dinâmicos é possível fazer uma aproximação homeomórfica em torno desses pontos, preservando a orientação no espaço de fases. Desse modo, é possível determinar, localmente, suas estabilidades. / This work presents stability analysis of the syncronous state for three types of one-way master-slave time distribution network topologies: single star, single chain and both of them, mixed. Using bifurcation theory, the dynamical behavior of second-order phase-locked loops employed to extract the syncronous state in each node is analyzed in function of the constitutive parameters. Two usual inputs, the step and the ramp phase pertubations, are supposed to appear in the master node and, in each case, the existence and stability of the syncronous state are studied. For parameter combinations resulting in non hyperbolic synchronous states, the linear approximation does not provide any information, even about the local behaviour of the system. In this case, the center manifold theorem permits the construction of an equivalent vector field representing the asymptotic behaviour of the original system in the neighborhood of these points. Thus, the local stability can be determined.

Apresenta-se a evolução dos sitemas de comunicação, com ênfase especial nos sistemas com tecnologia óptica. Discute-se a necessidade contínua do aumento de capacidade de tais sistemas de comunicação, e a consequente repercussão sobre os futuros sistemas ópticos. Em vista da necessidade do aumento de capacidade dos futuros sistemas de comunicação óptica, apresentam-se em seguida duas propostas recentes da literatura, sendo uma referente à realização de um gerador de pulsos ópticos estreitos, e a outra referente à implementação de um extrator de relógio realizado com técnicas ópticas. Apresenta-se um breve resumo da teoria das malhas de sincronismo de fase, ou PLLs, mostrando como as duas propostas discutidas realizam funções típicas desses sistemas. Ressalta-se a necessidade dos PLLs de sistemas ópticos possuirem ganhos de malha (parâmetro K) elevados. Após a caracterização dos requisitos necessários para PLLs de futuros sistemas ópticos, e após um resumo de alguns conceitos necessários da teoria de redes e filtros elétricos, apresentam-se dois tipos de projeto de filtros para aqueles PLLs. As duas formas de projeto tem como objetivo viabilizar o uso de filtros de tipo e ordem arbitrários. Um tipo de projeto visa a realização da função de transferência do PLL com a curva de resposta igual à de um filtro escolhido. O outro tipo de projeto parte da realização do filtro de loop do PLL com as características de um tipo de filtro escolhido, e define métodos para ajustar a função de transferência resultante para esse PLL. Apresentam-se algoritmos para o cálculo de parâmetros importantes nos dois procedimentos. Após a discussão dos dois pontos de vista de projeto, apresentam-se exemplos de realização de PLLs de acordo com as técnicas apresentadas. Para cada exemplo, mostram-se as curvas de resposta em frequência tanto do PLL como do correspondente filtro de loop, bem como o lugar das raízes e a resposta de captura do PLL obtido. O processo de captura foi estudado por simulações que procuram reproduzir o mais fielmente possível as condições reais de implementação, sem entretanto considerar efeitos de ruído. Finalmente, mencionam-se brevemente possíveis linhas de pesquisa futuras, sendo o foco principal o uso de filtros com pólos e zeros finitos. / The evolution of communication systems is discussed, with emphasis on optical technology. Special consideration is given to the continuous need for increasing the capacity of such systems, and the impact over future optical communication. In view of the great demands imposed over the capacity of future optical systems, an overview is presented of two recent proposals found in the literature, one of such proposals being the implementation of a generator of short optical pulses, and the other being a clock extractor device realized through the use of optical techniques. A brief review is made of phase-locked loop (or PLL) theory, to show how the discussed proposals could be used to realize tipical functions found in these systems. The very high loop gains (the so-called parameter K) that must be used in PLLs of optical communication systems are emphasized. After discussion of the necessary characteristics for PLLs of future optical systems, and also after a review of some concepts of the theory of electrical networks and filters, two design procedures for filters to be used in such PLLs are presented. Both designs have the goal of allowing the use of loop filters with any type and order. The first type of design has the objective to realize a PLL transfer function that has a frequency response identical to the response of a chosen type of filter. The other design starts with a chosen type of filter for a PLL loop filter, arriving to an suitable PLL transfer function. Some algorithms for determination of important design parameters are also presented. After the discussion of the two types of design, some examples of PLLs obtained by such methods are presented. For each example, frequency response curves are presented for the PLL and the respective loop filter, as well as the root locus and the capture response for the PLL so obtained. The capture process was studied through the use of simulations with parameters intended to approximate real implementation conditions, although noise effects are not considered. Finally, some possible research lines are discussed, whose main focus is on filters with finite poles and zeros.

Inicialmente, apresentam-se características de dispositivos eletrônicos conhecidos como PLLs (phase-locked loops). PLLs são amplamente empregados para se extrair sinais de tempo em canais de comunicação e em aplicações nas quais se deseja controle automático de freqüência. O objeto principal é estudar PLLs analógicos descritos por uma equação diferencial ordinária de terceira ordem. Assim, deduzem-se condições de estabilidade assintótica e identifica-se um regime de caos conservativo, que ocorre sob certas combinações de valores de parâmetros. Três métodos de controle não-linear/caótico são então apresentados e aplicados. Os métodos são os seguintes: o Método de Pyragas via realimentação de variável de estado; o Método de Pyragas com atraso temporal na realimentação; e o Método de Sinha, o qual efetua o controle perturbando um parâmetro do sistema. Simulações numéricas são levadas a cabo a fim de ilustrar o comportamento dinâmico do sistema quando sujeito à ação desses métodos. Este trabalho termina com um estudo de uma rede formada por uma cadeia de PLLs. Condições para soluções síncronas, periódicas e caóticas (dissipativas e conservativas) são deduzidas para tal rede. / Firstly, features of electronic devices known as PLLs (Phase-Locked Loops) are presented. PLLs are widely employed to extract time signals in communication channels and in applications where automatic control of frequency is desired. The main goal is to study analog PLLs described by a third-order nonlinear ordinary differential equation. Thus, conditions for asymptotic stability are derived and a regime of conservative chaos occurring under certain combinations of parameter values is identified. Then, three methods of control of nonlinear/ chaotic dynamics are presented and applied. The methods are the following: the Pyragas method via feedback of state variable; the Pyragas method with time delay in the feedback; and the Sinhas method, which performs the control by disturbing a parameter of the system. Numerical simulations are accomplished in order to illustrate the dynamical behavior of the system when subjected to the action of these methods. This work ends with a study of a single-chain PLL network. Conditions for synchronous, periodic and chaotic (dissipative and conservative) solutions are derived for such a network.

Recent advances in voltage-controlled oscillator (VCO) design and the trend of CMOS processing indicate that the oscillator control is quickly becoming one of the forefront problems in high-frequency and low-phase-noise phase-locked loop (PLL) design. This control centric study explores the limitations and challenges in high-performance analog charge-pump PLLs when they are extended to multiple gigahertz applications. Several problems with performance enhancement and precise oscillator control using analog circuits in low-voltage submicron CMOS processes, coupled with the fact that analog (or semi-digital) oscillators having various advantages over their digitally controlled counterparts, prompted the proposal of the digitally-controlled phase-locked loop. This research, then, investigates a class of otherwise analog PLLs that use a digital control path for driving a current-controlled oscillator. For this purpose, a novel method for control digitization is described where trains of pulses code the phase/frequency comparison information rather than the duration of the pulses: Pulse-Stream Coded Phase-Locked Loop (psc-PLL). This work addresses issues significant to the design of future PLLs through a comparative study of the proposed digital control path topology and improved cutting-edge charge-pump PLLs.

High-speed serial data links are quickly gaining in popularity and replacing the conventional parallel data links in recent years when the data rate of communication exceeds one gigabits per second. Compared with parallel data links, serial data links are able to achieve higher data rate and longer transfer distance. This dissertation is focused on the design of CMOS integrated phase-locked loops (PLLs) and relevant building blocks used in multi-gigabits serial data link transceivers. Firstly, binary phase-locked loops (BPLLs, i.e., PLLs based on binary phase detectors) are modeled and analyzed. The steady-state behavior of BPLLs is derived with combined discrete-time and continuous-time analysis. The jitter performance characteristics of BPLLs are analyzed. Secondly, a 10 Gbps clock and data recovery (CDR) chip for SONET OC- 192, the mainstream standard for optical serial data links, is presented. The CDR is based on a novel referenceless dual-loop half-rate architecture. It includes a binary phase-locked loop based on a quad-level phase detector and a linear frequency-locked loop based on a linear frequency detector. The proposed architecture enables the CDR to achieve large locking range and small jitter generation at the same time. The prototype is implemented in 0.18 μm CMOS technology and consumes 250 mW under 1.8 V supply. The jitter generation is 0.5 ps-rms and 4.8 ps-pp. The jitter peaking and jitter tolerance performance exceeds the specifications defined by SONET OC-192 standard. Thirdly, a fully-differential divide-by-eight injection-locked frequency divider with low power dissipation is presented. The frequency divider consists of a four-stage ring of CML (current mode logic) latches. It has a maximum operating frequency of 18 GHz. The ratio of locking range over center frequency is up to 50%. The prototype chip is implemented in 0.18 μm CMOS technology and consumes 3.6 mW under 1.8 V supply. Lastly, the design and optimization techniques of fully differential charge pumps are discussed. Techniques are proposed to minimize the nonidealities associated with a fully differential charge pump, including differential mismatch, output current variation, low-speed glitches and high-speed glitches. The performance improvement brought by the techniques is verified with simulations of schematics designed in 0.35 μm CMOS technology.