In this dissertation, the development of the first 60 GHz-standard compatible fully integrated 4-channel phase-locked loop (PLL) frequency synthesizer has been presented. The frequency synthesizer features third-order single loop architecture with completely integrated passive loop filter that does not require any additional external passive component. Two possible realizations of fully integrated clock and data recovery (CDR) circuits suitable for 60 GHz-standard compliant base band signal processing have been presented for the first time as well. The two CDRs have been optimized for either high data rate (3.456 Gb/s) or very low power consumption (5 mW) and they both work with a single 1 V supply. The frequency synthesizer is intended to generate a variable LO frequency in a fixed-IF heterodyne transceiver architecture. In such configuration the channel selection is implemented by changing the LO frequency by the required frequency step. This method avoids quadrature 50 GHz up/down-conversion thereby lowering the LO mixer design complexity and simplifying the LO distribution network. The measurement results show the PLL locking correctly on each of the four channels while consuming 60 mW from a 1 V power supply. The worst case phase noise is measured to be -80.1 dBc/Hz at 1 MHz offset from the highest frequency carrier (56.16 GHz). The output spectrum shows a reference spur attenuation of -32 dBc. The high data rate CDR features a maximum operating data rate in excess of 3.456 Gb/s while consuming 30 mW of power. The low power CDR consumes only 5 mW and operates at a maximum data rate of 1.728 Gb/s. Over a 1.5 m 60 GHz wireless link, both CDRs allow 95% reduction of the pulse shaping generated input peak-to-peak jitter from 450 ps down to 50 ps.

Inicialmente, apresentam-se características de dispositivos eletrônicos conhecidos como PLLs (phase-locked loops). PLLs são amplamente empregados para se extrair sinais de tempo em canais de comunicação e em aplicações nas quais se deseja controle automático de freqüência. O objeto principal é estudar PLLs analógicos descritos por uma equação diferencial ordinária de terceira ordem. Assim, deduzem-se condições de estabilidade assintótica e identifica-se um regime de caos conservativo, que ocorre sob certas combinações de valores de parâmetros. Três métodos de controle não-linear/caótico são então apresentados e aplicados. Os métodos são os seguintes: o Método de Pyragas via realimentação de variável de estado; o Método de Pyragas com atraso temporal na realimentação; e o Método de Sinha, o qual efetua o controle perturbando um parâmetro do sistema. Simulações numéricas são levadas a cabo a fim de ilustrar o comportamento dinâmico do sistema quando sujeito à ação desses métodos. Este trabalho termina com um estudo de uma rede formada por uma cadeia de PLLs. Condições para soluções síncronas, periódicas e caóticas (dissipativas e conservativas) são deduzidas para tal rede. / Firstly, features of electronic devices known as PLLs (Phase-Locked Loops) are presented. PLLs are widely employed to extract time signals in communication channels and in applications where automatic control of frequency is desired. The main goal is to study analog PLLs described by a third-order nonlinear ordinary differential equation. Thus, conditions for asymptotic stability are derived and a regime of conservative chaos occurring under certain combinations of parameter values is identified. Then, three methods of control of nonlinear/ chaotic dynamics are presented and applied. The methods are the following: the Pyragas method via feedback of state variable; the Pyragas method with time delay in the feedback; and the Sinhas method, which performs the control by disturbing a parameter of the system. Numerical simulations are accomplished in order to illustrate the dynamical behavior of the system when subjected to the action of these methods. This work ends with a study of a single-chain PLL network. Conditions for synchronous, periodic and chaotic (dissipative and conservative) solutions are derived for such a network.

Neste trabalho, são estudados os problemas de sincronismo de fase nas redes mestre-escravo de via única (OWMS), nas topologias Estrela Simples, Cadeia Simples e mista, através da Teoria Qualitativa de Equações Diferenciais, com ênfase no Teorema da Variedade Central. Através da Teoria das Bifurcações, analisa-se o comportamento dinâmico das malhas de sincronismo de fase (PLL) de segunda ordem que compõem cada rede, frente às variações nos seus parâmetros constitutivos. São utilizadas duas funções de excitação muito comuns na prática: o degrau e a rampa de fase, aplicadas pelo nó mestre. Em cada caso, discute-se a existência e a estabilidade do estado síncrono. A existência de pontos de equilíbrio não-hiperbólicos, não permite uma aproximação linear, e nesses casos é aplicado o Teorema da Variedade Central. Através dessa rigorosa técnica de simplificação de sistemas dinâmicos é possível fazer uma aproximação homeomórfica em torno desses pontos, preservando a orientação no espaço de fases. Desse modo, é possível determinar, localmente, suas estabilidades. / This work presents stability analysis of the syncronous state for three types of one-way master-slave time distribution network topologies: single star, single chain and both of them, mixed. Using bifurcation theory, the dynamical behavior of second-order phase-locked loops employed to extract the syncronous state in each node is analyzed in function of the constitutive parameters. Two usual inputs, the step and the ramp phase pertubations, are supposed to appear in the master node and, in each case, the existence and stability of the syncronous state are studied. For parameter combinations resulting in non hyperbolic synchronous states, the linear approximation does not provide any information, even about the local behaviour of the system. In this case, the center manifold theorem permits the construction of an equivalent vector field representing the asymptotic behaviour of the original system in the neighborhood of these points. Thus, the local stability can be determined.

Made available in DSpace on 2016-03-15T19:38:09Z (GMT). No. of bitstreams: 1 Marcos Kleber Soares Kunyosi.pdf: 2418852 bytes, checksum: ab6795f8d39445430da1eca23e865c56 (MD5) Previous issue date: 2006-09-11 / Instituto Presbiteriano Mackenzie / Recognition of patterns can be performed by using neural networks built with oscillators, like phase-locked loops (PLLs). These networks are modeled with differential equation systems and can be studied by using Dynamical System Theory, which is used in this work in order to investigate the dynamical behavior related to a synaptic configuration of a neural network. As a result of such an investigation, two methods (Brute Force and Algebric) that help to build neural networks formed by PLLs are presented. These methods aim to relate the synaptic configuration of the network to the corresponding basin of attraction of fixed points, which represent the stored patterns on the network. Also general properties of synaptic configuration are presented in order to generate other useful configurations. Then a model of an image recognition machine able to store in its memory a monochromatic image and able to determine if other image is similar to the memorized one is proposed. / Reconhecimento de padrões pode ser feito usando redes neurais construídas com osciladores, como malhas de sincronismo de fase (PLLs). Essas redes são modeladas por sistemas de equações diferenciais e podem ser estudas pela Teoria de Sistemas Dinâmicos, que é usada neste trabalho para investigar o comportamento dinâmico associado a uma configuração sináptica de uma rede neural. Como resultado dessa investigação, são apresentados dois métodos (Força Bruta e Algébrico) que auxiliam na construção de redes neurais formadas por PLLs. Esses métodos têm como objetivo relacionar a configuração sináptica da rede às respectivas bacias de atração de pontos atratores, os quais representam os padrões memorizados na rede. Também são apresentadas propriedades gerais da configuração sináptica que podem ser usadas para compor outras configurações de interesse. Por fim, é proposto um modelo de máquina reconhecedora de imagem capaz de armazenar em sua memória uma figura monocromática e determinar se uma imagem qualquer apresentada a ela é semelhante à memorizada.

A novel scheme of optimizing the individual components of a phase locked loop (PLL) which is used for stable clock generation and synchronization of signals is considered in this work. Verilog-A is used for the high level system design of the main components of the PLL, followed by the individual component wise optimization. The design of experiments (DOE) approach to optimize the analog, 45nm voltage controlled oscillator (VCO) is presented. Also a mixed signal analysis using the analog and digital Verilog behavior of components is studied. Overall a high level system design of a PLL, a systematic optimization of each of its components, and an analog and mixed signal behavioral design approach have been implemented using cadence custom IC design tools.

Integrated systems with billions of transistors on a single chip are a now reality. These systems include multi-core microprocessors and are built today using deca-nanometer devices organized into synchronous digital circuits. The movement of data within such systems is regulated by a set of predictable timing signals, called clocks, which must be distributed to a large number of sequential elements. Collectively, these clocks have a significant impact on the frequency of operation and, consequently, on the performance of the systems. The clocks are also responsible for a large fraction of the power consumed by these systems. The objective of this dissertation is to better understand clock distribution in order to identify opportunities and strategies for improvement by analyzing the conditions under which the optimal tradeoff between power and performance can be achieved, by modeling the constraints associated with local and global clocking, by evaluating the impact of noise, and by investigating promising new design strategies for future integrated systems.

With the move of the broadband cellular network towards 5G taking off and the preparatory work on 6G and beyond starting, the need for low-complexity, low-power, and high-performance frequency synthesis using Phase-Locked Loop (PLL)s increases. As we get deeper into the mm-wave frequencies and push towards frequencies in the order of 50-70 GHz design challenges with existing PLL architectures, such as limited technology scaling and limited in-band noise performance become more apparent. Other designs have tried overcoming these problems, for example by using single-bit phase detection at the cost of increased complexity when trying to control the bandwidth, or designing the loop with lower bandwidth to suppress in-band noise at the cost of requiring a lower noise and thus more power hungry oscillator. This thesis proposes a new Phase-locked loop architecture implemented in a 22nm node to combat these issues, utilizing a Pulse-Shrinking Time-To-Digital Converter (PS-TDC) offering sub-pico-second resolution with minimal power consumption in lock. The results found in this thesis have shown the viability of such a design, offering good in-band performance, allowing for wide bandwidth, and the use of a cheaper low-power Digital-Controlled Oscillator (DCO). The PS-TDC architecture combined with control logic implemented in this project can drastically decrease power consumption in lock while being able to compensate for process variations to optimize jitter performance. Additionally, by utilizing a Phase-Frequency Detector (PFD) and gear-shifting logic it has been shown that robust and fast locking can be achieved. / Med övergången till 5G i mobila bredbandsnätverk och förberedelserna för 6G på gång ökar behovet av lågkomplexa, lågeffekts- och högpresterande frekvenssyntes. När vi beger oss djupare in i millimetervågsfrekvenserna och strävar efter frekvenser uppemot 50-70 GHz blir designutmaningar med befintliga faslåsta loopar, såsom begränsad teknologiskalning och dålig prestanda för inband-brus, alltmer tydliga. Andra designer har försökt att övervinna dessa problem genom att till exempel använda enbitars fasdetektion till priset av ökad komplexitet vid styrning av systemets bandbredd, eller genom att designa loopen med lägre bandbredd för att vidare dämpa inband-brus, vilket kommer till priset av en oscillator med lägre brus och därmed högre effektförbrukning. Denna avhandling föreslår en ny arkitektur för faslåsta loopar för att överkomma dessa problem genom att använda en pulskrympande tids-till-digital omvandlare som erbjuder sub-pikosekunds upplösning med minimal effektförbrukning när frekvensen är låst. Resultaten som presenteras i denna avhandling har visat att en sådan design är möjlig, med god in-band prestanda, möjlighet till hög bandbredd och därmed användning av en billigare lågeffekt DCO. Den pulsskalande TDC-arkitekturen i kombination med kontrolllogik implementerad i detta projekt kan dramatiskt minska effektförbrukningen när frekvensen är låst, samtidigt som den kan kompensera för processvariationer för att optimera jitterprestanda. Sist har det visats att en robust och snabb låsning av frekvensen kan uppnås genom att använda en PFD.

Le projet HODISS dans le cadre duquel s'effectue nos travaux adresse la problématique de la synchronisation globale des systèmes complexes sur puce (System-on-Chip ou SOCs, par exemple un multiprocesseur monolithique). Les approches classiques de distribution d'horloges étant devenues de plus en plus obsolètes à cause de l'augmentation de la fréquence d'horloge, l'accroissement des temps de propagation, l'accroissement de la complexité des circuits et les incertitudes de fabrication, les concepteurs s’intéressent (pour contourner ces difficultés) à d'autres techniques basées entre autres sur les oscillateurs distribués. La difficulté majeure de cette dernière approche réside dans la capacité d’assurer le synchronisme global du système. Nous proposons un système d'horlogerie distribuée basé sur un réseau d’oscillateurs couplés en phase. Pour synchroniser ces oscillateurs, chacun d'eux est en fait une boucle à verrouillage de phase qui permet ainsi d'assurer un couplage en phase avec les oscillateurs des zones voisines. Nous analysons la stabilité de l'état synchrone dans des réseaux cartésiens identiques de boucles à verrouillage de phase entièrement numériques (ADPLLs). Sous certaines conditions, on montre que l'ensemble du réseau peut synchroniser à la fois en phase et en fréquence. Un aspect majeur de cette étude réside dans le fait que, en l'absence d'une horloge de référence absolue, le filtre de boucle dans chaque ADPLL est piloté par les fronts montants irréguliers de l'oscillateur local et, par conséquent, n'est pas régi par les mêmes équations d'état selon que l'horloge locale est avancée ou retardée par rapport au signal considéré comme référence. Sous des hypothèses simples, ces réseaux d'ADPLLs dits "auto-échantillonnés" peuvent être décrits comme des systèmes linéaires par morceaux dont la stabilité est notoirement difficile à établir. L'une des principales contributions que nous présentons est la définition de règles de conception simples qui doivent être satisfaites sur les coefficients de chaque filtre de boucle afin d'obtenir une synchronisation dans un réseau cartésien de taille quelconque. Les simulations transitoires indiquent que cette condition nécessaire de synchronisation peut également être suffisante pour une classe particulière d'ADPLLs "auto-échantillonnés". / The HODISS project, context in which this work is achieved, addresses the problem of global synchronization of complex systems-on-chip (SOCs, such as a monolithic multiprocessor). Since the traditional approaches of clock distribution are less used due to the increase of the clock frequency, increased delay, increased circuit complexity and uncertainties of manufacture, designers are interested (to circumvent these difficulties) to other techniques based among others on distributed synchronous clocks. The main difficulty of this latter approach is the ability to ensure the overall system synchronization. We propose a clock distribution system based on a network of phase-coupled oscillators. To synchronize these oscillators, each is in fact a phase-locked loop which allows to ensure a phase coupling with the nearest neighboring oscillators. We analyze the stability of the synchronized state in Cartesian networks of identical all-digital phase-locked loops (ADPLLs). Under certain conditions, we show that the entire network may synchronize both in phase and frequency. A key aspect of this study lies in the fact that, in the absence of an absolute reference clock, the loop-filter in each ADPLL is operated on the irregular rising edges of the local oscillator and consequently, does not use the same operands depending on whether the local clock is leading or lagging with respect to the signal considered as reference. Under simple assumptions, these networks of so-called “self-sampled” all-digital phase-locked-loops (SS-ADPLLs) can be described as piecewise-linear systems, the stability of which is notoriously difficult to establish. One of the main contributions presented here is the definition of simple design rules that must be satisfied by the coefficients of each loop-filter in order to achieve synchronization in a Cartesian network of arbitrary size. Transient simulations indicate that this necessary synchronization condition may also be sufficient for a specific class of SS-ADPLLs.

Ultra narrow-band filters and the use of two loops in a cascade configuration dominate current clock conditioners based on phase-locked-loop (PLL) schemes. Since a PLL exhibits a low-pass transfer function with respect to the reference clock, the noise performance at very close-to-carrier offset frequencies is still determined by the input signal. Although better cleaning can be achieved with extremely narrow loops, an ultra low cut-off frequency could not be selected since the stability of the configuration deteriorates as the filter bandwidth is reduced. This fact suggests that a full-spectrum clock conditioning is not possible using traditional PLL architectures, and an alternative scheme is necessary to attenuate the very-close-to-carrier phase noise (PN). In addition, ultra-narrow loop filters can compromise on-chip integration because of the large size capacitors needed when chosen as passive. Input signal attenuation with relaxed bandwidth requirements becomes the main aspect that a comprehensive clock cleaner must address to effectively regenerate a reference signal. This dissertation describes the Band-Reject Nested-PLL (BRN-PLL) scheme, a modified PLL-based architecture that provides an effective signal cleaning procedure by introducing a notch in the input transfer function through inner and outer loops and a high-pass filter (HPF). This modified response attenuates the reference-signal PN and reduces the size of the loop-filter capacitors substantially. Ultra narrow loops are no longer required because the notch size is related to the system bandwidth. The associated transfer function for the constitutive blocks (phase detectors and local oscillators) show that the output close-to-carrier and far-from-carrier PN sections are mainly dominated by the noise from the inner-PLL phase detector (PD) and local oscillator (LO) located in the outer loop, respectively. The inner-PLL PD transfer function maintains a low-pass characteristic with a passband gain inversely proportional to the PD gain becoming the main contribution around the carrier signal. On the other hand, the PN around the transition frequency is determined mainly by the reference and the inner-PLL LO. Their noise contributions to the output will depend on the associated passband local maxima, which is located at the BRN-PLL transition frequency. Hence, in this region, the inner-PLL LO is selected so that its effect can be held below that of the outer-PLL PD. The BRN-PLL can use a high-Q MEMS-based VCO to further improve the transition region of the output PN profile and an LC-VCO as outer-PLL LO to reduce the noise floor of the output signal. In particular, two tuning mechanisms are explored for the MEMS-VCO: series tuning using varactors and phase shifting of a resonator operating in nonlinear regime. Both schemes are implemented to generate a tunable oscillator with no PN-performance degradation.

La thèse a pour but de développer des algorithmes robustes de poursuite de phase multifréquence en environnement dégradé. L’objectif est d’élaborer de nouvelles structures pouvant opérer à des niveaux de rapport signal à bruit inférieurs aux limites des algorithmes actuellement implémentés dans des récepteurs grand public. Les problèmes de robustesse des algorithmes d’estimation de phase étant en grande partie causés par le phénomène de sauts de cycle, les différents axes de recherche se sont focalisés sur des nouvelles approches de développement de phase au sein des structures de poursuite. Pour ce faire, deux approches ont été étudiées et testées. Dans un premier temps, deux structures de poursuite monofréquence basées sur une DPLL conventionnelle ont été développées. Ces structures disposent d’un système externe de développement de phase visant à prédire et pré-compenser la sortie du discriminateur grâce à l’analyse des sorties du discriminateur ou des sorties du filtre de boucle. La réduction de la dynamique à estimer va alors permettre de réduire l’apparition des sauts de cycle se produisant au niveau du discriminateur. Par la suite, ce système de développement de phase a été adapté à la poursuite de phase multifréquence. Grâce à l’exploitation de la diversité en fréquence offerte par les signaux de navigation (i.e., de la proportionnalité des fréquences Doppler), il a été possible de mettre en place une étape de fusion de données qui a permis d’améliorer la précision de la prédiction de la sortie du discriminateur et donc d’améliorer la robustesse de la structure. Dans un second temps, les travaux de recherche se son taxés sur une nouvelle approche de poursuite de phase et de correction du phénomène de sauts de cycle basée sur une technique de filtrage Bayésien variationnel. Toujours en exploitant la diversité en fréquence des signaux de navigation, cette méthode suppose un modèle de dynamique de phase Markovien qui va imposer une certaine continuité de l’estimation et va permettre de fournir une estimation de phase développée. / This thesis aims at introducing multifrequency phase tracking algorithms operating in low C/N0environment. The objective is to develop new structures whose tracking limits are lower than thatof current algorithms used in mass market receivers. Phase tracking suffers from a lack of robustnessdue to the cycle slip phenomenon. Works have thus been focused on elaborating new phaseunwrapping systems. To do so, two different tracking approaches were studied. First, we have developed new monofrequency tracking loops based on a conventional DPLL. These structures aimat predicting the discriminator output by analyzing, thanks to a polynomial model, the last outputsamples of either the discriminator or the loop filter. Once the discriminator output is predicted,the estimated value is pre-compensated so that the phase dynamics to be tracked is reduced aswell as the cycle slip rate. Then, the unwrapping structure analyzing the loop filter outputs hasbeen extended to multifrequency signals. Using a data fusion step, the new multifrequency structuretakes advantage of the frequency diversity of a GNSS signal (i.e., proportionality of Dopplerfrequencies) to improve the tracking performances. Secondly, studies have been focused on developing a new multifrequency tracking algorithm using variational Bayesian filtering technique.This tracking method, which also uses the GNSS frequency diversity, assumes a Markovian phasedynamics that enforces the smoothness of the phase estimation and unwraps it.