L'efficacité énergétique est devenue une métrique clé de la performance des systèmes sur puce numériques, en particulier pour les applications tirant leur énergie de batteries ou de l'environnement. La miniaturisation technologique n'est plus suffisante pour atteindre les niveaux de consommation requis. Ce travail de recherche propose ainsi de nouvelles conceptions de circuits pour la génération d'horloge flexible, la mesure de puissance et de température ainsi que l'intégration de ces blocs au sein de systèmes sur puce complets.Le multiplieur de fréquence innovant en boucle ouverte proposé permet l'adaptation rapide de la fréquence générée (53MHz 0.5V - 889MHz 0.9 V). Sa surface réduite (981µm2) et faible consommation (0.45pJ/cycle à 0.5 V) facilitent son intégration dans des systèmes à basse consommation. Le capteur de puissance instrumente un convertisseur de tension switched-capacitor; validé sur deux architectures différentes, il permet une mesure de la puissance d'entrée et de sortie avec une précision de 2.5% à 6%. Enfin, un nouveau principe de capteur de température est proposé. Il exploite une méthode de calibration par body-biasing sur caisson n et un système numérique intégré pour la compensation de non-linéarité. Enfin, cette thèse illustre la manière dont ces circuits peuvent être intégrés pour assurer la gestion de consommation de systèmes complexes. Un travail de modélisation du body-biasing est proposé, illustrant sa complémentarité avec la gestion de tension d'alimentation. Puis trois exemples de stratégies de gestion de la consommation sont proposées au sein de systèmes complets. / Energy efficiency has become a key metric for digital SoC, especially for applications relying on batteries or energy harvesting. Hence, this work proposes new designs for on-chip flexible clock generator, power monitor and temperature sensor as well as the integration of those blocks within complete SoC.The novel open-loop clock multiplier architecture enables fast frequency scaling and is implemented to operate on the same voltage-frequency range as a digital core ((53MHz 0.5V - 889MHz 0.9 V). The achieved extremely low area (981µm2) and power consumption 0.45pJ/cycle 0.5 V) also ease its integration within low power SoC. The proposed power monitor instruments switched capacitor DC-DC converters, which are standard components of low voltage SoCs. The monitor has been demonstrated over two different converters topologies and provides a measurement of both the converter input and output power within 2.5% to 6% accuracy. Last, a new principle of temperature sensor is proposed. It leverages single n well body-biasing for calibration and integrated digital logic for large non-linearity correction. It is expected to achieve within 1C accuracy 0.1nJ / sample and 225 µm2 probe area. Then, this work illustrates how those circuits can be integrated within complex SoCs power management strategies. First, a modeling study of body biasing highlights the benefits it can provide in complement to voltage scaling, accounting for a wide temperature range. Last, three example of power management are proposed at SoC level.

The number of electrical vehicles in Sweden are increasing faster for every year and the demand of charging them at home is growing as well. This requires high delivery reliability and a stable low-voltage distribution grid. In this master thesis three different low-voltage networks are modelled and simulated together with load which corresponds home charging of electrical vehicles (EV) to analyse if the grid is able to handle these kinds of stresses. Information of the different grids were gathered from Falu Energi & Vatten and modelled in Matlab together with EV charging loads generated in a separate program. The electricity consumption data used in the simulations were measured at the transformer in each grid. A regression analysis of the consumption data were preformed to calculate values which corresponds to a worst case scenario. The results show that the low-voltage distribution grid in Falun is well dimensioned and can handle these possible future loads even in the worst constructed scenario.

Este trabalho propõe novas topologias de circuitos e técnicas de projeto para filtros ativos e amplificadores de ganho programável (PGA) com operação em ultra baixa tensão (ULV) e ultra-baixa potência (ULP). Os receptores de RF do tipo Bluetooth de baixa energia (BLE), utilizados nos circuitos de internet das coisas (IoT), são as aplicações alvo dos circuitos propostos neste trabalho. Na faixa de ULV são utilizados filtros do tipo RC-ativo, uma vez que possuem uma maior linearidade em relação aos filtros do tipo gmC. A operação em ULP é alcançada neste trabalho utilizando uma nova topologia de amplificador operacional de transcondutância (OTA), com único estágio, que apresenta uma alta eficiência e reduzida sensibilidade às variações de processo, tensão e temperatura (PVT). O baixo ganho de tensão do amplificador de estágio único e os efeitos das cargas resistivas de realimentação são compensados usando um transcondutor negativo, robusto a variações em PVT, conectado às entradas do OTA. A faixa dinâmica dos circuitos é elevada usando topologias totalmente diferenciais e as taxas de rejeição de modo comum e de fonte de alimentação são melhoradas utilizando circuitos de realimentação de modo-comum. Para possibilitar a operação na faixa de ULV todos os circuitos usam apenas dois transistores empilhados e o nível de inversão do canal é elevado através da polarização direta do substrato. Neste trabalho são propostas também uma ferramenta de análise do ponto de operação do transistor, baseando-se na simulação elétrica, e algumas metodologias de projetos para circuitos operando em ULV. Os circuitos e metodologias desenvolvidos foram utilizados para o projeto de um filtro passa-faixa complexo RC-ativo de terceira ordem, um amplificador de ganho programável e um filtro biquadrático do tipo Tow-Thomas com ganho programável, compatíveis com receptores de RF do padrão BLE. Para a implementação do PGA, uma nova topologia de transconductor negativo programável foi desenvolvida para permitir a compensação ótima do amplificador operacional em todos os modos de ganho. Todos os circuitos foram projetados para operar com uma tensão de alimentação de 0,4 V e foram prototipados em processos de fabricação CMOS e BiCMOS de 180 nm e 130 nm, respectivamente. Os resultados experimentais e de simulação pós-layout demonstram uma operação adequada em 0,4 V, uma ultra-baixa dissipação de potência, atingindo o mínimo de 10.9 ?W/polo, e a melhor figura-de-mérito (FoM) em relação aos outros filtros ativos e amplificadores disponíveis na literatura. / This thesis proposes novel circuit topologies and design techniques of ultra-low voltage (ULV) and ultra-low power (ULP) active-filters and programmable gain amplifiers (PGA) suitable for the Bluetooth low energy (BLE) RF receivers used in the Internet of Things (IoT) applications. The active-RC filters are preferred to the gm-C topologies at the ULV operation due to its improved linearity. However, the closed-loop operation increases the operational amplifier required voltage gain and its capacity to drive the resistive feedback load. In this work, the ULP dissipation is obtained by proposing a very efficient single-stage inverter-based operational transconductance amplifier (OTA) and a proper forward bulk biasing to reduce the sensitivity to process, voltage and temperature (PVT) variations. The low voltage gain and the resistive load effects on the single-stage OTA are completely compensated by using a PVT robust negative transconductor connected at the OTA inputs. The dynamic range is increased by using fully-differential topologies and common-mode feedback to improve the common-mode and power supply rejection rates. The operation at the ULV range is reached by using only two-stacked transistors in all the circuit implementations and bulk forward bias in some transistors to reduce the threshold voltage and to increase the channel inversion level. An operation point simulation-based tool and some design methodologies are also proposed in this work to design the ULV circuits. The proposed circuits were used to design a third-order active-RC complex band-pass filter (CxBPF), a programmable gain amplifier (PGA) and a Tow-Thomas biquad, with integrated programmable gain capability, suitable for BLE RF receivers. The PGA implementation uses a new programmable input negative transconductor to obtain the optimal closed-loop amplifier compensation in all the gain modes. The circuits were designed to operate at the power supply voltage of 0.4 V and are prototyped in 180 nm and 130 nm low-cost CMOS and BiCMOS process, respectively. The experimental and post-layout simulation results have demonstrated the proper ULV operation at 0.4 V, the ultra-low power dissipation down to 10.9 ?W/pole and the best figure-of-merit (FoM) among the state-of-the-art active-filters and amplifiers from the literature.

Este trabalho está dividido em duas partes distintas que constituem contribuições inéditas ao estudo da estabilidade em sistemas elétricos de potência. A primeira parte do trabalho é a mais importante e trata do problema da identificação das soluções de baixa tensão críticas do fluxo de carga. Esta parte do trabalho se presta a análise de estabilidade de tensão a pequenas perturbações. Os últimos capítulos deste trabalho apresentam também uma proposta de função energia estendida que modela as cargas dependentes da tensão segundo o modelo ZIP de carga, considerando a estrutura da rede preservada. Assim, a função energia proposta pode ser utilizada para analisar tanto a estabilidade de tensão como a estabilidade de ângulo em sistemas de potência. Esta proposta também é inédita na literatura. Embora a função energia proposta tenha sido aplicada apenas a sistemas de dimensão reduzidas, os resultados apresentados neste trabalho nos levam a acreditar que essa mesma função energia pode ser utilizada na análise de estabilidade de sistemas de potência de grandes dimensões. Já o método proposto para identificação das soluções de baixa tensão das equações de fluxo de carga se utiliza de um sistema dinâmico auxiliar das equações de fluxo de carga. O sistema dinâmico auxiliar utilizado não tem significado físico, mas pode ser escolhido de tal forma que a solução usual das equações de fluxo de carga seja um ponto de equilíbrio estável do sistema dinâmico auxiliar, eque as soluções de baixa tensão do fluxo de carga sejam pontos de equilíbrio instáveis do sistema dinâmico auxiliar. Dessa forma, é possível calcular as soluções de baixa tensão do fluxo de carga, calculando-se os pontos de equilíbrio instáveis do sistema dinâmico auxiliar. Assim, é possível utilizar partes da teoria de sistemas dinâmicos para estudar as soluções das equações de fluxo de carga. Baseado nestes princípios, foi desenvolvido um programa para calcular trajetórias do sistema dinâmico auxiliar, que se iniciam e se mantêm nas vizinhanças da fronteira da área de atração do ponto de equilíbrio estável do SEP. Dessa forma é possível afirmar que a trajetória calculada tende a convergir para a solução crítica das equações de fluxo de carga. O programa foi inicialmente concebido para calcular as soluções de baixa tensão de sistemas elétricos sem perdas. Em seguida o programa desenvolvido foi adaptado para calcular as soluções de baixa tensão de sistemas de potência completos, incluindo também as resistências das linhas de transmissão. Esta última versão do programa foi testada para os sistemas IEEE 39 e IEEE 118 barras, e os resultados obtidos se mostraram bastante satisfatórios. Assim, o método proposto é uma ferramenta original e eficaz para a solução do problema de calcular a solução crítica das equações de fluxo de carga de sistemas elétricos de potência. / This work may be divided into two distinct parts. Both of them are new contributions to stability analysis of power systems. In the first part it is proposed a new method to calculate the critical load flow low voltage solutions, and it is the main part of this work. Meanwhile, the last two chapters of this work presents a proposed extended energy function that consider the common load ZIP models. It allows the analysis of angle and voltage stability for power systems subjected to large disturbances. This work proposes a method to calculate the low voltage solutions (LVS) of the load flow equations of an electrical power system. The proposed method identifies the LVS involved in the saddle-node bifurcation leading the power system to a voltage collapse. This solution is known as the critical low voltage solution. In order to perform the proposed calculation, an auxiliary dynamical gradient system is used. It is shown that the equilibrium points of that associated auxiliary dynamical gradient system are the solutions of the load flow equations. In such manner, the paper proposes identifying the critical LVS calculating the equilibrium points of an auxiliary dynamical gradient system. The proposed method was tested on the Stagg 5-bus, on the IEEE 39-bus and on IEEE 118-bus test systems, and the results are presented at the end of the text.

Os métodos convencionais para o controle de tensão concentram-se na média tensão. Em alguns casos não são suficientes para a correção da tensão na rede secundária. Este trabalho apresenta os problemas relacionados à regulação de tensão na baixa tensão, os métodos convencionais para correção da tensão e uma estratégia para o controle de tensão na rede secundária de sistema de distribuição de energia elétrica. A solução final proposta é um conjunto de transformador com taps no lado de baixa tensão, hardware e software que promovem a comutação das derivações do transformador de forma automática. Para o desenvolvimento dessa estratégia será abordada a aplicação de sistemas inteligentes, o sistema fuzzy, e a estimação de modelos elétricos dos transformadores de distribuição. O objetivo desse produto é ser uma solução prática, viável técnica e economicamente para a regulação da tensão em cenários onde os métodos convencionais não o são. Os protótipos dessa solução foram montados e testados em laboratório e em campo e os resultados atenderam ao objetivo proposto. / The conventional methods for voltage control concentrated in medium voltage. In some case, they are not enough to correct the voltage on secondary grid of distribuition. This paper presents a strategy to control the voltage on the low voltage of the distribution grid. As proposed for dealing of this problem is made the presentation of an architecture for the intelligent automatic control, that is composed of distribuition transformer with tap on the low side, hardware and software. For the development of this strategy will be approached the application the intelligent systems, Fuzzy Systems, and the estimation of electrical model of distribuition transformers. The goal with this design is to provide grants to set up a system for regulating the voltage on the low side which is technically and economically feasible to be deployed where conventional solutions, with the inclusion of line regulators, are not.

Networks with hundreds of ad hoc nodes equipped with communication and position finding abilities are conceivable with recent advancements in technology. Methods are presented in this thesis to assess the communicative capabilities and node position estimation of mobile ad hoc networks. Specifically, we investigate techniques for providing communication and geolocation with specific characteristics in wireless ad hoc networks. The material presented in this thesis, communication and geolocation, may initially seem a collection of disconnected topics related only distantly under the banner of ad hoc networks. However, systems currently in development combining these techniques into single integrated systems. In this thesis first, we investigate the effect of multilayer interaction, including fading and path loss, on ad hoc routing protocol performance, and present a procedure for deploying an ad hoc network based on extensive simulations. Our first goal is to test the routing protocols with parameters that can be used to characterize the environment in which they might be deployed. Second, we analyze the location discovery problem in ad hoc networks and propose a fully distributed, infrastructure-free positioning algorithm that does not rely on the Global Positioning System (GPS). The algorithm uses the approximate distances between the nodes to build a relative coordinate system in which the node positions are computed in three-dimensions. However, in reconstructing three-dimensional positions from approximate distances, we need to consider error threshold, graph connectivity, and graph rigidity. We also statistically evaluate the location discovery procedure with respect to a number of parameters, such as error propagation and the relative positions of the nodes.

The increasing awareness on the effect of carbon emissions in our planet has led to several countries to adopt targets for their reduction. One way of contributing to this aim is to use and distribute electricity more efficiently. In this context, Conservation Voltage Reduction (CVR), a well-known technique that takes advantage of the positive correlation between voltage and demand to reduce energy consumption, is gaining renewed interest. This technique saves energy by only reducing customer voltages, without relying on customer actions and, therefore, can be controlled by the Distribution Network Operator (DNO). CVR not only brings benefits to the electricity system by reducing generation requirements (fewer fossil fuel burning and carbon emissions), but also to customers, as energy bill reductions. The extent to which CVR can bring benefits mainly depends on the customers load composition and their voltages. While the former dictates the voltage-demand correlation, the latter constraints the voltage reduction that can be applied without violating statutory limits. Although CVR has been studied for many years, most of the studies neglect the time-varying voltage-demand characteristic of loads and/or do not assess end customer voltages. While these simplifications could be used to estimate CVR benefits for fixed and limited voltage reductions, realistic load and network models are needed to assess the performance of active CVR schemes, where voltages are actively managed to be close to the minimum limit. Moreover, distribution networks have been traditionally designed with limited monitoring and controllability. Therefore, CVR has been typically implemented by adopting conservative voltage reductions from primary substations, for both American and European-style networks. However, as new infrastructure is deployed in European-style LV networks (focus of this work), such as monitoring and on-load tap changers (OLTCs), the opportunity arises to actively manage voltages closer to end customer (unlocking further energy savings). Although these technologies have shown to effectively control voltages in LV networks, their potential for CVR has not been assessed before. Additionally, most CVR studies were performed in a context where distributed generation (DG) was not common. However, this has changed in many countries, with residential photovoltaic (PV) systems becoming popular. As this is likely to continue, the interactions of residential PV and CVR need to be studied. This thesis contributes to address the aforementioned literature gaps by: (i) proposing a simulation framework to characterise the time-varying voltage-demand correlation of individual end customers; (ii) developing a process to model real distribution networks (MV and LV) from DNO data; (iii) adopting a Monte Carlo-based quantification process to cater for the uncertainties related to individual customer demand; (iv) assessing the CVR benefits that can be unlocked with new LV infrastructure and different PV conditions. To accomplish (iv), first, a simple yet effective rule-based scheme is proposed to actively control voltages in OLTC-enabled LV networks without PV and using limited monitoring. It is demonstrated that by controlling voltages closer to customers, annual energy savings can increase significantly, compared to primary substation voltage reductions. Also, to understand the effect of PV on CVR, a centralized, three-phase AC OPF-based CVR scheme is proposed. This control, using monitoring, OLTCs and capacitors across MV and LV networks, actively manages voltages to minimize energy consumption in high PV penetration scenarios whilst considering MV-LV constraints. Results demonstrate that without CVR, PV systems lead to higher energy imports for customers without PV, due to higher voltages. Conversely, the OPF-based CVR scheme can effectively manage voltages throughout the day, minimising energy imports for all customers. Moreover, if OLTCs at secondary substations are available (and managed in coordination with the primary substation OLTC), these tend to regulate customer voltages close to the minimum statutory limit (lower tap positions), while the primary OLTC delivers higher voltages to the MV network to also reduce MV energy losses.

Continuous-time (CT) Delta-Sigma Modulators (DSMs) have re-gained popularity recently for oversampling analog-to-digital conversion, because they are more suitable for low supply voltage implementation than their discrete-time (DT) counterparts, among other reasons. To the state of art at the low voltage front, a CT O.5-V audio-band DSM with a return-to-open feedback digital-to-analog converter has been reported. However, the O.5-V CT DSM has a limited performance of 74-dB SNDR due to clock jitters and other factors caused by the ultralow supply. / Finally, a O.5-V 2-1 cascaded CT DSM with SCR feedback is proposed. A new synthesis method is presented. Transistor-level simulations show that a 98dB SNDR is achieved over a 25-kHz signal bandwidth with a 6.4MHz sampling frequency and 350muW power consumption under a 0.5-V supply. / In this thesis, three novel ULV audio-band CT DSMs with high signal-to-noise-plus-distortion ratio (SNDR) are reported for a nominal supply of O.5V. The first one firstly realizes a switched-capacitor-resistor (SCR) feedback at O.5V, enabled by a fast amplifier at O.5V, for reduced clock jitter-sensitivity. Fabricated in a O.13mum CMOS process using only standard VT devices, the 3rd order modulator with distributed feedback occupies an active area of O.8mm2 . It achieves a measured SNDR of 81.2dB over a 25-kHz signal bandwidth while consuming 625muW at O.5-V. The measured modulator performance is consistent across a supply voltage range from O.5V to O.8V and a temperature range from -20°C to 90°C. Measurement results and thermal-noise calculation show that the peak SNDR is limited by thermal noise. / The scaling of the feature sizes of CMOS technologies results in a continuous reduction of supply voltage (VDD) to maintain reliability and to reduce the power dissipation per unit area for increasingly denser digital integrated circuits. The VDD for low-power digital circuits is predicted to drop to O.5V in about ten years. Ultra-low voltage (ULV) operation will also be required for the analog-to-digital converter, a universal functional block in mixed-signal integrated circuits, in situations where the benefits of using a single VDD out-weigh the overhead associated with multi-V DD solutions. / The second ULV CT DSM employs a feed-forward loop topology with SCR feedback. Designed in O.13mum CMOS process, the modulator achieves a post-layout simulation (thermal noise included) result of 89dB SNDR over a 25-kHz signal bandwidth. The 0.13mum CMOS chip consumes an active area of O.85mm2 and 682.5muW at O.5-V supply. It achieves an excellent measured performance of 87.8dB SNDR over a 25-kHz signal bandwidth and al02dB spurious-free dynamic range. To the best of our knowledge, this performance is the highest for DSMs in this supply voltage range. Thanks to the proposed adaptive biasing technique, the measured modulator performance is consistent across a supply voltage range from O.4V to O.75V and a temperature range from -20°C to 90°C. / Chen, Yan. / Adviser: Kong Pang Pun. / Source: Dissertation Abstracts International, Volume: 73-04, Section: B, page: . / Thesis (Ph.D.)--Chinese University of Hong Kong, 2011. / Includes bibliographical references (leaves 127-135). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [201-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstract also in Chinese.

Yeung Wing-ki. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2003. / Includes bibliographical references (leaves 64-65). / Abstracts in English and Chinese. / Abstracts --- p.i / 摘要 --- p.iii / Acknowledgements --- p.iv / Contents --- p.v / List of Figures --- p.vii / Chapter 1. --- Introduction --- p.1 / Chapter 1.1. --- Low ower Design --- p.1 / Chapter 1.2. --- ower Consumtion in Conventional CMOS Logic --- p.2 / Chapter 1.3. --- Adiabatic Switching --- p.7 / Chapter 1.3.1. --- Varying Suly Voltage --- p.7 / Chapter 1.3.2. --- Charge Recovery --- p.12 / Chapter 2. --- Adiabatic Quasi-static CMOS Logic --- p.13 / Chapter 2.1. --- AqsCMOS Logic Building Block --- p.14 / Chapter 2.2. --- AqsCMOS inverter --- p.17 / Chapter 2.3. --- ower Reduced in Sinusoidal Suly --- p.18 / Chapter 2.4. --- Clocking Scheme --- p.21 / Chapter 3. --- Contactless Smart Card --- p.23 / Chapter 3.1. --- Architecture --- p.23 / Chapter 3.2. --- Standardization --- p.26 / Chapter 3.3. --- Universal Asynchronous Receiver and Transmitter (UART) --- p.30 / Chapter 4. --- Clock Recovery --- p.35 / Chapter 4.1 --- Adiabatic Ring Oscillator --- p.35 / Chapter 4.2. --- Secial Frequencies of AqsCMOS Ring Oscillator --- p.39 / Chapter 4.3. --- ower Extraction --- p.41 / Chapter 5. --- Evaluations and Measurement Results --- p.43 / Chapter 5.1. --- Outut Transitions --- p.43 / Chapter 5.2. --- Ring Oscillator --- p.44 / Chapter 5.3. --- Synchronization --- p.47 / Chapter 5.4. --- ower Consumtion --- p.49 / Chapter 6. --- Conclusion --- p.53 / Aendix --- p.54 / Glossary --- p.62 / Reference --- p.64

Wireless sensor networks are becoming important in several monitoring and sensing applications. Ultra low power consumption in the sensor nodes is important for extending the battery life of the nodes. In this dissertation, two low power BFSK receiver architectures are proposed and verified with prototype implementations in silicion. A 2.4 GHz 1 Mb/s polyphase filter (PPF) BFSK receiver demonstrates ±180 ppm frequency offset tolerance (FOT) and 40 dB adjacent channel rejection (ACR) at a modulation index (MI) of 2, with a power consumption of 1.9 mW. High FOT at low MI is achieved by a frequency-to-energy conversion architecture using PPFs without any frequency correction. The proposed hybrid topology of the PPF provides an improved ACR at reduced power. To further improve the energy efficiency, a low energy 900 MHz mixer-less BFSK receiver is designed. High gain frequency-to-amplitude conversion and better sensitivity is achieved by a linear amplifier with Q-enhanced LC tank, eliminating the need for local oscillators and mixers. With a power consumption of 500 μW, the receiver achieves sensitivities of -90 dBm and -76 dBm for data rates of 0.5 Mb/s and 6 Mb/s, respectively. The energy efficiency is 80 pJ/b when operating at 6 Mb/s. / Graduation date: 2013 / Access restricted to the OSU Community at author's request from March 25, 2013 - March 25, 2014