As IC technologies scale to the nanometer regime, efficient and accurate modeling and analysis of VLSI systems with billions of transistors and interconnects becomes increasingly critical and difficult. VLSI systems impacted by the increasingly high dimensional process-voltage-temperature (PVT) variations demand much more modeling and analysis efforts than ever before, while the analysis of large scale on-chip interconnects that requires solving tens of millions of unknowns imposes great challenges in computer aided design areas. This dissertation presents new methodologies for addressing the above two important challenging issues for large scale on-chip interconnect modeling and analysis: In the past, the standard statistical circuit modeling techniques usually employ principal component analysis (PCA) and its variants to reduce the parameter dimensionality. Although widely adopted, these techniques can be very limited since parameter dimension reduction is achieved by merely considering the statistical distributions of the controlling parameters but neglecting the important correspondence between these parameters and the circuit performances (responses) under modeling. This dissertation presents a variety of performance-oriented parameter dimension reduction methods that can lead to more than one order of magnitude parameter reduction for a variety of VLSI circuit modeling and analysis problems. The sheer size of present day power/ground distribution networks makes their analysis and verification tasks extremely runtime and memory inefficient, and at the same time, limits the extent to which these networks can be optimized. Given today?s commodity graphics processing units (GPUs) that can deliver more than 500 GFlops (Flops: floating point operations per second). computing power and 100GB/s memory bandwidth, which are more than 10X greater than offered by modern day general-purpose quad-core microprocessors, it is very desirable to convert the impressive GPU computing power to usable design automation tools for VLSI verification. In this dissertation, for the first time, we show how to exploit recent massively parallel single-instruction multiple-thread (SIMT) based graphics processing unit (GPU) platforms to tackle power grid analysis with very promising performance. Our GPU based network analyzer is capable of solving tens of millions of power grid nodes in just a few seconds. Additionally, with the above GPU based simulation framework, more challenging three-dimensional full-chip thermal analysis can be solved in a much more efficient way than ever before.

Vertical stacking—based on modern manufacturing and integration technologies—of multiple 2D chips enables three-dimensional integrated circuits (3D ICs). This exploitation of the third dimension is generally accepted for aiming at higher packing densities, heterogeneous integration, shorter interconnects, reduced power consumption, increased data bandwidth, and realizing highly-parallel systems in one device. However, the commercial acceptance of 3D ICs is currently behind its expectations, mainly due to challenges regarding manufacturing and integration technologies as well as design automation. This work addresses three selected, practically relevant design challenges: (i) increasing the constrained reusability of proven, reliable 2D intellectual property blocks, (ii) planning different types of (comparatively large) through-silicon vias with focus on their impact on design quality, as well as (iii) structural planning of massively-parallel, 3D-IC-specific interconnect structures during 3D floorplanning. A key concept of this work is to account for interconnect structures and their properties during early design phases in order to support effective and high-quality 3D-IC-design flows. To tackle the above listed challenges, modular design-flow extensions and methodologies have been developed. Experimental investigations reveal the effectiveness and efficiency of the proposed techniques, and provide findings on 3D integration with particular focus on interconnect structures. We suggest consideration of these findings when formulating guidelines for successful 3D-IC design automation. / Dreidimensional integrierte Schaltkreise (3D-ICs) beruhen auf neuartigen Herstellungs- und Integrationstechnologien, wobei vor allem “klassische” 2D-ICs vertikal zu einem neuartigen 3D-System gestapelt werden. Dieser Ansatz zur Erschließung der dritten Dimension im Schaltkreisentwurf ist nach Expertenmeinung dazu geeignet, höhere Integrationsdichten zu erreichen, heterogene Integration zu realisieren, kürzere Verdrahtungswege zu ermöglichen, Leistungsaufnahmen zu reduzieren, Datenübertragungsraten zu erhöhen, sowie hoch-parallele Systeme in einer Baugruppe umzusetzen. Aufgrund von technologischen und entwurfsmethodischen Schwierigkeiten bleibt jedoch bisher die kommerzielle Anwendung von 3D-ICs deutlich hinter den Erwartungen zurück. In dieser Arbeit werden drei ausgewählte, praktisch relevante Problemstellungen der Entwurfsautomatisierung von 3D-ICs bearbeitet: (i) die Verbesserung der (eingeschränkten) Wiederverwendbarkeit von zuverlässigen 2D-Intellectual-Property-Blöcken, (ii) die komplexe Planung von verschiedenartigen, verhältnismäßig großen Through-Silicion Vias unter Beachtung ihres Einflusses auf die Entwurfsqualität, und (iii) die strukturelle Einbindung von massiv-parallelen, 3D-IC-spezifischen Verbindungsstrukturen während der Floorplanning-Phase. Das Ziel dieser Arbeit besteht darin, Verbindungsstrukturen mit deren wesentlichen Eigenschaften bereits in den frühen Phasen des Entwurfsprozesses zu berücksichtigen. Dies begünstigt einen qualitativ hochwertigen Entwurf von 3D-ICs. Die in dieser Arbeit vorgestellten modularen Entwurfsprozess-Erweiterungen bzw. -Methodiken dienen zur effizienten Lösung der oben genannten Problemstellungen. Experimentelle Untersuchungen bestätigen die Wirksamkeit sowie die Effektivität der erarbeiten Methoden. Darüber hinaus liefern sie praktische Erkenntnisse bezüglich der Anwendung von 3D-ICs und der Planung deren Verbindungsstrukturen. Diese Erkenntnisse sind zur Ableitung von Richtlinien für den erfolgreichen Entwurf von 3D-ICs dienlich.

Prenatal assessment of fetal health is routinely offered throughout pregnancy to ensure that the most effective management can be provided to maintain fetal and maternal well-being. Currently, invasive testing is used for definitive diagnosis of fetal aneuploidy, which is associated with a 1% risk of iatrogenic fetal loss. Developing non-invasive prenatal testing (NIPT) is a key area of research and methods to increase the level of cell-free fetal DNA (cffDNA) within the maternal circulation have been discussed to improve accuracy of such tests. In this study, three strategies; co-amplification at lower denaturation temperature polymerase chain reaction (COLD-PCR), inverse-PCR and Pippin Prep™ gel electrophoresis, were analysed to identify a novel approach to selectively enrich shorter cffDNA fragments from larger maternal cell-free DNA (cfDNA). The sensitivity of droplet digital PCR (ddPCR) against real-time PCR (qPCR) was compared for fetal sex and RHD genotyping. In addition RHD zygosity testing was carried out for non-maternal samples. Consequently, Pippin Prep™ gel electrophoresis was combined with ddPCR analysis for the NIPD of Down Syndrome (DS) in pseudo-maternal samples. The results revealed that the Pippin Prep™ gel electrophoresis enrichment approach successfully demonstrated 2-fold to 5-fold increases in the cffDNA fraction. However, further optimisation assays of COLD-PCR and inverse-PCR using actual maternal samples were required. The spike experiments for DS detection revealed that with the present assay IV overrepresentation of the chromosome 21 target could be significantly detected for samples with ≥15% ‘cffDNA fraction’. In conjunction with the Pippin Prep™ enrichment method, this would have enabled assessment of all 10 maternal samples. Alternatively, fetal sex and RHD genotyping results determined that ddPCR provides a more sensitive platform compared to qPCR approaches, particularly for samples that express low cffDNA fractions (<2%). The ddPCR platform also proved to be a rapid and accurate system for the determination of RHD zygosity. This study highlights that ddPCR could be used as opposed to qPCR for accurate determination of fetal sex and RHD status. While sequencing approaches currently provide the most sensitive platforms for NIPT of fetal aneuploidy, high costs (>£400) prevent universal application. The combination of cffDNA enrichment with ddPCR analysis could provide a cheaper and more widely available platform for NIPD. However, further large scale validation studies using actual maternal samples are required.

Over the past decade, the explosive growth of the Internet has led to a surge of interest to understand and predict aggregate behavior of large number of people or agents, particularly when they are connected through an underlying network structure. Numerous Internet-based applications have emerged that are as diverse as getting micro-tasks executed through online labor markets (also known as crowd sourcing) to acquiring new skills through massively open online courses (also known as MOOCs). However, there has been a major inadequacy in existing studies with respect to evaluating the impact of strategic behavior of the agents participating in such networks, crowds, and classrooms. The primary focus of this doctoral work is to understand the equilibrium behaviour emerging from these real-world, strategic environments by blending ideas from the areas of game theory, graph theory, and optimization, to derive novel solutions to these new-age economic models. In particular, we investigate the following three research challenges: (1) How do strategic agents form connections with one another? Will it ever happen that strategically stable networks are social welfare maximizing as well? (2) How do we design mechanisms for eliciting truthful feedback about an object (perhaps a new product or service or person) from a crowd of strategic raters? What can we tell about these mechanisms when the raters are connected through a social network? (3) How do we incentivize better participation of instructors and students in online edu-cation forums? Can we recommend optimal strategies to students and instructors to get the best out of these forums?

Vertical stacking—based on modern manufacturing and integration technologies—of multiple 2D chips enables three-dimensional integrated circuits (3D ICs). This exploitation of the third dimension is generally accepted for aiming at higher packing densities, heterogeneous integration, shorter interconnects, reduced power consumption, increased data bandwidth, and realizing highly-parallel systems in one device. However, the commercial acceptance of 3D ICs is currently behind its expectations, mainly due to challenges regarding manufacturing and integration technologies as well as design automation. This work addresses three selected, practically relevant design challenges: (i) increasing the constrained reusability of proven, reliable 2D intellectual property blocks, (ii) planning different types of (comparatively large) through-silicon vias with focus on their impact on design quality, as well as (iii) structural planning of massively-parallel, 3D-IC-specific interconnect structures during 3D floorplanning. A key concept of this work is to account for interconnect structures and their properties during early design phases in order to support effective and high-quality 3D-IC-design flows. To tackle the above listed challenges, modular design-flow extensions and methodologies have been developed. Experimental investigations reveal the effectiveness and efficiency of the proposed techniques, and provide findings on 3D integration with particular focus on interconnect structures. We suggest consideration of these findings when formulating guidelines for successful 3D-IC design automation.:1 Introduction 1.1 The 3D Integration Approach for Electronic Circuits 1.2 Technologies for 3D Integrated Circuits 1.3 Design Approaches for 3D Integrated Circuits 2 State of the Art in Design Automation for 3D Integrated Circuits 2.1 Thermal Management 2.2 Partitioning and Floorplanning 2.3 Placement and Routing 2.4 Power and Clock Delivery 2.5 Design Challenges 3 Research Objectives 4 Planning Through-Silicon Via Islands for Block-Level Design Reuse 4.1 Problems for Design Reuse in 3D Integrated Circuits 4.2 Connecting Blocks Using Through-Silicon Via Islands 4.2.1 Problem Formulation and Methodology Overview 4.2.2 Net Clustering 4.2.3 Insertion of Through-Silicon Via Islands 4.2.4 Deadspace Insertion and Redistribution 4.3 Experimental Investigation 4.3.1 Wirelength Estimation 4.3.2 Configuration 4.3.3 Results and Discussion 4.4 Summary and Conclusions 5 Planning Through-Silicon Vias for Design Optimization 5.1 Deadspace Requirements for Optimized Planning of Through-Silicon Vias 5.2 Multiobjective Design Optimization of 3D Integrated Circuits 5.2.1 Methodology Overview and Configuration 5.2.2 Techniques for Deadspace Optimization 5.2.3 Design-Quality Analysis 5.2.4 Planning Different Types of Through-Silicon Vias 5.3 Experimental Investigation 5.3.1 Configuration 5.3.2 Results and Discussion 5.4 Summary and Conclusions 6 3D Floorplanning for Structural Planning of Massive Interconnects 6.1 Block Alignment for Interconnects Planning in 3D Integrated Circuits 6.2 Corner Block List Extended for Block Alignment 6.2.1 Alignment Encoding 6.2.2 Layout Generation: Block Placement and Alignment 6.3 3D Floorplanning Methodology 6.3.1 Optimization Criteria and Phases and Related Cost Models 6.3.2 Fast Thermal Analysis 6.3.3 Layout Operations 6.3.4 Adaptive Optimization Schedule 6.4 Experimental Investigation 6.4.1 Configuration 6.4.2 Results and Discussion 6.5 Summary and Conclusions 7 Research Summary, Conclusions, and Outlook Dissertation Theses Notation Glossary Bibliography / Dreidimensional integrierte Schaltkreise (3D-ICs) beruhen auf neuartigen Herstellungs- und Integrationstechnologien, wobei vor allem “klassische” 2D-ICs vertikal zu einem neuartigen 3D-System gestapelt werden. Dieser Ansatz zur Erschließung der dritten Dimension im Schaltkreisentwurf ist nach Expertenmeinung dazu geeignet, höhere Integrationsdichten zu erreichen, heterogene Integration zu realisieren, kürzere Verdrahtungswege zu ermöglichen, Leistungsaufnahmen zu reduzieren, Datenübertragungsraten zu erhöhen, sowie hoch-parallele Systeme in einer Baugruppe umzusetzen. Aufgrund von technologischen und entwurfsmethodischen Schwierigkeiten bleibt jedoch bisher die kommerzielle Anwendung von 3D-ICs deutlich hinter den Erwartungen zurück. In dieser Arbeit werden drei ausgewählte, praktisch relevante Problemstellungen der Entwurfsautomatisierung von 3D-ICs bearbeitet: (i) die Verbesserung der (eingeschränkten) Wiederverwendbarkeit von zuverlässigen 2D-Intellectual-Property-Blöcken, (ii) die komplexe Planung von verschiedenartigen, verhältnismäßig großen Through-Silicion Vias unter Beachtung ihres Einflusses auf die Entwurfsqualität, und (iii) die strukturelle Einbindung von massiv-parallelen, 3D-IC-spezifischen Verbindungsstrukturen während der Floorplanning-Phase. Das Ziel dieser Arbeit besteht darin, Verbindungsstrukturen mit deren wesentlichen Eigenschaften bereits in den frühen Phasen des Entwurfsprozesses zu berücksichtigen. Dies begünstigt einen qualitativ hochwertigen Entwurf von 3D-ICs. Die in dieser Arbeit vorgestellten modularen Entwurfsprozess-Erweiterungen bzw. -Methodiken dienen zur effizienten Lösung der oben genannten Problemstellungen. Experimentelle Untersuchungen bestätigen die Wirksamkeit sowie die Effektivität der erarbeiten Methoden. Darüber hinaus liefern sie praktische Erkenntnisse bezüglich der Anwendung von 3D-ICs und der Planung deren Verbindungsstrukturen. Diese Erkenntnisse sind zur Ableitung von Richtlinien für den erfolgreichen Entwurf von 3D-ICs dienlich.:1 Introduction 1.1 The 3D Integration Approach for Electronic Circuits 1.2 Technologies for 3D Integrated Circuits 1.3 Design Approaches for 3D Integrated Circuits 2 State of the Art in Design Automation for 3D Integrated Circuits 2.1 Thermal Management 2.2 Partitioning and Floorplanning 2.3 Placement and Routing 2.4 Power and Clock Delivery 2.5 Design Challenges 3 Research Objectives 4 Planning Through-Silicon Via Islands for Block-Level Design Reuse 4.1 Problems for Design Reuse in 3D Integrated Circuits 4.2 Connecting Blocks Using Through-Silicon Via Islands 4.2.1 Problem Formulation and Methodology Overview 4.2.2 Net Clustering 4.2.3 Insertion of Through-Silicon Via Islands 4.2.4 Deadspace Insertion and Redistribution 4.3 Experimental Investigation 4.3.1 Wirelength Estimation 4.3.2 Configuration 4.3.3 Results and Discussion 4.4 Summary and Conclusions 5 Planning Through-Silicon Vias for Design Optimization 5.1 Deadspace Requirements for Optimized Planning of Through-Silicon Vias 5.2 Multiobjective Design Optimization of 3D Integrated Circuits 5.2.1 Methodology Overview and Configuration 5.2.2 Techniques for Deadspace Optimization 5.2.3 Design-Quality Analysis 5.2.4 Planning Different Types of Through-Silicon Vias 5.3 Experimental Investigation 5.3.1 Configuration 5.3.2 Results and Discussion 5.4 Summary and Conclusions 6 3D Floorplanning for Structural Planning of Massive Interconnects 6.1 Block Alignment for Interconnects Planning in 3D Integrated Circuits 6.2 Corner Block List Extended for Block Alignment 6.2.1 Alignment Encoding 6.2.2 Layout Generation: Block Placement and Alignment 6.3 3D Floorplanning Methodology 6.3.1 Optimization Criteria and Phases and Related Cost Models 6.3.2 Fast Thermal Analysis 6.3.3 Layout Operations 6.3.4 Adaptive Optimization Schedule 6.4 Experimental Investigation 6.4.1 Configuration 6.4.2 Results and Discussion 6.5 Summary and Conclusions 7 Research Summary, Conclusions, and Outlook Dissertation Theses Notation Glossary Bibliography

Siliziumnanodrähte (SiNWs) bieten aufgrund ihrer exzellenten elektrostatischen Kontrollierbarkeit eine gute Grundlage für die Entwicklung neuartiger Bauelemente, wie rekonfigurierbarer Feldeffekttransistoren (RFETs). Da SiNWs durch die Oxidation gezielt verzerrt werden können und diese Verzerrung die Bandstruktur des Siliziums verändert, bietet der Oxidationsprozess eine Möglichkeit, die Leitungseigenschaften der RFETs zu modulieren und eine symmetrische Transfercharakteristik zu erhalten. Die Untersuchung von SiNWs mit Durchmessern im einstelligen Nanometerbereich bedarf eines atomistischen Ansatzes. In der vorliegenden Arbeit wird mit einem reaktiven Kraftfeld die initiale Phase der Oxidation dünner SiNWs molekulardynamisch simuliert. Gegenstand der Untersuchungen sind die Temperaturabhängigkeit der Oxidation von <110>-SiNWs mit Anfangsradien von 10.2 Å sowie das Oxidationsverhalten von <110>- und <100>-SiNWs mit Anfangsradien von 5.1 Å. Dabei wird neben dem Sauerstoffanteil im Simulationssystem und der radial aufgelösten Dichte auch das radial aufgelöste Verhältnis zwischen Sauerstoff- und Siliziumatomen während der gesamten Simulationsdauer untersucht und ein Zusammenhang zur Dichte festgestellt. Darüber hinaus wird bei 300 K erstmals eine Analyse der Verzerrungsentwicklung während der initialen Oxidationsphase durchgeführt, bei der sich sowohl für <110>-SiNWs als auch für <100>-SiNWs eine tensile Verzerrung im unoxidierten Drahtkern einstellt. Wie eine Analyse der partiellen radialen Verteilungsfunktion zeigt, kommt es zu dieser Verzerrung, weil während der Oxidation die Grundstruktur des Siliziums im Oxid erhalten bleibt, durch die Einlagerung des Sauerstoffs allerdings der Bindungsabstand erhöht wird. Dieser erhöhte Bindungsabstand wird durch Bindungen zu Siliziumatomen im Oxid auch Siliziumatomen im unoxidierten Kern aufgezwungen.:Inhaltsverzeichnis Abbildungsverzeichnis Tabellenverzeichnis Abkürzungsverzeichnis Symbolverzeichnis 1. Einleitung 2. Theoretische Grundlagen 2.1. Molekulardynamik 2.2. Siliziumnanodrähte 2.3. Verzerrung und Verspannung 3. Modellsystem 3.1. Ausgangsstruktur 3.2. Vorrelaxation 3.3. Ablauf der Oxidation 4. Untersuchungsmethoden 4.1. Sauerstofffluenz, Oxidationsgrad und Oxidationsrate 4.2. Massendichte und Siliziumanteil 4.3. Radiale Verteilungsfunktion 4.4. Verzerrung 4.4.1. <110>-Draht 4.4.2. <100>-Draht 5. Ergebnisse und Diskussion 5.1. Festlegung des Einsetzintervalls 5.2. Temperaturvariation 5.2.1. Oxidationsgrad 5.2.2. Siliziumanteil 5.2.3. Massendichte 5.2.4. Radiale Verteilungsfunktion 5.3. Radius- und Orientierungsvariation 5.4. Verzerrung 6. Zusammenfassung und Ausblick 6.1. Zusammenfassung 6.2. Ausblick A. Festlegung des Einsetzintervalls Literaturverzeichnis

This paper investigates the use of deep Convolutional Neural Networks for modeling the intronic regulation of Alternative Splicing on the basis of DNA sequence. By training the CNN on massively parallel synthetic DNA libraries of Alternative 5'-splicing and Alternatively Skipped exon events, the model is capable of predicting the relative abundance of alternatively spliced mRNA isoforms on held-out library data to a very high accuracy (R2 = 0.77 for Alt. 5'-splicing). Furthermore, the CNN is shown to generalize alternative splicing across cell lines efficiently. The Convolutional Neural Net is tested against a Logistic regression model and the results show that while prediction accuracy on the synthetic library is notably higher compared to the LR model, the CNN is worse at generalizing to new intronic contexts. Tests on non-synthetic human SNP genes suggest the CNN is dependent on the relative position of the intronic region it was trained for, a problem which is alleviated with LR. The increased library prediction accuracy of the CNN compared to Logistic regression is concluded to come from the non-linearity introduced by the deep layer architecture. It adds the capacity to model complex regulatory interactions and combinatorial RBP effects which studies have shown largely affect alternative splicing. However, the architecture makes interpreting the CNN hard, as the regulatory interactions are encoded deep within the layers. Nevertheless, high-performance modeling of alternative splicing using CNNs may still prove useful in numerous Synthetic biology applications, for example to model differentially spliced genes as is done in this paper. / Den här uppsatsen undersöker hur djupa neurala nätverk baserade på faltning ("Convolutions") kan användas för att modellera den introniska regleringen av Alternativ Splicing med endast DNA-sekvensen som indata. Nätverket tränas på ett massivt parallelt bibliotek av syntetiskt DNA innehållandes Alternativa Splicing-event där delar av de introniska regionerna har randomiserats. Uppsatsen visar att nätverksarkitekturen kan förutspå den relativa mängden alternativt splicat RNA till en mycket hög noggrannhet inom det syntetiska biblioteket. Modellen generaliserar även alternativ splicing mellan mänskliga celltyper väl. Hursomhelst, tester på icke-syntetiska mänskliga gener med SNP-mutationer visar att nätverkets prestanda försämras när den introniska region som används som indata flyttas i jämförelse till den relativa position som modellen tränats på. Uppsatsen jämför modellen med Logistic regression och drar slutsatsen att nätverkets förbättrade prestanda grundar sig i dess förmåga att modellera icke-linjära beroenden i datan. Detta medför dock svårigheter i att tolka vad modellen faktiskt lärt sig, eftersom interaktionen mellan reglerande element är inbäddat i nätverkslagren. Trots det kan högpresterande modellering av alternativ splicing med hjälp av neurala nät vara användbart, exempelvis inom Syntetisk biologi där modellen kan användas för att kontrollera regleringen av splicing när man konstruerar syntetiska gener.