In this work, a 3.5 GHz RF Transmitter and Successive Approximation ADC design has been presented. The transmitter serves as an intermediate block which translates 350 MHz signal into 3.5 GHz signal. This signal is applied to 6-40 GHz wideband transmitter. The emphasis is on the design of Up conversion Mixer with high linearity, low noise and moderate image rejection performance. The successive approximation analog to digital converter was designed as a part of feedback loop control, which consists of a sensor circuit to detect the temperature changes in a power amplifier and the ADC to convert the sensor output to digital data. The data is used to determine the necessary control signals to restore the performance of the power amplifier. The circuits have been designed and implemented in ST Microelectronics CMOS 90nm process.

To enable fast and reliable processors, advances must be made in the interconnections on the printed circuit board and in the interconnections from the chip to the printed circuit board. Processing techniques have been demonstrated to fabricate a copper-clad encapsulated air dielectric layer to enable low loss off-chip electrical signal lines using sacrificial polymers and the three dimensional patterning capabilities of imprint lithography. The inclusion of an air gap can eliminate the dielectric loss allowing the signal to propagate over longer lengths. Additionally, the low dielectric constant of air lowers the loss contributions from the conductor and increases the signal propagation velocity reducing delay. The metal shielding could minimize the crosstalk noise and radiation losses that are significant at high frequencies. The three dimensional patterning capabilities of imprint lithography fabricated curved structures and rounded terminations which can reduce reflections at discontinuities. Furthermore, imprint lithography also created planarized surfaces which simplified the buildup process. Since imprint lithography, only uses temperature and pressure to make a pattern it is an inexpensive and simple process advancement. The metal-clad encapsulated air dielectric structures were fabricated in a comparable number of registration steps to traditional transmission lines. Implementation of all copper chip to substrate interconnects would provide high conductivity electrical connections, resistance to electromigration while avoiding formation of brittle intermetallics. High aspect ratio polymer molds for copper electroplating interconnects could enable improved integrated circuit electrical performance. The properties of a new aqueous base develop, negative-tone photosensitive polynorbornene polymer have been characterized to develop mechanically compliant all copper connections between the chip and printed circuit board. High aspect ratio features of 7:1 (height:width) were produced in 70 ìm thick films in a single coat with straight side-wall profiles and high fidelity. The polymer films studied had a contrast of 11.6 and a low absorption coefficient. To evaluate the polymer's suitability to microelectronics applications, epoxy cross-linking reactions were studied as a function of processing condition through Fourier transform infrared spectroscopy, nano-indentation, and dielectric measurements. The fully cross-linked films had an elastic modulus of 2.9 GPa and hardness of 0.18 GPa which can improve the mechanical compliance of the copper interconnections. A photo-imprint lithography process was developed to improve the photo-patterning of the polynorbornene polymer for high aspect ratio hollow structures. A shallow photo-imprint stamp was developed to physically displace material in the polymer core. Since the imprint stamp displaces material in the area of the feature, the effective film thickness is reduced compared to the bulk film. The reduction in film height reduced the effects of scattering in the core and also facilitated transport of developer within the core. The photo-imprint lithography process resulted in high aspect ratio hollow core pillars that exceeded optical resolution capabilities for comparable feature sizes.

Heat removal technologies are among the most critical needs for three-dimensional (3D) stacking of high-performance microprocessors. This research reports a 3D integration platform that can support the heat removal requirements for 3D integrated circuits that contain high-performance microprocessors in the 3D stack. This work shows the use of wafer-level batch fabrication to develop advanced electrical and fluidic three-dimensional interconnect networks in a 3D stack. Fabrication results are shown for the integration of microchannels and electrical through-silicon vias (TSVs). A compact physical model is developed to determine the design trade-offs for microchannel heat sink and electrical TSV integration. An experimental thermal measurement test-bed for evaluating a 3D inter-layer liquid cooling platform is developed. Experimental thermal testing results for an air-cooled chip and a liquid-cooled chip are compared. Microchannel heat sink cooling shows a significant junction temperature and heat sink thermal resistance reduction compared to air-cooling. The on-chip integrated microchannel heat sink, which has a thermal resistance of 0.229 °C/W, enables cooling of >100W/cm² of each high-power density chip, while maintaining an average junction temperature of less than 50°C. Cooling liquid is circulated through the 3D stack (two layers) at flow rates of up to 100 ml/min. The ability to assemble chips with integrated electrical and fluidic I/Os and seal fluidic interconnections at each strata interface is demonstrated using three assembly and fluidic sealing techniques. Assembly results show the stacking of up to four chips that contain integrated electrical and fluidic I/O interconnects, with an electrical I/O density of ~1600/cm².

With continued push toward 3D integrated packaging, Through-Silicon Vias (TSVs) play an increasingly important role in interconnecting stacked silicon dies. Although progress is being made in the fabrication of TSVs, experimental and theoretical assessment of their thermomechanical reliability is still in infancy. This work explores the thermomechanical reliability of TSVs through numerical models and innovative experimental characterization techniques. Starting with free-standing wafers, this work examines failure mechanisms such as Si and SiO₂ cohesive cracking as well as SiO₂/Cu interfacial cracking. Such cohesive crack propagation and interfacial crack propagation are studied using fracture mechanics finite-element modeling, and the energy available for crack propagation is determined through crack extension using the proposed centered finite-difference approach (CFDA). In parallel to the simulations, silicon wafers with TSVs are designed and fabricated and subjected to thermal shock test. Cross-sectional SEM failure analysis is carried out to study cohesive and interfacial crack initiation and propagation under thermal excursions. In addition, local micro-strain fields under thermal excursions are mapped through synchrotron X-ray diffraction. To understand the 3D to 2D strain measurement data projection process, a new data interpretation method based on beam intensity averaging is proposed and validated with measurements. Building upon the work on free-standing wafers, this research studies the package assembly issues and failure mechanisms in multi-die stacks. Comprehensive design-of-simulations study is carried out to assess the effect of various material and geometry parameters on the reliability of 3D microelectronic packages. Through experimentally-measured strain fields, thermal cycling tests, and simulations, design guidelines are developed to enhance the thermomechanical reliability of TSVs used in future 3D microelectronic packages.

It has been conventional to simplify the thermo-mechanical modeling of solder joints by omitting the primary (transient) contributions to total creep deformation, assuming that secondary (steady-state) creep strain is dominant and primary creep is negligible. The error associated with this assumption has been difficult to assess because it depends on the properties of the solder joint and the temperature-time profile. This research examines the relative contributions of primary and secondary creep in Sn3.8Ag0.7Cu solder using the constant load creep and stress relaxation measurements for bulk tensile specimens and the finite element analysis of a chip resistor (trilayer) solder joint structure that was thermally cycled under multiple temperature ranges and ramp rates. It was found that neglect of primary creep can result in errors in the predicted stress and strain of the solder joint. In turn, these discrepancies can lead to errors in the estimation of the solder thermal fatigue life due to the changing proportion of primary creep strain to total inelastic strain under different thermal profiles. The constant-load creep and stress relaxation data for Sn3.8Ag0.7Cu span a range of strain rates 10(-8) 1/s < strain rate < 10(-4) 1/s, and temperatures 25°C, 75°C and 100°C. Creep and stress relaxation measurements show that transient creep caused faster strain rates during stress relaxation for a given stress compared to the corresponding minimum creep rate from constant-load creep tests. The extent of strain hardening during primary creep was a function of temperature and strain rate. A constitutive creep model was presented for Sn3.8Ag0.7Cu that incorporates both transient and steady-state creep to provide agreement for both creep and stress relaxation data with a single set of eight coefficients. The model utilizes both temperature compensated time and strain rate to normalize minimum strain rate and saturated transient creep strain, thereby establishing equivalence between decreased temperature and increased strain rate. The apparent activation energy of steady-state creep was indicative of both dislocation core and bulk lattice diffusion was the most sensitive model parameter. A saturation threshold was defined that distinguishes whether primary or secondary creep is dominant under either static or variable loading.

It has been conventional to simplify the thermo-mechanical modeling of solder joints by omitting the primary (transient) contributions to total creep deformation, assuming that secondary (steady-state) creep strain is dominant and primary creep is negligible. The error associated with this assumption has been difficult to assess because it depends on the properties of the solder joint and the temperature-time profile. This research examines the relative contributions of primary and secondary creep in Sn3.8Ag0.7Cu solder using the constant load creep and stress relaxation measurements for bulk tensile specimens and the finite element analysis of a chip resistor (trilayer) solder joint structure that was thermally cycled under multiple temperature ranges and ramp rates. It was found that neglect of primary creep can result in errors in the predicted stress and strain of the solder joint. In turn, these discrepancies can lead to errors in the estimation of the solder thermal fatigue life due to the changing proportion of primary creep strain to total inelastic strain under different thermal profiles. The constant-load creep and stress relaxation data for Sn3.8Ag0.7Cu span a range of strain rates 10(-8) 1/s < strain rate < 10(-4) 1/s, and temperatures 25°C, 75°C and 100°C. Creep and stress relaxation measurements show that transient creep caused faster strain rates during stress relaxation for a given stress compared to the corresponding minimum creep rate from constant-load creep tests. The extent of strain hardening during primary creep was a function of temperature and strain rate. A constitutive creep model was presented for Sn3.8Ag0.7Cu that incorporates both transient and steady-state creep to provide agreement for both creep and stress relaxation data with a single set of eight coefficients. The model utilizes both temperature compensated time and strain rate to normalize minimum strain rate and saturated transient creep strain, thereby establishing equivalence between decreased temperature and increased strain rate. The apparent activation energy of steady-state creep was indicative of both dislocation core and bulk lattice diffusion was the most sensitive model parameter. A saturation threshold was defined that distinguishes whether primary or secondary creep is dominant under either static or variable loading.

The current trend in electronics manufacturing is to decrease the size of electronic components while attempting to increase processing power and performance. This is leading to increased interest in thinner printed wiring boards and finer line widths and wire pitches. However, mismatches in the thermomechanical properties of materials used can lead to warpage, hindering these goals. Warpage can be problematic as it leads to misalignments during package assembly, reduced tolerances, and a variety of operational failures. Current warpage prediction techniques utilize isotropic volume averaging to estimate effective material properties in layers of copper mixed with interlayer dielectric material. However, these estimates do not provide material properties with sufficient accuracy to predict warpage, as they contain no information about the orientation of the copper traces. This thesis describes the development of a new technique to predict the warpage of a particular substrate. The technique accounts for both the trace pattern planar density and planar orientation in determining effective orthotropic material properties for each layer of a multi-layer substrate. Starting with the trace pattern image, this technique first divides the trace pattern into several smaller areas for a given layer of the substrate and then uses image processing techniques to determine the copper percentage and average trace orientation in each small area. The copper percentage and average trace direction orientation are used in conjunction with the material properties of copper and the dielectric material to calculate the effective orthotropic material properties of each smaller area of the substrate. A finite-element model is then created where each layer is represented as a concatenation of several small areas with independent directional properties, and such a model is then subjected to sequential thermal excursion as seen in the actual fabrication process. The results from the models have been compared against experimental data with a great degree of accuracy. The modeling technique and the results obtained clearly demonstrate the need for the proposed subdivisional orthotropic material property calculations, as opposed to homogeneous isotropic properties typically used for each layer in computational simulations, as these more accurate directional properties are capable of predicting warpage with higher accuracy.