Discrete silicon carbide (SiC) power devices have unique characteristics that outpace those of silicon (Si) counterparts. The improved physical features have provided better faster switching, greater current densities, lower on-resistance, and temperature performances. However, there is lack of suitable commercial gate drivers that are compatible for high-voltage, and high-speed devices. There has been a great research effort required for the advancement of gate drivers for high voltage SiC transistors. A drive circuit for a SiC MOSFET needs to be optimized in normal operation to give best efficiency and same drive circuit should secure the MOSFET under unsuitable conditions. To ensure the rapid switching of these advanced SiC MOSFETs, a gate driver capable of providing the high current capability is required. In this work, three different high-power-density, high-speed, and high-noise-immunity gate driver modules for 10 kV SiC MOSFET were built and optimized.  Double-pulse test was developed for the dynamic characterization of SiC MOSFETs and gate drivers. This setup provided clean measurements of DUT voltage and current under well-defined conditions and correlated to simulation results. Designed gate drivers have thoroughly investigated to test and compare it with our future design. The influential parameters such as dV/dt, dI/dt, and gate driving capability of gate driver were adjusted according to the requirements. The short circuit protection test was performed to check the reliability of driver modules in worst conditions. Furthermore, a DC-DC converter was designed and tested with the advanced gate drivers. The driver modules were tested in designed converter under different load conditions and influential parameters were successfully demonstrated. The driver modules effectively helped in reducing the EMI and switching losses. These designed gate drivers and prototype converter provide all the attractive features and can be widely implemented in industrial applications for energy efficient systems.

In this dissertation, we use finite element method together with other numerical techniques to study advanced electron devices. We study the radiation properties in electron waveguide structure with multi-step discontinuities and soft wall lateral confinement. Radiation mechanism and conditions are examined by numerical simulation of dispersion relations and transport properties. The study of geometry variations shows its significant impact on the radiation intensity and direction. In particular, the periodic corrugation structure exhibits strong directional radiation. This interesting feature may be useful to design a nano-scale transmitter, a communication device for future nano-scale system. Non-quasi-static effects in AC characteristics of carbon nanotube field-effect transistors are examined by solving a full time-dependent, open-boundary Schrödinger equation. The non-quasi-static characteristics, such as the finite channel charging time, and the dependence of small signal transconductance and gate capacitance on the frequency, are explored. The validity of the widely used quasi-static approximation is examined. The results show that the quasi-static approximation overestimates the transconductance and gate capacitance at high frequencies, but gives a more accurate value for the intrinsic cut-off frequency over a wide range of bias conditions. The influence of metal interconnect resistance on the performance of vertical and lateral power MOSFETs is studied. Vertical MOSFETs in a D2PAK and DirectFET package, and lateral MOSFETs in power IC and flip chip are investigated as the case studies. The impact of various layout patterns and material properties on RDS(on) will provide useful guidelines for practical vertical and lateral power MOSFETs design.

For decades, the Silicon-based semiconductors have been the solution for power electronics applications. However, these semiconductors have approached their limits of operation in blocking voltage, working temperature and switching frequency. Due to material superiority, the relatively-new wide-bandgap semiconductors such as Silicon-Carbide (SiC) MOSFETs enable higher voltages, switching frequencies and operating temperatures when compared to Silicon technology, resulting in improved converter specifications. The current study tries to investigate the impact of emerging medium-voltage SiC MOSFETs on industrial motor drive application, where over a quarter of the total electricity in the world is being consumed. Firstly, non-commercial SiC MOSFETs at 3.3 kV and 400 A rating are characterized to enable converter design and simulation based on them. In order to feature the best performance out of the devices under test, an intelligent high-performance gate driver is designed embedding required functionalities and protections. Secondly, total of three converters are targeted for industrial motor drive application at medium-voltage and high-power range. For this purpose the cascaded H-bridge, the modular multilevel converter and the 5-L active neutral point clamped converters are designed at 4.16-, 6.9- and 13.8 kV voltage ratings and 3- and 5 MVA power ratings. Selection of different voltage and power levels is done to elucidate variation of different parameters within the converters versus operating point. Later, comparisons are done between the surveyed topologies designed at different operating points based on Si IGBTs and SiC MOSFETs. The comparison includes different aspects such as efficiency, power density, semiconductor utilization, energy stored in converter structure, fault containment, low-speed operation capability and parts count (for a measure of reliability). Having the comparisons done based on simulation data, an H-bridge cell is implemented using 3.3 kV 400 A SiC MOSFETs to evaluate validity of the conducted simulations. Finally, a novel method is proposed for series-connecting individual SiC MOSFETs to reach higher voltage devices. Considering the fact that currently the SiC MOSFETs are not commercially available at voltages higher above 1.7 kV, this will enable implementation of converters using medium-voltage SiC MOSFETs that are achieved by stacking commercially-available 1.7 kV MOSFETs. The proposed method is specifically developed for SiC MOSFETs with high dv/dt rates, while majority of the existing solutions could only work merely with slow Si-based semiconductors. / Ph. D.

La microscopie à émission de photons spectrale (SPEM) est une technique non destructive utilisée comme outil de localisation des défauts et comme indicateur des mécanismes de défaillance. Cette thèse présente un nouveau système de SPEM développé pour étudier la fiabilité des dispositifs de puissance à large bande interdite, notamment les MOSFET SiC et les MEMTs AlGaN/GaN. Un aperçu des différents aspects fondamentaux de l'émission de lumière dans les dispositifs à semi-conducteurs est présenté. L'analyse spectrale en électroluminescence des MOSFET SiC à haute puissance et des HEMTs AlGaN/GaN est rapportée et corrélée avec des analyses électriques et micro-structurales pour localiser les défaillances et identifier l'origine physique de la dérive des performances de ces composants. / Spectroscopic photon emission microscopy (SPEM) is a non-destructive technique used as a defect localizing tool and as an indicator of the failure mechanisms. This thesis presents a new system of SPEM developed to study the reliability of wide band Gap power devices notably SiC MOSFETs and AlGaN/GaN HEMTs. An overview of different fundamental aspects of the light emission defects on semiconductors devices is presented. The electroluminescence spectral analysis of high power stressed SiC MOSFETs and AlGaN/GaN HEMTs is reported and correlated with electrical and micro-structural analysis to localize the failures and identify the physical origin of the performance drift of these components.

NASA missions require innovative power electronics system and component solutions with long life capability, high radiation tolerance, low mass and volume, and high reliability in space environments. Presently vertical double-diffused MOSFETs (VDMOS) are the most widely used power switching device for space power systems. It is proposed that a new lateral double-diffused MOSFET (LDMOS) designed at UCF can offer improvements in total dose and single event radiation hardness, switching performance, development and manufacturing costs, and total mass of power electronics systems. Availability of a hardened fast-switching power MOSFET will allow space-borne power electronics to approach the current level of terrestrial technology, thereby facilitating the use of more modern digital electronic systems in space. It is believed that the use of a p+/p-epi starting material for the LDMOS will offer better hardness against single-event burnout (SEB) and single-event gate rupture (SEGR) when compared to vertical devices fabricated on an n+/n-epi material. By placing a source contact on the bottom-side of the p+ substrate, much of the hole current generated by a heavy ion strike will flow away from the dielectric gate, thereby reducing electrical stress on the gate and decreasing the likelihood of SEGR. Similarly, the device is hardened against SEB by the redirection of hole current away from the base of the device's parasitic bipolar transistor. Total dose hardness is achieved by the use of a standard complementary metal-oxide semiconductor (CMOS) process that has shown proven hardness against total dose radiation effects.

Ce travail de thèse présente une évaluation approfondie des différentes techniques de mesure transitoire et dynamique pour l’évaluation du comportement électro-thermique des transistors bipolaires à hétérojonctions HBT SiGe:C de la technologie BiCMOS et des transistors Métal-Oxyde-Semiconducteur à effet de champ (MOSFET) de la technologie CMOS 45nm. En particulier, je propose une nouvelle approche pour caractériser avec précision le régime transitoire d'auto-échauffement, basée sur des mesures impulsionelles. La méthodologie a été vérifiée par des mesures statiques à différentes températures ambiantes, des mesures de paramètres S à basses fréquences et des simulations thermiques transitoires. Des simulations thermiques par éléments finis (TCAD) en trois dimensions ont été réalisées sur les transistors HBTs de la technologie submicroniques SiGe: C BiCMOS. Cette technologie est caractérisée par une fréquence de transition fT de 230 GHz et une fréquence maximum d’oscillation fMAX de 290 GHz. Par ailleurs, cette étude a été réalisée sur les différentes géométries de transistor. Une évaluation complète des mécanismes d'auto-échauffement dans les domaines temporels et fréquentiels a été réalisée. Une expression généralisée de l'impédance thermique dans le domaine fréquentiel a été formulée et a été utilisé pour extraire cette impédance en deçà de la fréquence de coupure thermique. Les paramètres thermiques ont été extraits par des simulations compactes grâce au modèle compact de transistors auquel un modèle électro-thermique a été ajouté via le nœud de température. Les travaux théoriques développés à ce jour pour la modélisation d'impédance thermique ont été vérifiés avec nos résultats expérimentaux. Il a été montré que, le réseau thermique classique utilisant un pôle unique n'est pas suffisant pour modéliser avec précision le comportement thermique transitoire et donc qu’un réseau plus complexe doit être utilisé. Ainsi, nous validons expérimentalement pour la première fois, le modèle distribué électrothermique de l'impédance thermique utilisant un réseau nodal récursif. Le réseau récursif a été vérifié par des simulations TCAD, ainsi que par des mesures et celles ci se sont révélées en excellent accord. Par conséquent, un modèle électro-thermique multi-géométries basé sur le réseau récursif a été développé. Le modèle a été vérifié par des simulations numériques ainsi que par des mesures de paramètre S à basse fréquence et finalement la conformité est excellente quelque soit la géométrie des dispositifs. / An extensive evaluation of different techniques for transient and dynamic electro-thermal behavior of microwave SiGe:C BiCMOS hetero-junction bipolar transistors (HBT) and nano-scale metal-oxide-semiconductor field-effect transistors (MOSFETs) have been presented. In particular, new and simple approach to accurately characterize the transient self-heating effect, based on pulse measurements, is demonstrated. The methodology is verified by static measurements at different ambient temperatures, s-parameter measurements at low frequency region and transient thermal simulations. Three dimensional thermal TCAD simulations are performed on different geometries of the submicron SiGe:C BiCMOS HBTs with fT and fmax of 230 GHz and 290 GHz, respectively. A comprehensive evaluation of device self-heating in time and frequency domain has been investigated. A generalized expression for the frequency-domain thermal impedance has been formulated and that is used to extract device thermal impedance below thermal cut-off frequency. The thermal parameters are extracted through transistor compact model simulations connecting electro-thermal network at temperature node. Theoretical works for thermal impedance modeling using different networks, developed until date, have been verified with our experimental results. We report for the first time the experimental verification of the distributed electrothermal model for thermal impedance using a nodal and recursive network. It has been shown that, the conventional single pole thermal network is not sufficient to accurately model the transient thermal spreading behavior and therefore a recursive network needs to be used. Recursive network is verified with device simulations as well as measurements and found to be in excellent agreement. Therefore, finally a scalable electro-thermal model using this recursive network is developed. The scalability has been verified through numerical simulations as well as by low frequency measurements and excellent conformity has been found in for various device geometries.

No description available.

L'objectif de cette thèse est d'atteindre 0,5 V haute vitesse faible puissance SRAM. Pour ce faire, les cellules SRAM de pointe, des tableaux et des architectures de bus sont examinées. Les questions difficiles sont alors précisées. Pour répondre aux exigences, une cellule de 5T d'alimentation statique de puissance boostée, combiné avec WL boosté et milieu point de détection et d'un tableau de multi divisé BL ouvert sont proposées et évaluées. Pour encore accélérer l'opération d'écriture, un tableau de 4Kb sélectivement stimulé puissance alimentation 5T cell est proposé et évalué par simulation. Nous découvrons que le point milieu de détection avec moitié VDD BL precharge est plus stable lors de lire que la VDD complet conventionnelle precharge. En outre, pour atteindre un bus robuste à grande vitesse de faible puissance 0,5-V,une architecture de bus dynamique avec un bus factice, qui se compose d'un pilote de dynamique et d'un récepteur dynamique, est proposée. Le pilote dynamique permeten particulier de grande vitesse même à 0,5 V avec overdrive porte accrue enchangeant les lignes électriques de VDD/2 en mode veille avec VDD en mode actif. Ilaccélère encore avec l'aide du bus factice cette impulsion gena pour suivre le point dedétection tension du bus pour réduire l'oscillation de l'autobus. Ensuite, unearchitecture de bus 0,5-V 28 nm FD-SOI 32 bits à l'aide de la proposition estevaluaevaluated par simulation. Il s'avère que l'architecture a un potentiel à exploiterun bus 1-pF à 50-mV swing, 1,2 GHz et un courant de veille de 1,1 µA, avec x3-5 plus rapidement et plus de deux ordre plus faible courant de veille que l'architecture statique conventionnelle. / The goal of the thesis is to achieve 0.5-V high-speed low-power SRAMs. To do so, state-of-the-art SRAM cells, arrays, and bus-architectures are reviewed. The challenging issues are then clarified as 1) reduction of the minimum operating voltage VDD (Vmin) of the cell, 2) reducing bitline (BL)-active power, and 3) achieving low-power bus architecture. To meet the requirements, a static boosted-power-supply 5T cell, combined with boosted-WL and mid-point-sensing, and an open-BL multi-divided-array are proposed and evaluated. Layout and post-layout simulation with a 28-nm fully-depleted planar-logic SOI MOSFET reveal that a 0.5-V 5T-cell 4-kb array in a 128-kb SRAM core is able to achieve x2-3 faster cycle time and x11 lower power than the counterpart 6T-cell array, suggesting a possibility of a 730-ps cycle time at 0.5 V.To further speed up the write operation, a selectively-boosted-power-supply 5T-cell 4-kb array is proposed and evaluated by simulation, showing that the 4-kb array operates at 350-ps cycle with x6 faster cycle time and x13 lower power than the 6T-cell array, while maintaining a small leakage current. We find out that the mid-point-sensing with half-VDD BL-precharging is more stable during read than the conventional full-VDD precharging. Furthermore, to achieve a 0.5-V low-power high-speed robust bus, a dynamic bus architecture with a dummy bus, which consists of a dynamic driver and a dynamic receiver, is proposed. In particular, the dynamic driver enables high speed even at 0.5 V with increased gate-over-drive by changing the power lines from VDD/2 in the standby mode to VDD in the active mode. It further speeds up with the help of the dummy bus that generates a pulse to track the bus-voltage detecting point for reducing the bus swing. Then, a 0.5-V 28-nm-FD-SOI 32-bit bus architecture using the proposal is evaluated by simulation. It turns out that the architecture has a potential to operate a 1-pF bus at about 50-mV swing, 1.2 GHz, and a standby current of 1.1 µA, with x3-5 faster and more than two-order lower standby current than the conventional static architecture. Based on the results, further challenges to 0.5-V and sub-0.5-V SRAMs are described.