<p>During the past years has the Nostrum Network on Chip <i>(NoC)</i> been developed to become a competitive platform for network based on-chip communication. The Nostrum NoC provides a versatile communication platform to connect a large number of intellectual properties <i>(IP) </i>on a single chip. The communication is based on a packet switched network which aims for a small physical footprint while still providing a low communication overhead. To reduce the communication network size, a queue-less network has been the research focus. This network uses de ective hot-potato routing which is implemented to perform routing decisions in a single clock cycle.</p><p>Using a platform like this results in increased design reusability, validated signal integrity, and well developed test strategies, in contrast to a fully customised designs which can have a more optimal communication structure but has a significantly longer development cycle to verify the new design accordingly.</p><p>Several factors are considered when designing a communication platform. The goal is to create a platform which provides low communication latency, high throughput, low power consumption, small footprint, and low design, verification, and test overhead. Proximity Congestion Awareness is one technique that serves to reduce</p><p>the network load. This leads to that the latency is reduced which also increases the network throughput. Another technique is to implement low latency paths called<i> Data Motorways</i> achieved through a clocking method called Globally Pseudochronous Locally Synchronous clocking. Furthermore, virtual circuits can be used to provide guarantees on latency and throughput. Such guarantees are dificult in</p><p>hot-potato networks since network access has to be ensured. A technique that implements virtual circuits use looped containers that are circulating on a predefined circuit. Several overlapping virtual circuits are possible by allocating the virtual circuits in different Temporally Disjoint Networks.</p><p>This thesis summarise the impact the presented techniques and methods have on the characteristics on the Nostrum model. It is possible to reduce the network load by a factor of 20 which reduces the communication latency. This is done by distributing load information between the Switches in the network. Data Motorways</p><p>can reduce the communication latency with up to 50% in heavily loaded networks. Such latency reduction results in freed buffer space in the Switch registers which allows the traffic rate to be increased with about 30%.</p>

During the past years has the Nostrum Network on Chip (NoC) been developed to become a competitive platform for network based on-chip communication. The Nostrum NoC provides a versatile communication platform to connect a large number of intellectual properties (IP) on a single chip. The communication is based on a packet switched network which aims for a small physical footprint while still providing a low communication overhead. To reduce the communication network size, a queue-less network has been the research focus. This network uses de ective hot-potato routing which is implemented to perform routing decisions in a single clock cycle. Using a platform like this results in increased design reusability, validated signal integrity, and well developed test strategies, in contrast to a fully customised designs which can have a more optimal communication structure but has a significantly longer development cycle to verify the new design accordingly. Several factors are considered when designing a communication platform. The goal is to create a platform which provides low communication latency, high throughput, low power consumption, small footprint, and low design, verification, and test overhead. Proximity Congestion Awareness is one technique that serves to reduce the network load. This leads to that the latency is reduced which also increases the network throughput. Another technique is to implement low latency paths called Data Motorways achieved through a clocking method called Globally Pseudochronous Locally Synchronous clocking. Furthermore, virtual circuits can be used to provide guarantees on latency and throughput. Such guarantees are dificult in hot-potato networks since network access has to be ensured. A technique that implements virtual circuits use looped containers that are circulating on a predefined circuit. Several overlapping virtual circuits are possible by allocating the virtual circuits in different Temporally Disjoint Networks. This thesis summarise the impact the presented techniques and methods have on the characteristics on the Nostrum model. It is possible to reduce the network load by a factor of 20 which reduces the communication latency. This is done by distributing load information between the Switches in the network. Data Motorways can reduce the communication latency with up to 50% in heavily loaded networks. Such latency reduction results in freed buffer space in the Switch registers which allows the traffic rate to be increased with about 30%. / QC 20101122

The Silago concept introduces a hardware-centric platform that is based on coarse-grained reconfigurable fabrics and networks on chips(NoCs). With the intra-region and inter-region NoC, the Silago platform can form resource clusters to host various applications. The conventional global interconnection is implemented with a two-level NoC, which potentially results in heavyweight hardware and unpredictable behavior. Targeting optimizing the global inter-region data transfer, we propose a mathematical model that clarifies the scheduling mechanism, and present a software-defined interconnection solution that exploits the awareness of access pattern. The solution requires a executor which is expected to be a programmable lightweight transmitter. Considering that existing instruction set architectures(ISAs) lack direct support for single-cycle loop instruction, we propose a self-defined instruction set, which reduces the program size and enhances the schedulability. Based on the instruction set, we implemented the transmitter in the abstraction level of register transfer level(RTL). We also established a constraint random stimulus-based verification environment. The design is verified by regression test and synthesized. The results show that the design is functionally correct and synthesizable. Overall, the programmable transmitter helps to enable a composable interconnect scheme to connect hard IPs. / Silago-konceptet introducerar en hårdvarucentrerad plattform som är baserad på grovkorniga omkonfigurerbara tyger och nätverk på chips. Med intra-region och interregion NoC kan Silago-plattformen bilda resurskluster för att vara värd för olika applikationer. Den konventionella globala sammankopplingen är implementerad med en tvånivås NoC, vilket potentiellt resulterar i tung hårdvara och oförutsägbart beteende. Med inriktning på att optimera den globala dataöverföringen mellan regioner, föreslår vi en matematisk modell som klargör schemaläggningsmekanismen och presenterar en mjukvarudefinierad sammankopplingslösning som utnyttjar medvetenheten om åtkomstmönster. Lösningen kräver en executor som förväntas till en programmerbar lättviktssändare. Med tanke på att befintliga instruktionsuppsättningsarkitekturer (ISA) saknar direkt stöd för enkelcykelslinginstruktioner, föreslår vi en självdefinierad instruktionsuppsättning, som minskar programstorleken och förbättrar schemaläggningsbarheten. Baserat på instruktionsuppsättningen implementerade vi sändaren i abstraktionsnivån för registeröverföringsnivå (RTL). Vi etablerade också en slumpmässig stimulansbaserad verifieringsmiljö. Designen verifieras genom regressionstest och syntetiseras. Resultaten visar att designen är funktionellt korrekt och syntetiserbar.

Synchoros VLSI design style can be an alternative choice to fit the increasing complexity of embedded multi-processor architectures. SiLago Block is part of the synchoros blocks, which can effectively reduce the cost of logic and physical synthesis as it is hardened and highly centralized details from each layer of metal. Global NoCs play an essential part in system-level design and there is necessary to benchmark the SiLago global NoC against other existing NoC libraries. In this degree project, the structure of the NoC is established based on the SiLago models, including the wires and the switches. The whole structure has nine times nine grids and sixteen switches are placed inside symmetrically. The connection between two adjacent switches is built up by wires. The routing algorithm inside the switches can support the most common routing situations by destinations, routing states, and routing history. Except the routing algorithm, this essay provides some deadlock situations and also conclude some ways to solve them. The scripts developed from the NoC generator can be used to do the logical and physical synthesis for the SiLago models. The results from the synthesis can be explored to compare against other methods about the hability to estimate cost metrics from a high level of abstraction and the quality of results. The concept of partition is introduced to accomplish physical synthesis, and through this, the design can be more approach to the core idea of synchoros VLSI design. / Synchoros VLSI designstil kan vara ett alternativt val för att passa den ökande komplexiteten hos inbäddade flerprocessorarkitekturer. SiLago Block är en del av synchoros-blocken, som effektivt kan minska kostnaderna för logik och fysisk syntes eftersom det är härdat och mycket centraliserade detaljer från varje lager av metall. Globala NoC spelar en viktig roll i design på systemnivå och det är nödvändigt att jämföra SiLago globala NoC mot andra befintliga NoC-bibliotek. I detta examensarbete fastställs strukturen för NoC baserat på SiLago-modellerna, inklusive ledningarna och switcharna. Hela strukturen har nio gånger nio rutnät och sexton brytare är placerade inuti symmetriskt. Förbindelsen mellan två intilliggande brytare byggs upp av ledningar. Routingalgoritmen inuti switcharna kan stödja de vanligaste routingsituationerna efter destinationer, routingtillstånd och routinghistorik. Förutom routingalgoritmen ger den här uppsatsen några dödlägessituationer och kommer också fram till några sätt att lösa dem. Skripten som utvecklats från NoC-generatorn kan användas för att göra den logiska och fysiska syntesen för SiLago-modellerna. Resultaten från syntesen kan utforskas för att jämföras med andra metoder om förmågan att uppskatta kostnadsmått från en hög abstraktionsnivå och kvaliteten på resultaten. Begreppet partition introduceras för att åstadkomma fysisk syntes, och genom detta kan designen vara mer förhållningssätt till kärnidén med synchoros VLSI-design.

Formal System Design (ForSyDe) aims to bring the design of multiprocessor systems-on-chip (MPSoCs) to a higher level of abstraction and bridge the abstraction gap by transformational design refinement. The current research is focused on a correct-by-construction design flow, which requires design space exploration including formal models of computation and timepredictable platforms. The latter is widely used for hard real-time systems. In order to make a platform time-predictable, all components, as well as inter-core communication, need to have the worst-case execution time (WCET) estimations and be easily analyzed. Time-division multiplexing (TDM) networks can precisely allocate network resources at each time point and further provide time-predictable guarantees. However, the application developer must take the time to understand the hardware and capabilities of a network-on-chip (NoC) in order to communicate between the cores. Moreover, a wide variety of communication libraries belonging to different platforms increase the learning cost. The Message Passing Interface (MPI) standard inspires this project. For time-predictable communication on TDM-based MPSoCs, a specification with communication primitives should also be necessary for either system designers or application developers. Compared with the MPI standard, this specification should be lighter because it only elaborates on timepredictable communication. Besides, platforms it applies to are limited to real-time NoCs using TDM, which the worst-case communication time (WCCT) could be calculated at an early stage of the design. In this project, we abstracted from concurrency and communication libraries of existing platforms and derived communication primitives to this specification. Two different communication modes, push-based and interactive, are summarized. Push-based communication composes of checking the direct memory access (DMA) status, pushing the message, and checking the receiving buffer. Interactive communication comprises sending, receiving, and acknowledging primitives, which are divided into blocking and non-blocking. In addition, this specification permits the user to calculate WCCT of transmitting a message from one processor to another if one knows the size of messages transmitted and hardware configuration by addingWCET of all communication operations running on a single processor and latency of the communication connection together. The calculation process is shown using an existing platform. / Formell systemdesign (ForSyDe) syftar till att föra designen av multiprocessor system-on-chip (MPSoC) till en högre abstraktionsnivå och överbrygga abstraktionsgapet genom transformationell designförfining. Den aktuella forskningen är fokuserad på ett designflöde som är korrekt för konstruktion, vilket kräver utforskning av designutrymme inklusive formella beräkningsmodeller och tidsförutsägbara plattformar. Det senare används ofta för hårda realtidssystem. För att göra en plattform tidsförutsägbar måste alla komponenter, såväl som kommunikation mellan kärnor, ha de värsta tänkbara exekveringstiden (WCET) uppskattningar och vara lätta att analysera. Time-division multiplexing (TDM)-nätverk kan exakt allokera nätverksresurser vid varje tidpunkt och ytterligare ge tidsförutsägbara garantier. Applikationsutvecklaren måste dock ta sig tid att förstå hårdvaran och kapaciteten hos ett nätverk-på-chip (NoC) för att kunna kommunicera mellan kärnorna. Dessutom ökar ett brett utbud av kommunikationsbibliotek som tillhör olika plattformar inlärningskostnaden. Message Passing Interface (MPI)-standarden inspirerar detta projekt. För tidsförutsägbar kommunikation på TDM-baserade MPSoC:er bör en specifikation med kommunikationsprimitiver också vara nödvändig för antingen systemdesigners eller applikationsutvecklare. Jämfört med MPI-standarden borde denna specifikation vara lättare eftersom den bara utvecklar tidsförutsägbar kommunikation. Dessutom är plattformar som den gäller begränsade till realtids-NoCs som använder TDM, som den värsta kommunikationstiden (WCCT) skulle kunna beräknas i ett tidigt skede av designen. I detta projekt har vi abstraherat från samtidighets- och kommunikationsbibliotek för befintliga plattformar och härledda kommunikationsprimitiver till denna specifikation. Två olika kommunikationslägen, push-baserade och interaktiva, sammanfattas. Pushbaserad kommunikation består av att kontrollera DMA-statusen (Direct Memory Access), skicka meddelandet och kontrollera mottagningsbufferten. Interaktiv kommunikation innefattar att skicka, ta emot och bekräfta primitiver, som är uppdelade i blockerande och icke-blockerande. Dessutom tillåter denna specifikation användaren att beräkna WCCT för att sända ett meddelande från en processor till en annan om man känner till storleken på skickade meddelanden och hårdvarukonfigurationen genom att lägga till WCET för alla kommunikationsoperationer som körs på en enda processor och latens för kommunikationsanslutningen tillsammans . Beräkningsprocessen visas med en befintlig plattform.