Τις τελευταίες δεκαετίες, η ανάπτυξη των non-volatile μνημών (NVMs) κατέστησε ικανή την αντικατάσταση volatile μνημών, όπως των DRAMs και των μαγνητικών σκληρών δίσκων (HDDs), σε caching και storage εφαρμογές, αντίστοιχα. Οι δίσκοι στερεάς κατάστασης (SSDs) που βασίζονται σε NAND Flash μνήμες έχουν ήδη αναδειχθεί ως ένα χαμηλού κόστους, υψηλής απόδοσης και αξιόπιστο μέσο στα σύγχρονα συστήματα αποθήκευσης. Επιπλέον, οι ιδιότητες των υλικών αλλαγής φάσης και η πρόσφατη κλιμάκωση της Phase-Change μνήμης (PCM), την καθιστά ένα τέλειο υποψήφιο για την ανάπτυξη μνημών τυχαίας προσπέλασης αλλαγής φάσης (PCRAMs). Η ραγδαία κλιμάκωση των NVMs, με διαδικασίες ολοκλήρωσης κάτω από 19nm, και η χρήση της multi-level cell (MLC) τεχνολογίας συνέβαλλαν στην αύξηση της πυκνότητας αποθήκευσης πληροφορίας και συνεπώς μείωσαν το κόστος αποθήκευσης δραματικά. Ωστόσο, η διάρκεια ζωής των NV μνημών δεν παρέμεινε ανεπηρέαστη. Διαφορετικές παρεμβολές και πηγές θορύβου σε συνδυασμό με την επίδραση της γήρανσης έχουν ένα μεγάλο αντίκτυπο στην αξιοπιστία και την αντοχή αυτών των τεχνολογιών μνήμης, και ως εκ τούτου, των συστημάτων αποθήκευσης στα οποία χρησιμοποιούνται (SSDs, PCRAMs). Πολλές μέθοδοι και τεχνικές, όπως η μέθοδος wear-leveling, εξειδικευμένοι κώδικες ανίχνευσης και διόρθωσης λαθών (ECC) και τεχνικές pre-coding έχουν χρησιμοποιηθεί για να αντισταθμίσουν αυτές τις επιπτώσεις, ενώ άλλες, πιο περίπλοκες μεν, αλλά και πιο αποτελεσματικές, όπως η δυναμική προσαρμογή των κατωφλίων ανάγνωσης, βρίσκονται σε πειραματικό στάδιο. Η ανάπτυξη αυτών των τεχνικών βασίζεται στον πειραματικό χαρακτηρισμό των NV μνημών, τόσο σε επίπεδο κελιού όσο και σε επίπεδο ολοκληρωμένου κυκλώματος. Ο χαρακτηρισμός αυτός σχετίζεται με την μέτρηση του λόγου του αριθμού των bit σφαλμάτων προς τον αριθμό των συνολικών bits (BER) και το χρόνο απόκρισης (ανάγνωσης και εγγραφής) καθ' όλη τη διάρκεια ζωής της μνήμης, για διάφορες μορφές δεδομένων και σενάρια χρονισμών. Η διαδικασία αυτή, μέχρι τώρα, γίνεται με τη χρήση της πραγματικής NV μνήμης, συνήθως με ολοκληρωμένα κυκλώματα που βρίσκονται στο στάδιο της προ-παραγωγής, ενώ πιο ενδελεχής έλεγχος γίνεται στο τελικό στάδιο της παραγωγής. Αυτή η προσέγγιση έχει δύο σημαντικά μειονεκτήματα. Από τη μία πλευρά, είναι μια πολύ χρονοβόρα διαδικασία, δεδομένου ότι η γήρανση μίας NVM μπορεί να απαιτεί ένα μεγάλο αριθμό από program / erase (P/E) κύκλους που πρέπει να εκτελεστούν για κάθε πείραμα. Ο αριθμός αυτός κυμαίνεται από κάποιες δεκάδες χιλιάδες (NAND Flash) έως και κάποια εκατομμύρια κύκλους (PCM). Από την άλλη πλευρά, τα χαρακτηριστικά γήρανσης μίας NVM είναι αναλόγως εξαρτώμενα από τον αριθμό των Ρ/Ε κύκλων που εκτελούνται, καθιστώντας έτσι αδύνατη την διεξαγωγή διαφορετικών ή διαδοχικών πειραμάτων στην ίδια κατάσταση γήρανσης της μνήμης. Σε αυτή την εργασία παρουσιάζουμε ένα μοντέλο που αντιπροσωπεύει με ακρίβεια τη διαδικασία γήρανσης NV μνημών, αντιμετωπίζοντας τες ως ένα χρονικά μεταβαλλόμενο κανάλι επικοινωνίας βασισμένο σε ένα μη συμμετρικό n-PAM μοντέλο. Με βάση τη μοντελοποίηση των χαρακτηριστικών γήρανσης, υλοποιούμε ένα σύστημα εξομοίωσης σε πραγματικό χρόνο και με μεγάλη ακρίβεια της συμπεριφοράς NV-μνημών, κάτω από ορισμένες από το χρήστη συνθήκες γήρανσης, σε τεχνολογία FPGA. Η πλατφόρμα που παρουσιάζεται στην παρούσα εργασία βασίζεται σε μια αναπροσαρμόσιμη αρχιτεκτονική υλικού και λογισμικού που επιτρέπει την ακριβή εξομοίωση των νέων και αναδυόμενων τεχνολογιών και μοντέλων των NVMs. Η πλατφόρμα που αναπτύχθηκε μπορεί να αποτελέσει ένα πολύτιμο εργαλείο για την ανάπτυξη και αξιολόγηση αλγορίθμων και τεχνικών κωδικοποίησης. / Over the last few years, non-volatle memory (NVM) has shown a great potential in replacing volatile memory, like DRAM in caching applications, and magnetic HDDs in storage applications. NAND Flash-based solid state drives (SSDs) have already emerged as a low-cost, high-performance and reliable storage medium for both commercial and enterprise storage systems. Additionally, the properties of phase-change materials and the recent scaling of Phase-Change Memory (PCM) has made it a perfect candidate for developing phase-change random access memories (PCRAMs). The rapid scaling of NVMs, with process nodes below 19nm, and the use of multi-level cell (MLC) technologies has increased their storage density and reduced the storage cost per bit. However, their lifetime capacity has not remained unaffected. Different interferences and noise sources along with aging effects have now a great impact on the reliability and endurance of these memory technologies, and hence, on the storage systems where these memories are used (SSDs, PCRAMs). Numerous techniques, such as wear-leveling, specialized error correcting codes (ECC) and precoding techniques have been employed to compensate these effects, while others, more complex but also more efficient, like dynamic adaptation of read reference thresholds, are at an experimental level. The development of these techniques is based on experimental characterization of NVM cells and chips. Characterization is related with measuring bit error ratio (BER) and response time (read and write time) during the whole lifetime of a device, for various loading data patterns and timing scenarios. This process is performed using real NVM integrated chips, usually the engineering, pre-production parts, while more thorough testing at the system level is performed when production parts are available. This approach has two major drawbacks. On one hand it is a very time-consuming process, since the aging of an NVM may require a large number of program/erase (P/E) cycles to be performed for each experiment, ranging from tens of thousands (NAND Flash) to millions (PCM) program cycles. On the other hand, the aging characteristics of an NVM are proportionally dependent on the number of the performed P/E cycles, thus making it impossible to conduct different or successive experiments at the same aging state of a memory chip. In this work, we present a model that accurately represents the aging process of an NVM cell, by treating it as a time-variant communications channel, based on an asymmetric n-PAM model. We present the architecture of a flexible FPGA-based platform, designed for accurate emulations of NVM technologies, focusing mainly on MLC NAND Flash technologies. Accuracy is measured in reference to experimentally specified bit error probabilities for various aging conditions (ie. the number of P/E cycles applied to a NAND Flash chip), usually for random data patterns. The hardware platform presented in this work is based on a reconfigurable hardware-software architecture, which enables the accurate emulation of new and emerging models and technologies of NVMs. The developed platform can be a valuable tool for the evaluation of memory-related algorithms, signal processing and coding techniques.

The simplest combinational logic circuits are made by inverting the output of a fundamental logic gate. Despite this simplicity, these gates are vital. In fact, we can realize any truth table using a circuit made only from AND gates with inverted outputs.

The NAND gate outputs a logic zero only when all its inputs equal logic one. Let’s explore how this universal gate can be used to implement any Boolean expression.

Un nouveau moteur de recherche embarqué conçu pour les objets intelligents. Ces dispositifs sont généralement équipés d'extrêmement de faible quantité de RAM et une grande capacité de stockage Flash NANAD. Pour faire face à ces contraintes matérielles contradictoires, les moteurs de recherche classique privilégient soit la scalabilité en insertion ou la scalabilité en requête, et ne peut pas répondre à ces deux exigences en même temps. En outre, très peu de solutions prennent en charge les suppressions de documents et mises à jour dans ce contexte. nous avons introduit trois principes de conception, à savoir y Write-Once Partitioning, Linear Pipelining and Background Linear Merging, et montrent comment ils peuvent être combinés pour produire un moteur de recherche intégré concilier un niveau élevé d'insertion / de suppression / et des mises à jour. Nous avons mis en place notre moteur de recherche sur une Board de développement ayant un représentant de configuration matérielle pour les objets intelligents et avons mené de vastes expériences en utilisant deux ensembles de données représentatives. Le dispositif expérimental résultats démontrent la scalabilité de l'approche et sa supériorité par rapport à l'état des procédés de l'art. / A new embedded search engine designed for smart objects. Such devices are generally equipped with extremely low RAM and large Flash storage capacity. To tackle these conflicting hardware constraints, conventional search engines privilege either insertion or query scalability but cannot meet both requirements at the same time. Moreover, very few solutions support document deletions and updates in this context. we introduce three design principles, namely Write-Once Partitioning, Linear Pipelining and Background Linear Merging, and show how they can be combined to produce an embedded search engine reconciling high insert/delete/update rate and query scalability. We have implemented our search engine on a development board having a hardware configuration representative for smart objects and have conducted extensive experiments using two representative datasets. The experimental results demonstrate the scalability of the approach and its superiority compared to state of the art methods.

Maitriser et optimiser les performances et la consommation énergétique dans les systèmes embarqués est aujourd'hui crucial. Pour ce faire, des techniques d'estimation de ces métriques sont utilisées dans des environnements où la réalisation de mesures est difficile. Ce travail cible l'évaluation des performances et de la consommation énergétique du service du stockage secondaire dans un système d'exploitation embarqué utilisant une mémoire flash NAND. L'un des moyens de gérer ce type de média est l'utilisation de systèmes de fichiers dédiés (Flash File Systems, FFS), pour lequel on peut constater un manque de travaux dans la littérature concernant les techniques d'estimation des performances et de la consommation. Les contributions apportées dans cette thèse s'articulent autour d'une méthodologie de modélisation pour l'estimation des performances et de la consommation des systèmes de stockage embarqués de type FFS. Cette méthodologie est divisée en trois phases. En phase d'exploration on identifie, via des micro-benchmarks, les éléments du système de stockage impactant les performances et la consommation du système embarqué. En phase de modélisation, cet impact est représenté sous la forme de modèles de différents types, dont les principaux sont les modèles fonctionnels, de performances et de consommation. Les paramètres de ces modèles sont extraits via des mesures. En phase de simulation, les modèles sont implémenté dans un simulateur, développé dans le cadre de cette thèse, permettant d'obtenir des estimations concernant les performances et la consommation d'un système de stockage à base de mémoire flash soumis à une charge d'entrées / sorties donnée. / Controlling and optimizing embedded system performance and power consumption is critical. In this context, estimation techniques are used when performing measurement campaigns is difficult due to time or financial constraints. This work targets the performance and power consumption evaluation of the secondary storage service in an embedded operating system using NAND flash memory. One way to manage flash memory is to used dedicated Flash File Systems (FFS). One can observe a lack of work in the literature concerning FFS performance and power consumption estimation techniques.The contributions presented in this thesis rely on a three steps performance and power consumption modeling methodology. During the exploration phase, we identify through micro-benchmarking the main elements of a FFS based system impacting performance and power consumption of the embedded system. In the modeling phase, this impact is represented by building models of various types. The main models types are the functional, performance and power consumption models. Models parameters are extracted through measurements on a real platform. During the simulation phase the models are implemented in a simulator. This tool allows obtaining performance and power consumption estimations concerning a flash-based storage system processing a given I/O workload.

This master's thesis deals with designing and implementation of universal programmer with JTAG interface. The project consists of a hardware and software part. Theoretical part discusses actual state in using the standards for programming and testing electronic devices, with special emphasis on JTAG implementation. Next part deals with programming ARM and FPGA devices through JTAG. The programming of this devices using available software is described in the practical part of this document. Final product of this work is the programmer itself. The programmer consists of the hardware and supplement software. At the end of this thesis there is a conclusion about possible improvements and development in the future.

The research that stems from my doctoral dissertation focuses on addressing essential challenges in developing techniques that utilize solid-state memory technologies (with emphasis on NAND flash memory) from device, circuit, architecture, and system perspectives in order to exploit their true potential for improving I/O performance in high-performance computing systems. These challenges include not only the performance quirks arising from the physical nature of NAND flash memory, e.g., the inability to modify data in-place, read/write performance asymmetry, and slow and constrained erase functionality, but also the reliability drawbacks that limits solid state drives (SSDs) from widely deployed. To address these challenges, I have proposed, analyzed, and evaluated the I/O scheduling schemes, strategies for storage space virtualization, and data protection methods, to boost the performance and reliability of SSDs.

No description available.

Flash Memories have been widely used as a storage media in electronic devices such as USB flash drives, mobile phones and cameras. Flash Memory offers a portable and non-volatile de- sign, which can be carried to everywhere without data loss. It is durable against temperature and humidity. With all these advantages, Flash Memory gets popular day by day. However, Flash Memory has also some disadvantages, such as erase-before restriction and erase limi- tation of each individual block. Erase-before restriction pushes every single writable unit to be erased before an update operation. Another limitation is that every block can be erased up to a fixed number. Flash Translation Layer - FTL is the solution for these disadvantages. Flash Translation Layer is a software module inside the Flash Memory working between the operating system and the memory. FTL tries to reduce these disadvantages of Flash Memory via implementing garbage collector, address mapping scheme, error correcting and many oth- ers. There are various Flash Translation Layer software. Some of them have been reviewed in terms of their advantages and disadvantages. The study aims at designing, implementing and simulating a NAND type FTL algorithm.

Dy-incorporated HfO₂ gate oxide with TaN gate electrode nMOS device has been developed for high performance CMOS applications in 22nm node technology. DyO /HfO bi-layer structure shows thin EOT with reduced leakage current and less charge trapping compared to HfO₂. Excellent electrical performance of the DyO-capped HfO₂ oxide n-MOSFET such as lower V[subscript TH], higher drive current, and improved channel electron mobility are reported. DyO/HfO samples also show better immunity for V[subscript TH] instability and less severe charge trapping characteristics. Its charge trapping characteristics, conduction mechanisms and dielectric reliability have been investigated in this work. As an application to memory device, HfON charge trapping layered NAND flash memory is developed and characterized. First, temperature-dependent Dy diffusion and the diffusion-driven Dy dipole formation process are discussed to clarify the origin of V[subscript TH] shift, and eventually modulate the effective work function in Dy-Hf-O/SiO₂ system. The Dy-induced dipoles are closely related to the Dy-silicate formation at the high-k/SiO₂ interfaces since the V[subscript FB] shift in Dy₂O₃ is caused by the dipole and coincides with the Dy-silicate formation. Dipole formation is a thermally activated process, and more dipoles are formed at a higher temperature with a given Dy content. The Dy-silicate related bonding structure at the interface is associated with the strength of the Dy dipole moment, and becomes dominant in controlling the V[subscript FB]/V[scubscript TH] shift during high temperature annealing in the Dy- Hf-O/SiO₂ gate oxide system. Dy-induced dipole reduces the degradation of the electron mobility. Second, to understand the reduced leakage current of the DyO/HfO sample, the effective barrier height of Dy₂O₃ was calculated from FN tunneling models, and the band diagram was estimated. The higher effective barrier height of Dy₂O₃, which is around 2.32 eV calculated from the F-N plot, accounts for the reduced leakage current in Dy incorporated HfO₂ nMOS devices. The lower barrier height of HfO₂ result in increased electron tunneling currents enhanced by the buildup of hole charges trapped in the oxide, which causes a severe increase of stress-induced leakage current (SILC), leading to oxide breakdown. However, the increased barrier height in Dy incorporated HfO₂ inhibits a further increase of the electron tunneling from the TaN gate, and trapped holes lessen the hole tunneling currents, resulting in a negligible SILC. The lower trap generation rate by the reduced hole trap density and the reduced hole tunneling of the Dy-doped HfO₂ dielectric demonstrates the high dielectric breakdown strength by weakening the charge trapping and defect generation during the stress. Based on these fundamental studies of the dielectric breakdown, modeling of time-dependent dielectric breakdown (TDDB) was done. The intrinsic TDDB of the Dy-doped HfO₂ gate oxide having 1 nm EOT is characterized by the progressive breakdown (PBD) model. At high temperature, the PBD becomes severe, since thermal energy causes carrier hopping between the localized weak spots. The voltage acceleration factor derived from the power law shows a realistic prediction in comparison with those from the 1/E model. The increase of the voltage acceleration factor at lower stress voltage is due to the lower trap generation rate in Dy- incorporated HfO₂. This voltage acceleration factor can be easily extended to include temperature dependency, and the effective activation energy derived from the power law is voltage dependent. Lastly, I studied the device characteristics of thin HfON charge-trap layer nonvolatile memory in a TaN/Al₂O₃/HfON/SiO₂/p-Si (TANOS) structure. A large memory window and fast erase speed, as well as good retention time, were achieved by using the NH₃ nitridation technique to incorporate nitrogen into the thin HfO₂ layer, which causes a high electron-trap density in the HfON layer. The higher dielectric constant of the HfON charge-trap layer induces a higher electric field in the tunneling oxide at the same voltage compared to non-nitrided films and, thus, creates a high Fowler-Nordheim (FN) tunneling current to increase the erase and programming speed. The trap-level energy in the HfON layer was calculated by using an amphoteric model. / text