The operating characteristics of non-volatile memory for modern requirement are high-density , low power consumption, fast read and write speed, and good reliability. The floating gate memory generated leakage path in the tunnel oxide during the trend of scaling down, which will result in the loss of all stored charge to the silicon substrate. As the data retention time and endurance are taken into consideration, the thickness of tunnel oxide exist a physical limit, owing to the demand of high-density capacities. RRAM is offered as an option in the next generation non-volatile memories, due to the following advantages: (1) simple structure and easy to process, and low cost ; (2) less restrictive in the scaling-down process; (3) with the multi-bit data storage features; (4) high speed operation; (5) Repeat write and read is more than one million. In the thesis, we use a simple and low-temperature process to form the silicon germanium oxide (Si-Ge-O) RRAM and silicon germanium oxide RRAM with nitrogen doping between the electrode and silicon-germanium oxide interface. By sputtering at argon and oxygen (Ar/O2), and sputtering at argon and ammonia (Ar/NH3) with silicon-germanium target to form silicon germanium oxide RRAM and silicon germanium oxide (Si-Ge-O)/silicon germanium oxnitride (Si-Ge-O-N) RRAM. By informing a SiGeON layer between the interface of electrode and silicon-germanium oxide improve the stability of write voltage and endurance reliability. In addition, both silicon and germanium are useful as materials in the optoelectronics industry and extensively studied in material science. Based on the two materials, the smiting characterizations of RRAM will be improved in the read-write stability and operation reliability.

Τις τελευταίες δεκαετίες, η ανάπτυξη των non-volatile μνημών (NVMs) κατέστησε ικανή την αντικατάσταση volatile μνημών, όπως των DRAMs και των μαγνητικών σκληρών δίσκων (HDDs), σε caching και storage εφαρμογές, αντίστοιχα. Οι δίσκοι στερεάς κατάστασης (SSDs) που βασίζονται σε NAND Flash μνήμες έχουν ήδη αναδειχθεί ως ένα χαμηλού κόστους, υψηλής απόδοσης και αξιόπιστο μέσο στα σύγχρονα συστήματα αποθήκευσης. Επιπλέον, οι ιδιότητες των υλικών αλλαγής φάσης και η πρόσφατη κλιμάκωση της Phase-Change μνήμης (PCM), την καθιστά ένα τέλειο υποψήφιο για την ανάπτυξη μνημών τυχαίας προσπέλασης αλλαγής φάσης (PCRAMs). Η ραγδαία κλιμάκωση των NVMs, με διαδικασίες ολοκλήρωσης κάτω από 19nm, και η χρήση της multi-level cell (MLC) τεχνολογίας συνέβαλλαν στην αύξηση της πυκνότητας αποθήκευσης πληροφορίας και συνεπώς μείωσαν το κόστος αποθήκευσης δραματικά. Ωστόσο, η διάρκεια ζωής των NV μνημών δεν παρέμεινε ανεπηρέαστη. Διαφορετικές παρεμβολές και πηγές θορύβου σε συνδυασμό με την επίδραση της γήρανσης έχουν ένα μεγάλο αντίκτυπο στην αξιοπιστία και την αντοχή αυτών των τεχνολογιών μνήμης, και ως εκ τούτου, των συστημάτων αποθήκευσης στα οποία χρησιμοποιούνται (SSDs, PCRAMs). Πολλές μέθοδοι και τεχνικές, όπως η μέθοδος wear-leveling, εξειδικευμένοι κώδικες ανίχνευσης και διόρθωσης λαθών (ECC) και τεχνικές pre-coding έχουν χρησιμοποιηθεί για να αντισταθμίσουν αυτές τις επιπτώσεις, ενώ άλλες, πιο περίπλοκες μεν, αλλά και πιο αποτελεσματικές, όπως η δυναμική προσαρμογή των κατωφλίων ανάγνωσης, βρίσκονται σε πειραματικό στάδιο. Η ανάπτυξη αυτών των τεχνικών βασίζεται στον πειραματικό χαρακτηρισμό των NV μνημών, τόσο σε επίπεδο κελιού όσο και σε επίπεδο ολοκληρωμένου κυκλώματος. Ο χαρακτηρισμός αυτός σχετίζεται με την μέτρηση του λόγου του αριθμού των bit σφαλμάτων προς τον αριθμό των συνολικών bits (BER) και το χρόνο απόκρισης (ανάγνωσης και εγγραφής) καθ' όλη τη διάρκεια ζωής της μνήμης, για διάφορες μορφές δεδομένων και σενάρια χρονισμών. Η διαδικασία αυτή, μέχρι τώρα, γίνεται με τη χρήση της πραγματικής NV μνήμης, συνήθως με ολοκληρωμένα κυκλώματα που βρίσκονται στο στάδιο της προ-παραγωγής, ενώ πιο ενδελεχής έλεγχος γίνεται στο τελικό στάδιο της παραγωγής. Αυτή η προσέγγιση έχει δύο σημαντικά μειονεκτήματα. Από τη μία πλευρά, είναι μια πολύ χρονοβόρα διαδικασία, δεδομένου ότι η γήρανση μίας NVM μπορεί να απαιτεί ένα μεγάλο αριθμό από program / erase (P/E) κύκλους που πρέπει να εκτελεστούν για κάθε πείραμα. Ο αριθμός αυτός κυμαίνεται από κάποιες δεκάδες χιλιάδες (NAND Flash) έως και κάποια εκατομμύρια κύκλους (PCM). Από την άλλη πλευρά, τα χαρακτηριστικά γήρανσης μίας NVM είναι αναλόγως εξαρτώμενα από τον αριθμό των Ρ/Ε κύκλων που εκτελούνται, καθιστώντας έτσι αδύνατη την διεξαγωγή διαφορετικών ή διαδοχικών πειραμάτων στην ίδια κατάσταση γήρανσης της μνήμης. Σε αυτή την εργασία παρουσιάζουμε ένα μοντέλο που αντιπροσωπεύει με ακρίβεια τη διαδικασία γήρανσης NV μνημών, αντιμετωπίζοντας τες ως ένα χρονικά μεταβαλλόμενο κανάλι επικοινωνίας βασισμένο σε ένα μη συμμετρικό n-PAM μοντέλο. Με βάση τη μοντελοποίηση των χαρακτηριστικών γήρανσης, υλοποιούμε ένα σύστημα εξομοίωσης σε πραγματικό χρόνο και με μεγάλη ακρίβεια της συμπεριφοράς NV-μνημών, κάτω από ορισμένες από το χρήστη συνθήκες γήρανσης, σε τεχνολογία FPGA. Η πλατφόρμα που παρουσιάζεται στην παρούσα εργασία βασίζεται σε μια αναπροσαρμόσιμη αρχιτεκτονική υλικού και λογισμικού που επιτρέπει την ακριβή εξομοίωση των νέων και αναδυόμενων τεχνολογιών και μοντέλων των NVMs. Η πλατφόρμα που αναπτύχθηκε μπορεί να αποτελέσει ένα πολύτιμο εργαλείο για την ανάπτυξη και αξιολόγηση αλγορίθμων και τεχνικών κωδικοποίησης. / Over the last few years, non-volatle memory (NVM) has shown a great potential in replacing volatile memory, like DRAM in caching applications, and magnetic HDDs in storage applications. NAND Flash-based solid state drives (SSDs) have already emerged as a low-cost, high-performance and reliable storage medium for both commercial and enterprise storage systems. Additionally, the properties of phase-change materials and the recent scaling of Phase-Change Memory (PCM) has made it a perfect candidate for developing phase-change random access memories (PCRAMs). The rapid scaling of NVMs, with process nodes below 19nm, and the use of multi-level cell (MLC) technologies has increased their storage density and reduced the storage cost per bit. However, their lifetime capacity has not remained unaffected. Different interferences and noise sources along with aging effects have now a great impact on the reliability and endurance of these memory technologies, and hence, on the storage systems where these memories are used (SSDs, PCRAMs). Numerous techniques, such as wear-leveling, specialized error correcting codes (ECC) and precoding techniques have been employed to compensate these effects, while others, more complex but also more efficient, like dynamic adaptation of read reference thresholds, are at an experimental level. The development of these techniques is based on experimental characterization of NVM cells and chips. Characterization is related with measuring bit error ratio (BER) and response time (read and write time) during the whole lifetime of a device, for various loading data patterns and timing scenarios. This process is performed using real NVM integrated chips, usually the engineering, pre-production parts, while more thorough testing at the system level is performed when production parts are available. This approach has two major drawbacks. On one hand it is a very time-consuming process, since the aging of an NVM may require a large number of program/erase (P/E) cycles to be performed for each experiment, ranging from tens of thousands (NAND Flash) to millions (PCM) program cycles. On the other hand, the aging characteristics of an NVM are proportionally dependent on the number of the performed P/E cycles, thus making it impossible to conduct different or successive experiments at the same aging state of a memory chip. In this work, we present a model that accurately represents the aging process of an NVM cell, by treating it as a time-variant communications channel, based on an asymmetric n-PAM model. We present the architecture of a flexible FPGA-based platform, designed for accurate emulations of NVM technologies, focusing mainly on MLC NAND Flash technologies. Accuracy is measured in reference to experimentally specified bit error probabilities for various aging conditions (ie. the number of P/E cycles applied to a NAND Flash chip), usually for random data patterns. The hardware platform presented in this work is based on a reconfigurable hardware-software architecture, which enables the accurate emulation of new and emerging models and technologies of NVMs. The developed platform can be a valuable tool for the evaluation of memory-related algorithms, signal processing and coding techniques.

Nowadays, researchers are trying to shrink the memory cell in order to increase the capacity of the memory system and reduce the hardware costs. In recent years, there has been a revolution in electronics by using fundamentals of physics to build a new memory for computer application in order to increase the capacity and decrease the power consumption. Increasing the capacity of the memory causes a growth in the chip area. From 1971 to 2012 semiconductor manufacturing process improved from 6µm to 22 µm. In May 2008, S.Williams stated that "it is time to stop shrinking". In his paper, he declared that the process of shrinking memory element has recently become very slow and it is time to use another alternative in order to create memory elements [9]. In this project, we present a new design of a memory array using the new element named Memristor [3]. Memristor is a two-terminal passive electrical element that relates the charge and magnetic flux to each other. The device remained unknown since 1971 when it was discovered by Chua and introduced as the fourth fundamental passive element like capacitor, inductor and resistor [3]. Memristor has a dynamic resistance and it can retain its previous value even after disconnecting the power supply. Due to this interesting behavior of the Memristor, it can be a good replacement for all of the Non-Volatile Memories (NVMs) in the near future. Combination of this newly introduced element with the nanowire crossbar architecture would be a great structure which is called Crossbar Memristor. Some frameworks have recently been introduced in literature that utilized Memristor crossbar array, but there are many challenges to implement the Memristor crossbar array due to fabrication and device limitations. In this work, we proposed a simple design of Memristor crossbar array architecture which uses input feedback in order to preserve its data after each read operation

Indiana University-Purdue University Indianapolis (IUPUI) / Thermal constraints and the quantum limit will soon put a boundary on the scale of new micro and nano magnetoelectronic devices. This necessitates a push into the limits of harnessable natural phenomena to facilitate a post-Moore’s era of design. Requirements for thermodynamic stability at room temperature, fast (Ghz) switching, and low energy cost narrow the list of candidates. Here we show voltage controllable, room temperature, stable locking of the spin state, and the corresponding conductivity change, when molecular spin crossover thin films are deposited on a ferroelectric substrate. This opens the door to the creation of a non-volatile, room temperature, molecular multiferroic gated voltage controlled device.

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No description available.

Non-volatile main memory (NVM) technologies are revolutionizing the entire computing stack thanks to their storage-and-memory-like characteristics. The ability to persist data in memory provides a new opportunity to build crash-consistent software without paying a storage stack I/O overhead. A crash-consistent NVM program can recover back to a consistent state from a persistent NVM in the event of a software crash or a sudden power loss. In the presence of a volatile cache, data held in a volatile cache is lost after a crash. So NVM programming requires users to manually control the durability and the persistence ordering of NVM writes. To avoid performance overhead, developers have devised customized persistence mechanisms to enforce proper persistence ordering and atomicity guarantees, rendering NVM programs error-prone. The problem statement of this dissertation is how one can effectively detect persistence bugs from NVM programs. However, detecting persistence bugs in NVM programs is challenging because of the huge test space and the manual consistency validation required. The thesis of this dissertation is that we can detect persistence bugs from NVM programs in a scalable and automatic manner by inferring likely-correctness conditions from programs. A likely-correctness condition is a possible correctness condition, which is a condition a program must maintain to make the program crash-consistent. This dissertation proposes to infer two forms of likely-correctness conditions from NVM programs to detect persistence bugs. The first proposed solution is to infer likely-ordering and likely-atomicity conditions by analyzing program dependencies among NVM accesses. The second proposed solution is to infer likely-linearization points to understand a program's operation-level behavior. Using these two forms of likely-correctness conditions, we test only those NVM states and thread interleavings that violate the likely-correctness conditions. This significantly re- duces the test space required to examine. We then leverage the durable linearizability model to validate consistency automatically without manual consistency validation. In this way, we can detect persistence bugs from NVM programs in a scalable and automatic manner. In total, we detect 47 (36 new) persistence correctness bugs and 158 (113 new) persistence performance bugs from 20 single-threaded NVM programs. Additionally, we detect 27 (15 new) persistence correctness bugs from 12 multi-threaded NVM data structures. / Doctor of Philosophy / Non-volatile main memory (NVM) technologies provide a new opportunity to build crash-consistent software without incurring a storage stack I/O overhead. A crash-consistent NVM program can recover back to a consistent state from a persistent NVM in the event of a software crash or a sudden power loss. NVM has been and will further be used in various computing services integral to our daily life, ranging from data centers to high-performance computing, machine learning, and banking. Building correct and efficient crash-consistent NVM software is therefore crucial. However, developing a correct and efficient crash-consistent NVM program is challenging as developers are now responsible for manually controlling cacheline evictions in NVM programming. Controlling cacheline evictions makes NVM programming error-prone, and detecting persistence bugs that lead to inconsistent NVM states in NVM programs is an arduous task. The thesis of this dissertation is that we can detect persistence bugs from NVM programs in a scalable and automatic manner by inferring likely-correctness conditions from programs. This dissertation proposes to infer two forms of likely-correctness conditions from NVM programs to detect persistence bugs, i.e., likely-ordering/atomicity conditions and likely-linearization points. In total, we detect 47 (36 new) persistence correctness bugs and 158 (113 new) persistence performance bugs from 20 single-threaded NVM programs. Additionally, we detect 27 (15 new) persistence correctness bugs from 12 multi-threaded NVM data structures.

In an effort to lower interconnect time delays and power dissipation in highly integrated logic and memory nanoelectronic products, numerous changes in the materials and processes utilized to fabricate the interconnect have been made in the past decade. Chief among these changes has been the replacement of aluminum (Al) by copper (Cu) as the interconnect metal and the replacement of silicon dioxide (SiO2) by so called low dielectric constant (low-k) materials as the insulating interlayer dielectric (ILD). Cu/low-k structure significantly decreases the RC delay compared with the traditional interconnect (Al/SiO₂). Therefore, the implementation of low-k dielectric in Cu interconnect structures has become one of the key subjects in the microelectronics industry. Incorporation of pores into the existing low-k dielectric is a favorable approach to achieve ultra low-k ILD materials. To bring memory and logic closer together is an effective approach to remove the latency constraints in metal interconnects. The resistive random access memories (RRAM) technology can be integrated into a complementary metal-oxide-semiconductor (CMOS) metal interconnect structure using standard processes employed in back-end-of-line (BEOL) interconnect fabrication. Based on this premise, the study of this thesis aims at assessing a possible co-integration of resistive switching (RS) cells with current BEOL technology. In particular, the issue is whether RS can be realized with porous dielectrics, and if so, what is the electrical characterization of porous low-k/Cu interconnect-RS devices with varying percentages of porosity, and the diffusive and drift transport mechanism of Cu across the porous dielectric under high electric fields. This work addresses following three areas: 1. Suitability of porous dielectrics for resistive switching memory cells. The porous dielectrics of various porosity levels have been supplied for this work by Intel Inc. In course of the study, it has been found that Cu diffusion and Cu+ ion drift in porous materials can be significantly different from the corresponding properties in non-porous materials with the same material matrix. 2. Suitability of ruthenium as an inert electrode in resistive switching memory cells. Current state-of-the-art thin Cobalt (Co)/Tantalum Nitride (TaN) bilayer liner with physical vapor deposited (PVD) Cu-seed layer has been implemented for BEOL Cu/low-k interconnects. TaN is used for the barrier and Co is used to form the liner as well as promoting continuity for the Cu seed. Also, the feasibility of depositing thin CVD ruthenium (Ru) liners in BEOL metallization schemes has been evaluated. For this study, Ru is used as a liner instead of Ta or Co in BEOL interconnects to demonstrate whether it can be a potential candidate for replacing PVD-based TaN/Ta(Co)/Cu low-k technology. In this context, it is of interest to investigate how Ru would perform in well-characterized RS cell, like Cu/TaOx/Ru, given the fact that Cu/TaOx/Pt device have been proven to be good CBRAM device due to its excellent unipolar and bipolar switching characteristics, device performance, retention, reliability. If Cu/TaOx/Ru device displays satisfactory resistive switching behavior, Cu/porous low-k dielectric/Ru structure could be an excellent candidate as resistive switching memory above the logic circuits in the CMOS back-end. 3. Potential of so-called covalent dielectric materials for BEOL deployment and possibly as dielectric layer in the resistive switching cells. The BEOL reliability is tied to time dependent failure that occurs inside dielectric between metal lines. Assessing the suitability of covalent dielectrics for back-end metallization is therefore an interesting topic. TDDB measurements have been performed on pure covalent materials, low-k dielectric MIM and MI-semiconductor (MIS) devices supplied by Intel Inc. / Master of Science / While the scaling of conventional memories based on floating gate MOSFETs is getting increasingly difficult, novel types of non-volatile memories, such as resistive-switching memories, have recently been of interest to both industry and academia. Resistive switching memory is being considered for next-generation non-volatile memory due to relatively high switching speed, high scalability, low power consumption, good retention and simple structure. Additionally, these twoterminal devices operate by changing resistance from high resistance OFF-state (HRS) to low resistance ON-state (LRS) in response to applied voltage or current due to the formation and rupture of a conductive filament. In particular, Conductive Bridging Random Access Memory (CBRAM), also referred as Programmable Metallization Cell (PMC), is a promising candidate for a resistive memory device due to its highly scalable and low-cost technology. Currently, the interconnect RC scaling methods have reached their limits and there is an urgent need for alternative ways to reduce or remove the latency constraints in CMOS low-k/Cu interconnect. One method is building CBRAM directly into a low-k/Cu interconnects to reduce the latency in connectivity constrained computational devices and the chip’s footprint by stacking memory on top of logic circuits. This is possible since the Cu metal lines and low-k/Cu interconnect already prefigure a potential RS device. This work addresses three areas: Firstly, the suitability of porous dielectrics for resistive switching memory cells. Secondly, the suitability of ruthenium as an inert electrode in resistive switching memory cells. If Ru resistive memory device displays satisfactory resistive switching behavior, Cu/porous low-k dielectric/Ru structure could be an excellent candidate as resistive switching memory above the logic circuits in the CMOS back-end-of-line (BEOL). Thirdly, the potential of so-called covalent dielectric materials for BEOL deployment and possibly as dielectric layer in the resistive switching cells.

In this dissertation, we present a number of studies that primarily focus on data movement challenges among different types of memories (viz., 3D-DRAM, DDRx DRAM and NVM) employed together as a flat-address heterogeneous memory system. We introduce two different hardware-based techniques for prefetching data from slow off-chip phase change memory (PCM) to fast on-chip memories. The prefetching techniques efficiently fetch data from PCM and place that data into processor-resident or 3D-DRAM-resident buffers without putting high demand on bandwidth and provide significant performance improvements. Next, we explore different page migration techniques for flat-address memory systems which differ in when to migrate pages (i.e., periodically or instantaneously) and how to manage the migrations (i.e., OS-based or hardware-based approach). In the first page migration study, we present several epoch-based page migration policies for different organizations of flat-address memories consisting of two (2-level) and three (3-level) types of memory modules. These policies have resulted in significant energy savings. In the next page migration study, we devise an efficient "on-the-fly'" page migration technique which migrates a page from slow PCM to fast 3D-DRAM whenever it receives a certain number of memory accesses without waiting for any specific time interval. Furthermore, we present a light-weight hardware-assisted address reconciliation process for address management of the migrated pages. Such an on-the-fly page migration with hardware-assisted address reconciliation technique provides significant performance improvement over systems using epoch-based page migration and OS-based address management. Finally, we have developed an analytical model, which employs offline analyses of memory access counts per page and recommends whether an application is migration friendly or not. This can be useful in deciding if page migration (either epoch-based or on-the-fly based) should be used or turned off for a given application. Thus, our data management techniques and model enable significant performance improvements for flat-address heterogeneous memory systems involving NVMs.

The pace at which data and information transfer and storage has shifted from PCs to mobile devices is of great concern to the digital forensics community. Android is fast becoming the operating system of choice for these hand-held devices, hence the need to develop better forensic techniques for data recovery cannot be over-emphasized. This thesis analyzes the volatile memory for Motorola Android devices with a shift from traditional physical memory extraction to carving residues of data on a “per process basis”. Each Android application runs in a separate process within its own Dalvik Virtual Machine (JVM) instance, thus, the proposed “per process basis” approach. To extract messages, we first extract the runtime memory of the MotoBlur application, then carve and reconstruct both deleted and undeleted messages (emails and chat messages). An experimental study covering two Android phones is also presented.