In this thesis, the traditional fixed-point CORDIC algorithm is extended to floating-point version in order to calculate transcendental functions (such as sine/cosine, logarithm, powering function, etc.) with high accuracy and large range. Based on different algorithm derivations, two different floating-point high-throughput pipelined CORDIC architectures are proposed. The first architecture adopts barrel shifters to implement the shift operations in each pipelined stage. The second architecture uses pure hardwired method for the shifting operations. Another key contribution of this thesis is to analyze the execution errors in the floating-point CORDIC architectures and make comparison with the execution resulting from pure software programs. Finally, the thesis applies the floating-point CORDIC to realizing the rotation-related operations required in 3D graphics applications.

With the portable computing devices and wireless communication systems are popularly used, the power consumption became one of the major targets of VLSI design. However, multiplier is always a fundamental component and influences the power consumption and performance much in many DSP and multimedia applications. Therefore, multiplier is the crucial design and need to be concerned at first. In these systems, the data width of input data is various because the different applications are operated in the same system. According to this characteristic of input data, this paper presents architecture of reconfigurable multiplier without the necessity to completely reconfigure the internal layout of a programmable device. The multiplier employs the Booth algorithm which reduces the partial products to half to implement the sign multiplication. In order to reduce power consumption, the proposed multiplier introduces the clock gating technique to disable the circuit which does not need to be computed. Moreover, the energy-efficient multiplier presented in this thesis can perform multiplication with different data widths to further decrease power dissipation and enhance performance. In this work, we proposed two versions of multipliers. The first version is reconfigurable pipelined Booth multiplier, which can perform one n by n multiplication or two n/2 by n/2 multiplications concurrently. When the multiplier performs n-bit multiplication, it can reduce power consumption by disabling the unnecessary blocks according to the input data. The second version further deploys the truncated functionality to provide different way to make multiplication more energy-efficient. Experiment shows that the proposed multipliers can perform multiplication with less energy and lower power dissipation. It is certain that the more functions the design provides, the more area it will cost.

Low-power and small size analog to digital converters (ADCs) are the strategic building blocks in state of the art mobile wireless communication systems. Various techniques have been developed to reduce both power consumption and die area of the ADC. Among these, the opamp-sharing technique shows the most promise. In opamp-sharing, power and die area are saved by sharing one opamp between two successive pipeline stages. However, this technique suffers from the well-known memory effect drawback due to the absence of the reset phase that discharges the opamp's input parasitics. In this dissertation, this drawback is solved by introducing a discharge phase before the opamp is used for the pipeline stages without compromising speed and resolution of the ADC. Further power and area reduction is achieved by using a capacitor-sharing technique. This technique reduces the effective load capacitance of the opamp by reusing the charge on the feedback capacitor for the MDAC operation of the following stage, resulting in faster settling without increasing opamp power. The proposed low input-capacitance variable-gm opamp also helps to reduce the memory effect and improves the settling behavior of the stage output by increasing the bandwidth of the opamp while input parasitics of the opamp are kept small. The prototype designs of a 10-bit 50MSample/s pipelined ADC and a 14-bit 100MSample/s pipelined ADC implemented in 0.18¹m CMOS technology demonstrate the effectiveness of the proposed techniques. The first ADC achieves 56.2dB SNDR and 72.7dB SFDR for a Nyquist input at full sampling rate while consuming 12 mW from a 1.8-V supply. The FOM, defined as, [power/2[superscript ENOB].Fs], is 0.46 pJ/step with Fin = 24.5MHz at 50MS/s. The second ADC achieves 72.4dB SNR and 88.5dB SFDR at 100MS/s with a 46MHz input and consumes 230mW from a 3V supply. The FOM of the second ADC is 0.69 pJ/step with Fin = 46MHz at 100MS/s.

The semiconductor industry has seen a paradigm shift from Application Specific Integrated Circuits to Multiprocessor System on Chip systems over the last decade, primarily due to the miniaturization of the transistor. However, billion of transistors available on a single chip need to be used efficiently to provide more functionalities in portable devices, yet minimize power and chip area, which increases the design complexity of multiprocessor systems. Tighter time to market deadlines further pressurizes the designer, requiring a comprehensive automation of the design process of such complex multiprocessor systems. This thesis presents a design automation methodology for the design of Multiprocessor System on Chip (MPSoC) systems for multimedia applications. This thesis introduces a heterogeneous multiprocessor system where processing elements are connected in a pipelined fashion. A multimedia application is executed very efficiently on a pipelined system due to the stream oriented data flow nature of such applications. Application Specific Instruction set Processors (ASIPs) are used as the elementary processing elements in the multiprocessor system as they can be customized according to the application tasks assigned to them. The problem of selecting a processor configuration for each of the ASIPs in the pipelined system is formalized. We present three different techniques to select processor configurations by exploring the design space of an ASIP based pipelined system, and integrating them into a flexible and designer driven design flow for efficient exploration of large design spaces in order of 10^16 design points. The first two techniques are based on Integer Linear Programming (ILP), named Exact ILP formulation (EIF) and Reduced ILP formulation (RIF), while the third technique is based on a novel heuristic. We also developed a design space pruning algorithm that can enable the use of EIF and RIF to obtain optimal or near optimal design points from large design spaces. For four multimedia applications, we show that RIF and the heuristic can explore the design space and reveal the Pareto front in several hours, while EIF took several days to obtain the Pareto front. The quick availability of the Pareto front of a design space will help the designer to make early changes in the design. Furthermore, it is shown that, on average, the error incurred by RIF and the heuristic is within 1.25% and 2.25% of the optimal design points obtained via EIF for all the four multimedia applications. In the worst case, RIF introduced an error of 17.08% while the heuristic had an error of 11.39%.

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<p>This thesis is funded by the IBM Center for Advanced Studies</p> / <p>A large number of scientific applications rely on the computing of logarithm. Thus, accelerating the speed of computing logarithms is significant and necessary. To this end, we present the realization of a pipelined Logarithm Computation Unit (LCU) in hardware that uses lookup table and interpolation techniques. The presented LCU supports single precision arithmetic with fixed accuracy and speed. We estimate that it can generate 2.9G single precision values per second under a 65nm fabrication process. In addition, the accuracy is at least 21 bits while lookup table size is about 7.776KB. To the best of our knowledge, our LCU achieves the fastest speed at its current accuracy and table size.</p> / Master of Science (MSc)

In this document, I explore the problem of scheduling pipelined applications onto large-scale distributed platforms, in order to optimize several criteria. A particular attention is given to throughput maximization (i.e., the number of data sets that can be processed every time unit), latency minimization (i.e., the time required to process one data set entirely), and failure probability minimization. First, I accurately define the models and the scheduling problems, and exhibit surprising results, such as the difficulty to compute the optimal throughput and/or latency that can be obtained given a mapping. In particular, I detail the importance of the communication models, which induce quite different levels of difficulty. Second, I give an overview of complexity results for various cases, both for mono-criterion and for bi-criteria optimization problems. I illustrate the impact of the models on the problem complexity. Finally, I show some extensions of this work to different applicative contexts and to dynamic platforms.

<p>An analog-to-digital converter (ADC) is a link between the analog and digital domains and plays a vital role in modern mixed signal processing systems. There are several architectures, for example flash ADCs, pipeline ADCs, sigma delta ADCs,successive approximation (SAR) ADCs and time interleaved ADCs. Among the various architectures, the pipeline ADC offers a favorable trade-off between speed,power consumption, resolution, and design effort. The commonly used applications of pipeline ADCs include high quality video systems, radio base stations,Ethernet, cable modems and high performance digital communication systems.Unfortunately, static errors like comparators offset errors, capacitors mismatch errors and gain errors degrade the performance of the pipeline ADC. Hence, there is need for accuracy enhancement techniques. The conventional way to overcome these mentioned errors is to calibrate the pipeline ADC after fabrication, the so-called post fabrication calibration techniques. But environmental changes like temperature and device aging necessitates the recalibration after regular intervals of time, resulting in a loss of time and money. A lot of effort can be saved if the digital outputs of the pipeline ADC can be used for the estimation and correctionof these errors, further classified as foreground and background techniques. In this thesis work, an algorithm is proposed that can estimate 10% inter stage gain errors in pipeline ADC without any need for a special calibration signal. The efficiency of the proposed algorithm is investigated on an 8-bit pipeline ADC architecture.The first seven stages are implemented using the 1.5-bit/stage architecture whilethe last stage is a one-bit flash ADC. The ADC and error correction algorithms simulated in Matlab and the signal to noise and distortion ratio (SNDR) is calculated to evaluate its efficiency.</p>

Thesis (M.S.)--Oregon State University, 2007. / Printout. Includes bibliographical references (leaves 82-86). Also available on the World Wide Web.