This study investigated the Class F and inverse Class F RF power amplifier operating at 5.8 GHz. The major challenging issue in design and implementation of CMOS power transistor is the breakdown voltage especially in sub-micron CMOS technologies. In order to eliminate this problem a Cascode topologies were implemented to reduce the Drain-toSource voltage (stress). A Cascode Class F & Inverse Class F RF power amplifier were designed, and optimized in order to improve efficiency and reliability using 0.18µm CMOS technology process. A 50% decrease in the stress has been achieved in the Cascode class-F and Inverse class F amplifiers. The sensitivity and temperature effect were investigated using BSIM-4 model. Such an amplifier was designed and optimized for a good sensitivity. A substrate bias circuit was implemented to achieve a good sensitivity. Recommendations were made for future advancements for modification and optimization of the class F and inverse class F circuit by the application of other stress reduction strategies, and improvement of the substrate bias circuit for a better sensitivity.

Today, ESD is a major consideration in the design and manufacture of ICs. ESD problems are increasing in the electronics industry because of the increasing trend toward higher speed and smaller device sizes. There is growing interest in knowing the effects of ESD protection circuit on the performance of semiconductor integrated circuits (ICs) because of the impact it has on core RF circuit performance. This study investigated the impact of ESD protection circuit on RF Power amplifiers. Even though ESD protection for digital circuits has been known for a while, RF-ESD is a challenge. From a thorough literature search on prior art ESD protection circuits, Silicon controlled rectifier was found to be most effective and reliable ESD protection for power amplifier circuit. A SCR based ESD protection was used to protect the power amplifier and a model was developed to gain better understanding of ESD protected power amplifiers. Simulated results were compared and contrasted against theoretically derived equations. A 5.2GHz fully ESD protected Class AB power amplifier was designed and simulated using TSMC 0.18 um technology. Further, the ESD protection circuit was added to a cascoded Class-E power amplifier operating at 5.2 GHz. ADS simulation results were used to analyze the PA’s RF performance degradation. Various optimization techniques were used to improve the RF circuit performance.

Yes / This work integrates a harmonic tuning mechanism in synergy with the GaN HEMT transistor for 5G mobile transceiver applications. Following a theoretical study on the operational behavior of the Class-F power amplifier (PA), a complete amplifier design procedure is described that includes the proposed Harmonic Control Circuits for the second and third harmonics and optimum loading conditions for phase shifting of the drain current and voltage waveforms. The performance improvement provided by the Class-F configuration is validated by comparing the experimental and simulated results. The designed 10W Class-F PA prototype provides a measured peak drain efficiency of 64.7% at 1dB compression point of the PA at 3.6GHz frequency.

Modern wireless communication systems use spectrally efficient modulation schemes to reach high data rate transmission. These schemes are generally involved with signals with high peak-to-average power ratio (PAPR). Moreover, the development of next generation wireless communication systems requires the power amplifiers to operate over a wide frequency band or multiple frequency bands to support different applications. These wide-band and multi-band solutions will lead to reductions in both the size and cost of the whole system. This dissertation presents several advanced power amplifier solutions to provide wide-band and multi-band operations with efficiency improvement at power back-offs.

No description available.

In retrospect we can see that from the last century, wireless electronic technology has been in a rapid state of development. With the popularity of wireless communication, the power amplifier demand is rising. In general, magnitude, maximum noise figure, minimum noise figure, efficiency, and output power are important indicators of the amplifier. The IC industry is exploring how to reduce the additional cost and improve the high-frequency performance. Therefore, designing a strong adaptability and high cost performance of the PA has become a priority. As these technologies advance, the power amplifiers need to have better integration, lower cost, and lower power dissipation. Also, some special requirements are being asked in some areas, such as multi-mode and multi-band. In general, people have to use several power amplifiers parallel to frame a multifunction chip. Each of them working at different frequencies of interest has to have separate matching network, design, and area; also, the diversity amplifier prices will increase with the number of amplifiers, and its cost is also changed. In this thesis, because Class E power amplifier has lower power dissipation, 100% ideal efficiency, simple circuit structure, and strong applicability, the Class E is used as power amplifier in main stage. Moreover, in order to decrease input power and increase output power, the class A power amplifier is used as driver stage. It can use very small amount of power to provide a larger power. Moreover, we use a switched variable inductor and capacitor to constitute a dual band matching network which can let the PA work at more than one frequency. In fact, we design a Class A PA which is as a driver stage. Then, when we support 1 dBm input power, the driver stage can have 8 dBm output power. Also the output will be the input power for the main stage. When the Class E PA get 8dBm input power, it will export a 15dBm output power. Because the dual band matching network, the PA can work at 2.2 GHz and 2.6 GHz; also, the efficiency is 48% and 51%, and the both gains are 13 dB. In the future, in order to further improve the performance of the power amplifier and better multi-frequencies, more new designs with new structures should be investigated. Moreover, we need further research about design theory. In fact multi-frequencies power amplifier has a great potential in real application. It based on its special structure and design parameters.

Widely used design techniques for radio frequency power amplifiers yield results which are approximate; the initial design is usually refined by applying trial-and-error procedures in the laboratory. More accurate design techniques are complicated in their application and have not gained acceptance by practicing engineers. A new design technique for VHF linear power amplifiers using bipolar junction transistors is presented in this report. This design technique is simple in its application but yields accurate results. The design technique is based upon a transistor model which is simple enough to be useful for design, but which is sufficiently accurate to predict performance at high frequencies. Additionally, the model yields insight into many of the processes which take place within the typical RF power transistor. The fundamental aspect of the model is the inclusion of charge storage within the transistor base. This charge storage effect gives rise to a nearly sinusoidal collector current waveform, even in a transistor which ostensibly is biased for class B or nonsaturating class C operation. Methods of predicting transistor input and output impedances are presented. A number of other topics related to power amplifier measurement and design are also included. A unique measurement approach which is ideally suited for use with power amplifiers is discussed. This measurement approach is a hybrid of the common S-parameter measurement technique and the "load-pull" procedure. Practical considerations such as amplifier stability, bias network design, and matching network topology are also included in the report. / Ph. D.

Many communications signal formats are not power efficient because of their large peak-to-average power ratios (PARs). Moreover, in the presence of nonlinear devices such as power amplifiers (PAs) or mixers, the non-constant-modulus signals may generate both in-band distortion and out-of-band interference. Backing off the signal to the linear region of the device further reduces the system power efficiency. To improve the power efficiency of the communication system, one can pursue two approaches: i) linearize the PA; ii) reduce the high PAR of the input signal. In this dissertation, we first explore the optimal nonlinearity under the peak power constraint. We show that the optimal nonlinearity is a soft limiter with a specific gain calculated based on the peak power limit, noise variance, and the probability density function of the input amplitude. The result is also extended to the fading channel case. Next, we focus on digital baseband predistortion linearization for power amplifiers with memory effects. We build a high-speed wireless test-bed and carry out digital baseband predistortion linearization experiments. To implement adaptive PA linearization in wireless handsets, we propose an adaptive digital predistortion linearization architecture that utilizes existing components of the wireless transceiver to fulfill the adaptive predistorter training functionality. We then investigate the topic of PAR reduction for OFDM signals and forward link CDMA signals. To reduce the PAR of the OFDM signal, we propose a dynamic selected mapping (DSLM) algorithm with a two-buffer structure to reduce the computational requirement of the SLM method without sacrificing the PAR reduction capability. To reduce the PAR of the forward link CDMA signal, we propose a new PAR reduction algorithm by introducing a relative offset between the in-phase branch and the quadrature branch of the transmission system.

Software Defined Radios (SDRs) and Cognitive Radios (CRs) pave the way for next-generation radio technology. They promise versatility, flexibility and cognition which can revolutionize communications systems. However they present greater challenges to the design of radio frequency (RF) front-ends. RF front-ends for the radios in use today are narrow-band in their frequency response and are optimized and tuned to the carrier frequency of interest. SDRs and CRs demand front-ends which are versatile, configurable, tunable and be capable of transmitting and receiving signals with different bandwidths and modulation schemes. Integrating power amplifiers (PAs) with transmitters in CMOS has many advantages and challenges. This thesis deals with the design of an RF transmitter front-end for SDRs and CRs in CMOS. The thesis begins with an introduction to SDRs and the requirements they place on transmitters and the challenges involved in designing them in CMOS. After a brief overview of the existing techniques, the proposed architecture is presented and explained. A digitally intensive transmitter solution is proposed. The transmitter covers a wide frequency range of 750 MHz to 2.5 GHz. The inputs to the proposed transmitter are in-phase and quadrature (I & Q) data bit streams. Multiple stages of up-sampling and filtering are used to remove all spurs in the spectrum such that only the harmonics of the carrier remain. Differential rail-to-rail quadrature clocks are generated from a continuous wave signal at twice the carrier frequency. The clocks are corrected for their duty cycle and quadrature impairments. The heart of the transmitter is an integrated reconfigurable CMOS power amplifier (PA). A methodology to design reconfigurable Class E PAs with a series fixed inductor has been presented. A CMOS power amplifier that can span a wide frequency range with sufficient output power and efficiency, supporting varying envelope complex modulation signals, with good linearity has been designed. Digital pre-distortion (DPD) is used to linearize the PA. The full transmitter and the clock correction blocks have been designed and fabricated in a commercial 130-nm CMOS process and experimentally characterized. The PA delivers a maximum power of 13 dBm with an efficiency of 27% at 1 GHz. While transmitting a 16-QAM signal at 1 GHz, the measured EVM is 4%. It delivers a maximum power of around 11-13 dBm from 750 MHz to 1.5 GHz and up to 6.5 dBm of power till 2.5 GHz. Comparing the proposed system with recently published literature, it can be seen that the proposed design is one of the very few transmitters which has an integrated matching network, tunable across the frequency range. The proposed PA produces the highest output power and with largest efficiency for systems with on-chip output networks.

The incorporation of Gallium Nitride (GaN) Power Amplifiers (PAs) into future high power aperture radar systems is certain; however, the introduction of this technology into multifunction radar systems will present new challenges to radar engineers. This dissertation describes a broad investigation into amplitude and phase transients produced by GaN PAs when they are excited with multifunction radar waveforms. These transients are the result of self-heating electrothermal memory effects and are manifested as interpulse instabilities that can negatively impact the coherent processing of multiple pulses. A behavioral model based on a Foster network topology has been developed to replicate the measured amplitude and phase transients accurately. This model has been used to develop a digital predistortion technique that successfully mitigates the impact of the transients. The Moving Target Indicator (MTI) Improvement Factor and the Root Mean Square (RMS) Pulse-to-Pulse Stability are used as metrics to assess the impact of the transients on radar system performance and to test the effectiveness of a novel digital predistortion concept. / Ph. D.