The pursuit for higher performance at a lower cost is driving rapid progress in the field of packaged digital systems. As the complexity of interconnects and packages increases, and the rise and fall time of the signal decreases, the electromagnetic effects in distributed passive structures become an important factor in determining the system performance. Hence there is a need to accurately simulate these parasitic electromagnetic effects that are observed in the signal distribution network (SDN) and the power delivery network (PDN) of an electronic system. The accurate simulation of high-speed systems requires information on the high frequency transient currents that are injected into the power distribution network causing simultaneous switching noise. Existing techniques for determining these transient currents are not sufficiently accurate. Furthermore existing transient simulation techniques suffer from two major drawbacks: 1) they are not scalable and hence cannot be applied to large sized systems, and 2) the time domain simulations violate causality. This dissertation addresses the above-mentioned problems in the domain of high-speed packaging. It proposes a new technique to accurately extract the transient switching noise currents in high-speed digital systems. The extracted switching noise currents can be used in both the frequency domain and the time domain to accurately simulate simultaneous switching noise. The dissertation also proposes a methodology for the transient co-simulation of the SDN and the PDN in high-speed digital systems. The methodology enforces causality on the transient simulation and can be scaled to perform large sized simulations. The validity of the proposed techniques has been demonstrated by their application on a variety of real-world test cases.

Due to recent aggressive process scaling into the nanometer regime, power delivery network design faces many challenges that set more stringent and specific requirements to the EDA tools. For example, from the perspective of analysis, simulation efficiency for large grids must be improved and the entire network with off-chip models and nonlinear devices should be able to be analyzed. Gated power delivery networks have multiple on/off operating conditions that need to be fully verified against the design requirements. Good power delivery network designs not only have to save the wiring resources for signal routing, but also need to have the optimal parameters assigned to various system components such as decaps, voltage regulators and converters. This dissertation presents new methodologies to address these challenging problems. At first, a novel parallel partitioning-based approach which provides a flexible network partitioning scheme using locality is proposed for power grid static analysis. In addition, a fast CPU-GPU combined analysis engine that adopts a boundary-relaxation method to encompass several simulation strategies is developed to simulate power delivery networks with off-chip models and active circuits. These two proposed analysis approaches can achieve scalable simulation runtime. Then, for gated power delivery networks, the challenge brought by the large verification space is addressed by developing a strategy that efficiently identifies a number of candidates for the worst-case operating condition. The computation complexity is reduced from O(2^N) to O(N). At last, motivated by a proposed two-level hierarchical optimization, this dissertation presents a novel locality-driven partitioning scheme to facilitate divide-and-conquer-based scalable wire sizing for large power delivery networks. Simultaneous sizing of multiple partitions is allowed which leads to substantial runtime improvement. Moreover, the electric interactions between active regulators/converters and passive networks and their influences on key system design specifications are analyzed comprehensively. With the derived design insights, the system-level co-design of a complete power delivery network is facilitated by an automatic optimization flow. Results show significant performance enhancement brought by the co-design.

With electronic devices trending toward higher clock rates, lower voltage levels, and smaller form factors, the simultaneously switching noise (SSN), which is induced in package and printed circuit board, is one of the major factors affecting the performance and design of the high speed digital circuits. This noise will lead to false switching and malfunctioning in digital and/or analog circuits, and causes serious signal integrity (SI) and electromagnetic interference (EMI) problems for the high speed digital systems. Therefore, mitigating the SSN becomes a major challenge for the high speed circuits design. In this thesis, first of all, we introduce and discuss previously proposed solutions to suppress the SSN. These solutions include the use of decoupling capacitors, isolation moats, and electromagnetic bnadgap (EBG) structures. We analyzed the EBG structures and generated some EBG design rules. As the speed of digital circuits moving toward higher frequencies, the Double L-bridge EBG structure can be used to improve the performance of Hybrid EBG structure by employing the EBG design rules that were generated. The Double L-bridge EBG structure design improved the behavior at the high frequencies, which also maintained the low frequency performance. It is demonstrated numerically and experimentally. For fast estimating the stopband, we use one-dimensional lump circuit model. Then, we propose another structure, named Double Cross EBG structure. This design, compared to the Double L-bridge EBG structure, not only maintained the high frequency performance, but also improved the low frequency behavior. It is also both experimentally and numerically validated.

Effective power delivery in Double-sided 3-D glass interposer packages was proposed, investigated, and demonstrated towards achieving high logic-to-memory bandwidth. Such 3-D interposers enable a simpler alternative to direct 3-D stacking by providing low-loss, wide-I/O channels between the logic device on one side of the ultra-thin glass interposer and memory stack on the other side, eliminating the need for complex TSVs in the logic die. A simplified PDN design approach with power-ground planes was proposed to overcome resonance challenges from (a) added parasitic inductance in the lateral power delivery path from the printed wiring board (PWB), due to die placement on the bottom side of the interposer, and (b) the low-loss property of the glass substrate. Based on this approach, this dissertation developed three important suppression solutions using, (a) the 3-D interposer package configuration, (b) the selection of embedded and SMT-based decoupling capacitors, and (c) coaxial power-ground planes with TPVs. The self-impedance of the 3-D glass interposer PDN was simulated using electromagnetic solvers, including printed-wiring-board (PWB) and chip-level models. Two-metal and four-metal layer test vehicles were fabricated on 30-μm and 100-μm thick glass substrates using a panel-based double-side fabrication process, for potential lower cost and improved electrical performance. The PDN test structures were characterized upto 20 GHz, to demonstrate the measured verification of (a) 3-D glass interposer power delivery network and (b) resonance suppression. The data and analysis presented in this dissertation prove that the objectives of this research were met successfully, leading to the first demonstration of effective PDN design in ultra-thin (30-100μm), and 3-D double-sided glass BGA packages, by suppressing the PDN noise from mode resonances.

Distributed on-chip voltage regulation where multiple voltage regulators are distributed among different locations of the chip demonstrates advantages as compared to on-chip voltage regulation utilizing a single voltage regulator. Better on-chip voltage noise performance and faster transient response can be realized due to localized voltage regulation. Despite the advantages of distributed on-chip voltage regulation, unbalanced current sharing issue can occur among each voltage regulator, which has been demonstrated to deteriorate power conversion efficiency, stability, and reliability of the power delivery network. An effective balanced current sharing scheme that can be applied to most voltage regulator types is proposed to balance the current sharing. Furthermore, a relatively high on-chip temperature induced by increased power density leads to prominent voltage regulator performance degradations due to aging. The emerging type of digital low-dropout regulator is investigated regarding aging induced transient and steady state performance degradations. Reliability enhancement techniques for digital low-dropout regulators are developed and verified. Such techniques introduce negligible power and area overhead and do not affect the normal operations of digital low-dropout regulators. Reliability enhancement techniques also reduce the area overhead needed to mitigate aging induced performance degradations. Area overhead saving further translates into more space for increased number of distributed on-chip voltage regulators, enabling scalable on-chip voltage regulation.

In conventional design of power delivery networks (PDNs), the PDN impedance is required to be less than the target impedance over the frequency range of interest to minimize the IR drop and to suppress the inductive noise during data transitions. As a result, most PDNs in high-speed systems consist of power and ground planes to provide a low-impedance path between the voltage regulator module (VRM) and the integrated circuit (IC) on the printed circuit board (PCB). For off-chip signaling, charging and discharging signal transmission lines induce return currents on the power and ground planes. The return current always follows the path of least impedance on the reference plane closest to the signal transmission line. The return current path plays a critical role in maintaining the signal integrity of the bits propagating on the signal transmission lines. The problem is that the disruption between the power and ground planes induces return path discontinuities (RPDs), which create displacement current sources between the power and ground planes. The current sources excite the plane cavity and cause voltage fluctuations. These fluctuations are proportional to the plane impedance since the current is drawn through the PDN by the driver. Therefore, low PDN impedance is required for power supply noise reduction. Alternatively, methods of preventing RPDs can be used to suppress power supply noise. Using a power transmission line (PTL) eliminates the discontinuity between the power and ground planes, thereby preventing the RPD effects. In this approach, transmission lines replace the power plane for conveying power from the VRM to each IC on the PCB. The PTL-based PDN enables both power and signal transmission lines to be referenced to the same ground plane so that a continuous current path can be formed, unlike the power-plane-based PDN. As a result, a closed current loop is achieved, and the voltage fluctuation caused by RPDs is removed in idealistic situations. Without the RPD-related voltage fluctuation, reducing the PDN impedance is not as critical as in the power-plane-based approach. Instead, the impedance of the PTL is determined by the impedance of the signaling circuits. To use the PTL-based PDN in a practical signaling environment, several issues need to be solved. First, the dc drop coming from the source termination of the PTL needs to be addressed. The driver being turned on and off dictates the current flow through the PTL, causing the dc drop to be dynamic, which depends on the data pattern. Second, impedance mismatch between the PTL and termination can occur due to manufacturing variations. Third, an increase in the number of PCB traces should be addressed by devising a method to feed more than one driver with one PTL. Lastly, the power required to transmit 1 bit of data should be optimized for the PTL by using a new signaling scheme and adjusting the impedance of the signaling circuit. Constant flow of current through the PDN is one solution proposed to address the first two issues. Constant current removes the dynamic characteristics of the dc drop by inducing a fixed amount of dc drop over the PTL. Moreover, constant current keeps the PTL fully charged at all times, and thereby eliminates the process of repeatedly charging and discharging the power transmission line. The constant current PTL (CCPTL) scheme maintains constant current flow regardless of the input data pattern. Early results on the CCPTL scheme have been discussed along with the measurements. The CCPTL scheme severs the link between the current flowing through the PTL and the output data of the I/O driver connected to it. Also, it eliminates the charging and discharging process of the PTL, thereby completely eliminating power supply noise in idealistic situations. To reduce any associated power penalty, a pseudo-balanced PTL (PBPTL) scheme is also proposed using the PTL concept. A pseudo-balanced (PB) signaling scheme, which uses an encoding technique to map N-bit data onto M-bit encoded data with fixed number of 1s and 0s, is applied. When the PB signaling scheme is combined with the PTL, the jitter performance improves significantly as compared to currently practiced design approach.

Hybrid renewable energy system was introduced to improve the individual renewable energy power system’s productivity and operation-ability. This circumstance has led towards an extensive technological study and analysis on the hybrid renewable energy system. The extensive technological study is conducted using many different approaches, but in this research the linear programming, artificial intelligence and smart grid approaches are studied. This thesis proposed a complete hardware system development, implementation and construction of real-time DC Hybrid Renewable Energy System for solar-wind-battery energy source integrated with grid network support. The proposed real-time DC HRES hardware system adopts the hybrid renewable energy system concept which is composed of solar photovoltaic, wind energy system, battery energy storage system and grid network support. The real-time DC HRES hardware system research work is divided into three stages. Stage 1 involves modelling and simulation of the proposed system using MATLAB Simulink/Stateflow software. During this stage, system’s methodological design and development is emphasised. The obtained results are considered as fundamental finding to design, develop, integrate, implement and construct the real-time DC HRES hardware system. Stage II is designing and developing the electronic circuits for the real-time DC HRES hardware system using PROTEUS software. Real time simulation is performed on the electronic circuits to study and analyse the circuit’s behaviour. This stage also involves embedded software application development for the microcontroller PIC16F877A. Thus, continuous dynamic decision-making algorithm is developed and incorporated into microcontroller PIC16F877A. Next, electronic circuits and continuous dynamic decision-making algorithm are integrated with the microcontroller PIC16F877A as a real-time DC HRES hardware system to perform real time simulation. The real-time DC HRES hardware system simulation results are studied, analysed and compared with the results obtained in Stage 1. Any indifference between the obtained results in Stage 1 and Stage 2 are analysed and necessary changes are made. Stage 3 involves integrating, implementation and construction of real-time DC HRES. The continuous dynamic decision-making algorithm is also incorporated into the real microcontroller PCI16F877A development board. Real-time DC HRES’s experimental results have successfully demonstrated the system’s ability to perform supervision, coordination, management and control of all the available energy sources with lease dependency on the grid network. The obtained results demonstrated the energy management and optimisation of the available energy sources as primary power source deliver.

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Cílem této práce je navrhnout a sestavit napájecí zdroj pro notebooky různých výrobců pro použití v osobních a nákladních automobilech a na motocyklech s výstupním výkonem až 120W. Výsledný zdroj obsahuje USB-C konektor pro podporu napájení notebooků a chytrých zařízení s podporou Power Delivery, dále USB-A konektor s podporou Quick Charge 3.0 a také 12V automobilovou zásuvku pro možnost připojení dalšího automobilového příslušenství. Napájecí zdroj dále disponuje ochranou proti přepětí a přepólování vstupního napětí a také ochranou proti přetížení jednotlivých výstupů. Součástí zařízení je také LED displej, který uživateli umožňuje pomocí vstupního rozhraní jednoduše nastavit výstupní napětí pro notebook a sledovat aktuální hodnoty všech výstupů. Pro nastavování výstupu, indikaci a ochrany je použit mikrokontroler Arduino Nano.

The main objective of this dissertation is to explore and develop computer-aided-design methodologies and optimization techniques for reliability, performance, and power of through-silicon-via-based 3D IC designs. Through-silicon-via (TSV), a vertical interconnect element between dies, is the key enabling technology in 3D ICs. This new design element provides unprecedented design freedom as well as challenges. To maximize benefits and overcome challenges in TSV-based 3D ICs, new analysis methodologies and optimization techniques should be developed. In this dissertation, first, the robustness of 3D power delivery network is assessed under different power/ground TSV placement schemes and TSV RC variations. Next, thermo-mechanical stress and reliability problems are examined in full-chip/stack scale using the principle of linear superposition of stress tensors. Finally, physical design methods for low power 3D designs are explored to enhance the 3D power benefit over the 2D counterpart.