The objective of this dissertation is to develop electrical modeling and co-simulation methodologies for signal and power integrity of package and board applications. The dissertation includes 1) the application of the finite element method to the optimization for decoupling capacitor selection and placement on a power delivery network (PDN), 2) the development of a PDN modeling method effective for multidimensional and multilayer geometries, 3) the analysis and modeling of return path discontinuities (RPDs), and 4) the implementation of the absorbing boundary condition for PDN modeling. The optimization technique for selection and placement of decoupling capacitors uses a genetic algorithm (GA) and the multilayer finite element method (MFEM), a PDN modeling method using FEM. The GA is customized for the decoupling problem to enhance the convergence speed of the optimization. The mathematical modifications necessary for the incorporation of the capacitor model into MFEM is also presented. The main contribution of this dissertation is the development of a new modeling method, the multilayer triangular element method (MTEM), for power/ground planes of a PDN. MTEM creates a surface mesh on each plane-pair using dual graphs; a non-uniform triangular mesh (Delaunay triangulation) and its orthogonal counterpart (Voronoi diagram), to which electromagnetic and equivalent circuit concepts are applied. The non-uniform triangulation is especially efficient for discretizing multidimensional and irregular geometries which are common in package and board PDNs. Moreover, MTEM generates a sparse, banded, and symmetric system matrix, which enables efficient computations. For a given plane-pair, MTEM extracts an equivalent circuit that is consistent with the physics-based planar-circuit model of a plane-pair. Thus, the values of the lumped elements can be simply calculated from the physical parameters, such as material properties and mesh geometries of each unit-cell. Consequently, the modeling of MTEM is flexible and easy to modify for further extensions, such as the incorporation of external circuits, e.g. decoupling capacitors and vertical interconnects. Power and ground planes provide paths for the return current of signal traces. Typically, planes have discontinuities such as via holes, plane cutouts, and split planes that disturb flow of signal return currents. At the discontinuity, return currents have to detour or switch to different layers, causing signal and power integrity problems. Therefore, a separate analysis of signal interconnects will neglect the significant coupling with a PDN, and the result will not be reliable. In this dissertation, the co-simulation of the signal and power integrity is presented focusing on the modeling of RPDs created by split planes, apertures, and vias. Plane resonance is one of the main sources of power integrity problems in package and board PDNs. A number of techniques have been developed and published in literature to reduce or prevent the resonance of a plane-pair. One of the techniques is to surround plane-pair edges with absorbing material that effectively damps the outgoing parallel-plate wave and minimizes the reflection. To model this behavior, the boundary condition of MTEM needs to be changed from its original form, the open-circuit boundary condition. In this dissertation, the application of the 1st order absorbing boundary condition to MTEM is presented.

The objective of this dissertation is to derive a set of compact physical models addressing power integrity issues in high performance gigascale integration (GSI) systems and three-dimensional (3-D) systems. The aggressive scaling of CMOS integrated circuits makes the design of power distribution networks a serious challenge. This is because the supply current and clock frequency are increasing, which increases the power supply noise. The scaling of the supply voltage slowed down in recent years, but the logic on the integrated circuit (IC) still becomes more sensitive to any supply voltage change because of the decreasing clock cycle and therefore noise margin. Excessive power supply noise can lead to severe degradation of chip performance and even logic failure. Therefore, power supply noise modeling and power integrity validation are of great significance in GSI systems and 3-D systems. Compact physical models enable quick recognition of the power supply noise without doing dedicated simulations. In this dissertation, accurate and compact physical models for the power supply noise are derived for power hungry blocks, hot spots, 3-D chip stacks, and chip/package co-design. The impacts of noise on transmission line performance are also investigated using compact physical modeling schemes. The models can help designers gain sufficient physical insights into the complicated power delivery system and tradeoff various important chip and package design parameters during the early stages of design. The models are compared with commercial tools and display high accuracy.

Components used in mobile hand-held devices (smart phones and tablets) vary greatly in performance and power consumption. The microprocessors used in these devices also have vastly different capabilities and manufacturing limitations leading to significant variation effects. Battery life is a significant concern to the end users of these products. A stand-alone Android application capable of benchmarking a device's performance and power consumption is introduced. The application does not require the end user to have any analytic equipment or to have a technical background. This enables individual end users to better understand their particular device's performance and battery life interaction. They may also use the application to determine if their device's performance or battery life has degraded over time. Data is also uploaded to a central location so that devices can be compared against each other. The benchmarking application is capable of resolving variation effects caused by device, environmental changes and power management actions. This application demonstrates the feasibility of creating a low cost ecosystem where thousands of devices can be quantitatively compared. / text

High step-down dc/dc converters are widely adopted in a variety of areas such as industrial, automotive, and telecommunication. The 48 V power delivery system becomes increasingly popular for powering high-current and low-voltage chips. The Series-Capacitor Buck (SCB) converter doubles the duty ratio and equalizes the current between the two phases. Hard switching has hindered efforts to reduce volume via increased switching frequency, although a monolithically integrated SCB converter has boosted current density. A Series-Resonator Buck (SRB) converter is realized by adding a resonant tank in series with the series capacitor Cs. All switches turn on at zero-voltage (ZVOn), and the low-side switches turn off at zero-current (ZCOff). The design of the SRB converter includes characterizing the design variables' impacts on the converter performances and designing low-loss resonant components as the series resonator. The Series-Resonator Buck converter belongs to the class of quasi-resonant converters. Its resonant frequency is higher than the switching frequency, and its waveforms are quasi-sinusoidal. This work develops a steady-state model of the SRB converter to calculate voltage gain, component peak voltages, and resonant inductor peak current. Each switching cycle is modeled based on the concept of generalized state-space averaging. The soft-switching condition of the high-side switches is derived. The ZVS condition depends on the normalized control variable and the load condition. The gain equation models the load-dependent characteristic and the peak gain boundary. The theoretical peak voltage gain of the SRB converter is smaller than the maximum gain of the SCB converter. A smaller normalized load condition results in a larger peak voltage gain of the SRB converter. The large-signal model of the SRB converter characterizes the low-frequency behavior of the low-pass filters with the series capacitor and the high-frequency behavior of the resonant elements. A design recommendation of t_off f_r<0.5 is suggested to avoid the oscillation between the series capacitor Cs and the output inductors Lo. In other words, the off-duration of the low-side switches is less than half of 1/fr, and therefore the negative damping effect from the parallel resonant tank to the vCs response is reduced. The transfer functions of the SRB converter are presented and compared with those of the SCB converter. The series resonator brings in an extra damping effect to the response of output capacitor voltage. The understanding of the analytical relationships among the resonant tank energy, voltage gain, and component stresses was utilized to guide the converter design of the converter's parameters. A normalized load condition at √2 minimizes the stresses of the series resonator by balancing the peak energy in the resonant elements Lr and Cr. The f_s variation with voltage gain M is less than 10%. The non-resonant components C_s, L_oa, and L_ob are designed according to the specified switching ripples. The ac winding loss complicates the winding design of a resonant inductor. This work replaces the rectangular window with a rhombic window to reduce the eddy current loss caused by the fringing effect. The window ratio k_y is added as a design variable. The impacts of the design variables on the inductance, core loss, and winding loss are discussed. The air-gap length l_g is designed to control the inductance. A larger k_y design results in a short inductor length l_c and a smaller winding loss. The disadvantages include a smaller energy density design and a larger core loss due to the smaller cross-sectional area. In the design example presented in the thesis, the presence of the rhombic shape increases the gap-to-winding distance by two times, and also reduces the y-component of the magnetic field by a factor of two. The total inductor loss is reduced by 56% compared to a conventional design with a rectangular winding window while keeping the same inductance and the same inductor volume. This dissertation implements a resonator, replacing the series capacitor, in an SCB converter. The resultant SRB converter shows a 30% reduction in loss and a 50% increase in power density. The root cause of the divergence issue is identified by modeling the negative damping effect caused by resonant elements. The presented transient design guideline clears the barriers to closed-loop regulation and commercialization of the SRB converter. This work also reshapes winding windows from rectangle to rhombus which is a low-cost change that reduces magnetic loss by half. The theoretical analysis and design procedures are demonstrated in a 200 W prototype with 7% peak efficiency increase compared to the commonly used 30 W commercial SCB product. / Doctor of Philosophy / High step-down dc/dc converters are widely adopted in a variety of areas such as industrial, automotive, and telecommunication areas. The 48 V power delivery system becomes increasingly popular for powering high-current and low-voltage chips. The Series-Capacitor Buck (SCB) converter doubles the duty ratio and equalizes the current between the two phases. Hard switching has hindered efforts to reduce volume via increased switching frequency although a monolithically integrated SCB converter has boosted current density. A Series-Resonator Buck (SRB) converter is realized by adding a resonant tank in series with the series capacitor Cs. All switches turn on at zero-voltage (ZVOn), and the low-side switches turn off at zero-current (ZCOff). The challenges to designing the SRB converter include characterizing the design variables' impacts on the converter performances and designing low-loss resonant components as the series resonator. The resultant SRB converter shows a 30% reduction in loss and a 50% increase in power density. The root cause of the divergence issue is identified by modeling the negative damping effect caused by the resonant elements. The presented transient design guideline clears the barriers of closed-loop regulation and commercialization of the SRB converter. This work also reshapes winding windows from rectangle to rhombus, which is a low-cost change that reduces magnetic loss by half. The theoretical analysis and design procedures are demonstrated in a 200 W prototype with 7% peak efficiency increase compared to the commonly used 30 W commercial SCB product.