Orientador: Rodolfo Jardim de Azevedo / Dissertação (mestrado) - Universidade Estadual de Campinas, Instituto de Computação / Made available in DSpace on 2018-08-10T16:13:05Z (GMT). No. of bitstreams: 1 Ma_JosueTzanHsin_M.pdf: 3316745 bytes, checksum: c195170ef253c94333ce4727afeae31c (MD5) Previous issue date: 2007 / Resumo: A constante redução do tamanho e o conseqüente aumento do número de transistores em um mesmo chip faz com que a potência dissipada pelos circuitos digitais aumente exponencialmente. Esse fato, combinado com a crescente demanda por dispositivos portáteis, têm levado à uma crescente preocupação quanto ao consumo de energia. Quanto mais potência é dissipada mais calor é gerado e mais energia é gasta com o seu resfriamento. Como resultado, projetistas estão considerando cada vez mais o impacto de suas decisões nesse quesito. Atualmente, ADLs¹ têm sido utilizadas para projetar novos processadores. Essas linguagens descrevem o comportamento da arquitetura para cada ação ou instrução. ADLs, além de diminuirem o tempo de projeto, são úteis para descobrir problemas arquiteturais em um nível mais elevado. Nesse trabalho, foi desenvolvida uma ferramenta de estimativa de consumo de energia em nível de instrução utilizando-se como base a ADL ArchC e, como estudo de caso, um processador SPARCv8. Como resultado do uso da ferramenta desenvolvida, uma simulação de um programa com estimativa de consumo de energia pode ser realizada 100 vezes mais rápida, na média, em relação ao fluxo tradicional / Abstract: The constant reduction in size and consequential increase in number of transistors inside a chip causes an exponential growth in digital circuit power consumption. Combined with the growing demand for portable electronic devices, this has led to a rising concern about energy consumption. The more power is dissipated, the more heat is generated, and the more energy is spent in the cooling process. As a result, designers have been more and more considering the impact of their decisions on this matter. Currently, ADLs¹ are being used to design new processors. These languages describe the architectural behaviour for each action or instruction. Besides decreasing the time-to-market gap, ADLs are useful in discovering architectural problems at a higher level. This work presents an instruction leveI power estimation tool that uses ArchC ADL as a base, and a SPARCv8 processor as a case study. By using the developed tool, a simulation of a program with estimated power consumption can be accomplished 100 times faster, in average, than the traditional tools / Mestrado / Sistemas de Computação / Mestre em Ciência da Computação

Orientadores: Rodolfo Jardim de Azevedo, Guido Costa Souza de Araujo / Dissertação (mestrado) - Universidade Estadual de Campinas, Instituto de Computação / Made available in DSpace on 2018-08-05T00:43:06Z (GMT). No. of bitstreams: 1 Klein_FelipeVieira_M.pdf: 1314281 bytes, checksum: e347b1943f449e13f4f2d382ffd856be (MD5) Previous issue date: 2005 / Resumo: Com a constante redução do tamanho dos transistores e o conseqüente aumento do número de transistores em um mesmo chip, a potência dissipada pelos circuitos digitais está aumentando exponencialmente. As implicações do aumento de potência vão desde o aumento de custo advindo de soluções elaboradas para o resfriamento do chip e da limitação crítica do tempo de bateria até a própria destruição do chip. Por estes motivos, o projeto de circuitos digitais visando a redução do consumo de potência têm se tornado um fator cada vez mais importante no fluxo de projeto - o chamado low power design. Esta dissertação de mestrado apresenta a PowerSC, uma biblioteca que estende as capacidades de SystemC, dando suporte _a captura da atividade de transição de modelos em descrições de alto nível, em código C++. Além disso, propõe-se uma metodologia mais simples e transparente para o usuário, como uma alternativa à metodologia de uma ferramenta comercial. Outra contribuição deste trabalho é o algoritmo SMS, um algoritmo de monitoração eficiente, que consegue reduzir drasticamente o tempo de monitoração, com uma perda mínima de precisão. Os resultados experimentais obtidos mostram a factibilidade do uso de nossa abordagem para a captura efetiva da atividade de transição de modelos SystemC / Abstract: With the ever-shrinking size of the transistors and the consequent growth in the number of transistors per chip, the power dissipated by digital circuits is raising exponentially. There are several implications of the increasing of power consumption, ranging from the higher cost per chip, resulting from elaborated cooling and packaging solutions, and the critical limitation of the battery's lifetime to the circuit failure. Thus, the design of integrated circuits aiming at the reduction of the power consumption has become an important role in the design flow - the so-called low power design. This master thesis introduces the PowerSC, a library that extends the capabilities of SystemC, enabling the capture of the switching activity of high-level description models, coded in C++. Moreover, a simpler and transparent methodology is proposed, alternatively to a methodology of a commercial tool. Another contribution of this thesis is the SMS algorithm, an efficient monitoring algorithm, which can dramatically reduce the monitoring time, with a minimal loss of accuracy. The experimental results show the feasibility of the using of our approach to the effective capture of switching activity from SystemC models / Mestrado / Mestre em Ciência da Computação

As device technologies migrate into Deep Submicron (DSM) feature sizes, high-performance power-efficient computer architectures that keep pace with improving technologies need to be explored. Technology scaling increases the effects of wire latencies, inductive effects, noise and crosstalk in on-chip communication, limiting the performance of DSM designs. Power efficient performance gains from Instruction Level Parallelism (ILP) are reaching a limit. Single-Chip Parallel Computers are promising solutions to the DSM design challenges and the performance limitations of ILP. These systems are explicitly modular architectures that efficiently support Thread Level Parallelism (TLP) while avoiding global signals and shared resources. Microarchitectural level power analysis is required for evaluating the feasibility of newly conceived architectures in terms of power dissipation and energy efficiency. Accounting for power in the early stages of design shortens the time-to-market due to reduced design iteration times. Power optimizations at the architectural level can yield large power savings. This thesis proposes a microarchitectural level power estimation and analysis infrastructure for Single Chip Parallel Computers. The power estimation tool and the analysis methodology are developed based on the Single Chip Message-Passing Parallel (SCMP) Computer and can be extended to other Single Chip Parallel Computers. The thesis focuses on the development of power estimation models, construction of the power analysis tool, study of the power advantages of the architecture and identification of subsystems requiring power optimization. / Master of Science

The phenomenal density growth in semiconductors has resulted in the availability of billions of transistors on a single die. The time-to-design is shrinking continuously due to aggressive competition. Also, the integration of many discrete components on a single chip is growing at a rapid pace. Designing such heterogeneous systems in short duration is becoming difficult with existing technology. Field-Programmable Gate Arrays offer a good alternative in both productivity and heterogeneity issues. However, there are many obstacles that need to be addressed to make them a viable option. One such obstacle is the lack of early design space exploration tools and techniques for FPGA designs. This thesis develops techniques to evaluate systematically, the available design options before the actual system implementation. The aspect which makes this problem interesting, yet complicated, is that a system-level optimization is not linearly summable. The discrete components of a system, benchmarked as best in all design parameters — speed, area and power, need not add up to the best possible system. This work addresses the problem in two ways. In the first approach, we demonstrate that by working at higher levels of abstraction, one can achieve orders of improvement in productivity. Designing a system directly from its behavioral description is an on-going effort in industry. Instead of focusing on design aspects, we use these methods to develop quick prototypes and estimate the design parameters. Design space exploration needs relative comparison among available choices and not accurate values of design parameters. It is shown that the proposed method can do an acceptable job in this regard. The second approach is about evolving statistical techniques for estimating the design parameters and then algorithmically searching the design space. Specifically, a high level power estimation model is developed for FPGA designs. While existing techniques develop power model for discrete components separately, this work evaluates the option of generic power model for multiple components. / Master of Science

While FPGAs provide flexibility for performing high performance DSP functions, they consume a significant amount of power. Often, a large portion of the dynamic power is wasted on unproductive signal glitches. Reducing glitching reduces dynamic energy consumption. In this study, retiming is used to reduce the unproductive energy wasted in signal glitches. Retiming can reduce energy by up to 92%. Evaluating energy consumption is an important part of energy reduction. In this work, an activity rate-based power estimation tool is introduced to provide FPGA architecture independent energy estimations at the gate level. This tool can accurately estimate power consumption to within 13% on average. This activation rate-based tool and retiming are combined in a single algorithm to reduce energy consumption of FPGA designs at the gate level. In this work, an energy evaluation metric called energy area delay is used to weigh the energy reduction and clock rate improvements gained from retiming against the area and latency costs. For a set of benchmark designs, the algorithm that combines retiming and the activation rate-based power estimator reduces power on average by 40% and improves clock rate by 54% for an average 1.1x area cost and a 1.5x latency increase.

[pt] Os satélites de um sistema de comunicações que opera numa determinada faixa de frequências utilizando satélites não-geoestacionários podem sofrer interferências indesejáveis provocadas por transmissores do Serviço Fixo Terrestre (SF) que operam nessa mesma faixa. Para o operador do sistema não geoestacionário é importante identificar quais as áreas da superfície da Terra que contêm os transmissores responsáveis por essas interferências indesejáveis, o que seria um primeiro passo na tentativa de resolver o problema através de negociações bilaterais com as estações transmissoras do SF envolvidas (coordenação). O presente trabalho apresenta a modelagem matemática do problema, e propõe que a identificação dessas áreas seja feita por meio da estimação das potências e apontamentos (ângulos de azimute e elevação) das antenas transmissoras do SF com base em medidas de potência tomadas nos diversos feixes de recepção de um satélite de teste. O trabalho analisa aspectos específicos do problema e propõe a utilização do Filtro de Kalman Estendido (EKF) para a estimação das potências e apontamentos das antenas transmissoras do SF. / [en] Satellites of a non-geostationary communication system may be victims of harmful interference produced by terrestrial fixed service (FS) transmitting stations operating in the same frequency band. It is important to the satellite system operator to identify the specific areas on Earth s surface containing the FS stations that are responsible for such interference. This would be a first step for solving the problem via bilateral coordination with each of the involved FS operators. This dissertation presents a mathematical model for the problem and proposes that the identification of these areas be made though the estimation of the transmitted power and the antenna pointing (azimuth and elevation angles) of the various FS stations, based on received power measurements taken on the beams of a test non-GSO satellite. This work also investigates the particular aspects of the problem and proposes the Extended Kalman Filter (EKF) as the algorithm for estimation.

OFDM has been recognized as a powerful multi-carrier modulation technique that provides efficient spectral utilization and resilience to frequency selective fading channels. Adaptive modulation is a concept whereby the modulation modes are dynamically changed based on the perceived instantaneous channel conditions. In conjunction with OFDM systems, adaptive modulation is a very powerful technique to combat the frequency selective nature of mobile channels, while simultaneously attempting to fully maximize the time-varying capacity of the channel. This is based on the fact that frequency selective fading affects the sub-carriers unevenly, causing some of them to fade more severely than others. The modulation modes are adaptively selected on the sub-carriers depending on the amount of fading, to maximize throughput and improve the overall BER. Transmission parameter adaptation is the response of the transmitter to the time-varying channel quality. To efficiently react to the dynamic nature of the channel, adaptive OFDM systems rely on efficient algorithms in three key areas namely, channel quality estimation, transmission parameter selection and signaling or blind detection mechanisms of the modified parameters. These are together termed as the enabling techniques that contribute to the effective performance of adaptive OFDM systems. This thesis deals with higher performance and efficient enabling parameter estimation algorithms that further improve the overall performance of adaptive OFDM systems. Traditional estimation of channel quality indicators, such as noise power and SNR, assume that the noise has a flat power spectral density within the transmission band of the OFDM signal. Hence, a single estimate of the noise power is obtained by averaging the instantaneous noise power values across all the sub-carriers. In reality, the noise within the OFDM bandwidth is a combination of white and correlated noise components, and has an uneven affect across the sub-carriers. It is this fact that has motivated the proposal of a windowing approach for noise power estimation. Windowing provides many local estimates of the dynamic noise statistics and allows better noise tracking across the OFDM transmission band. This method is particularly useful for better resource utilization and improved performance in sub-band adaptive modulation, where adaptation is performed on the sub-carriers on a group-by-group basis based on the observed channel conditions. Blind modulation mode detection is another relatively unexplored issue in regard to adaptation of OFDM systems. The receiver has to be informed of the appropriate modulation modes used at the transmitter for proper demodulation. If this can be done without any explicit signaling information embedded within the OFDM symbol, it has the advantage of improved throughput and data capacity. A model selection approach is taken, a novel statistical blind modulation detection method based on the Kullback-Leibler (K-L) distance is proposed. This algorithm takes into account the distribution of the Euclidian distances from the received noisy samples on the complex plane to the closest legitimate constellation points of all the modulation modes used. If this can be done without any explicit signaling information embedded within the OFDM symbol, it has the advantage of improved throughput and data capacity. A model selection approach is taken, and a novel statistical blind modulation detection method based on the Kullback-Leibler (K-L) distance is proposed. This algorithm takes into account the distribution of the Euclidian distances from the received noisy samples on the complex plane to the closest legitimate constellation points of all the modulation modes used.

With the total energy consumption of computing systems increasing at a steep rate, much attention had been paid to the design of energy-efficient computing systems and applications. So far, database system design has focused on improving the performance of query processing. The objective of this study is to explore the potential of energy conservation in relational database management systems. The hypothesis is: by modifying the query optimizer in a Database management system (DBMS) to take the energy cost of query plans into consideration, we will be able to reduce the energy usage of database servers and control the tradeoffs between energy consumption and system performance. In this thesis, we provide an in-depth anatomy of typical queries in various benchmarks and qualitatively analyze the energy profile of such queries. The results of extensive experiments show that power savings in the range of 11% to 22% can be achieved by equipping the DBMS with a simple query optimizer that selects query plans based on both estimated processing time and energy requirements. We advocate more research efforts be invested into the design and evaluation of power-aware DBMSs in hope to reach higher level of energy efficiency.

Clock scheduling is studied to improve the performance of synchronous sequential circuits. The performance improvement covers the optimization of the clock frequency and the peak power consumption, separately. For clock period minimization, cycle stealing method is utilized, in which the redundant cycle time of fast combinational logic is transferred to slower logic by proper clock skew adjustment of registers. The clock scheduling system determines the minimum clock period that a synchronous sequential circuit can operate without hazards. The timing of each register is adjusted for operation with the minimum clock period. The dependence of the propagation delays of combinational gates on load capacitance values are modeled in order to increase the accuracy of the clock period minimization algorithm. Simulation results show up to 45% speed-up for circuits that are scheduled by the system. For peak power minimization, the dependence of the switching currents of circuit elements on the load capacitance values are modeled. A new method, namely the Shaped Pulse Approximation Method (SPA), is proposed for the estimation of switching power dissipation of circuit elements for arbitrary capacitive loads. The switching current waves can accurately be estimated by using the SPA method with less than 10% normalized rms error. The clock scheduling algorithm of Takahashi for the reduction of the peak power consumption of synchronous sequential circuits is implemented using the SPA method. Up to 73% decrease in peak power dissipation is observed in simulation results when proper clock scheduling scheme is applied to test circuits.

Orientadores: Rodolfo Jardim de Azevedo, Guido Costa Souza de Araujo / Tese (doutorado) - Universidade Estadual de Campinas, Instituto de Computação / Made available in DSpace on 2018-08-15T15:19:14Z (GMT). No. of bitstreams: 1 Klein_FelipeVieira_D.pdf: 3206083 bytes, checksum: c061ecd0ae638bd119cadc4fdfaf309c (MD5) Previous issue date: 2009 / Resumo: O crescente aumento da demanda por funcionalidades agregadas a um mesmo dispositivo, aliado a rígidas restrições de desempenho colocam a dissipação de potência como um dos requisitos mais importantes dentro do fluxo de projeto em CAD/EDA. A constante evolução da tecnologia de semicondutores das 'ultimas décadas tem garantido o aumento da complexidade dos sistemas, que demandam cada vez mais recursos computacionais. Contudo, esta crescente complexidade leva ao aumento do consumo de potência, que tem uma série de efeitos colaterais indesejados, tais como, problemas térmicos e aumento da densidade de potência, comprometendo a confiabilidade do circuito. Desta forma, 'e necessário introduzir soluções para o resfriamento do chip, aumentando seu custo final e seu time-to-market. Além disso, no que diz respeito aos dispositivos portáteis, estes têm sua autonomia reduzida devido aos elevados montantes de energia requeridos para seu funcionamento. As contribuições desta tese englobam dois temas distintos dentro do chamado low-power design. O primeiro tema aborda as técnicas de macromodelagem de potência em RTL. Inicialmente, 'e mostrado que as técnicas convencionais de modelo simples têm limitações intrínsecas que afetam a precisão de suas estimativas. Uma análise quantitativa e qualitativa 'e conduzida, apontando as limitações de diversas técnicas conhecidas, e demonstrando que o uso de uma 'única técnica pode comprometer a qualidade geral das predições. Em seguida, são propostas duas novas técnicas de macromodelagem baseadas em múltiplos modelos, a fim de explorar os pontos fortes de cada modelo individual e otimizar a qualidade das estimativas. Os resultados obtidos com a abordagem proposta revelaram melhorias significativas em relação a abordagem convencional, alcançando resultados 7 vezes superiores para os erros médios, enquanto que os erros máximos foram reduzidos em até 9 vezes. O segundo tema aborda uma 'área que vem recebendo muita atenção com a chegada da era multi-core: o paradigma de programação concorrente conhecido como memória transacional, cujo intuito 'e tornar a tarefa de criar software concorrente mais simples. Embora esta seja uma 'área muito ativa, os pesquisadores têm quase que invariavelmente se concentrado no desempenho das aplicações, negligenciando métricas tais como energia e potência. Este trabalho apresenta uma análise pormenorizada do consumo de energia de uma implementação estado-da-arte de STM (Software Transactional Memory), sendo a primeira do gênero neste contexto. Além disso, uma nova estratégia de gerenciamento de contenção baseada em DVFS (Dynamic Voltage and Frequency Scaling) é proposta, com o intuito de reduzir o consumo de energia de aplicações exibindo alta contenção no barramento / Abstract: The growing demand for features to be included into electronic devices, along with tight performance constraints, make power consumption one of the most important design constraints in the CAD/EDA design flow. The constant evolution of the semiconductor technology, observed in the last decades, has considerably increased the complexity of today's systems, which demand exorbitant computational resources. Unfortunately, the growing complexity leads to a higher power consumption which, in turn, has a number of undesired side effects, such as thermal issues and increased power density, thus compromising the overall circuit reliability. Hence, elaborated cooling solutions are required, increasing its final cost and compromising its time-to-market. Moreover, the large amounts of energy needed by portable devices substantially reduce their battery lifetime. The contributions of this thesis encompass two distinct topics within the so-called low-power design. The first one is related to RTL power macromodeling techniques. It is shown that conventional single-model techniques have intrinsic limitations that affect their accuracy. Then, a quantitative and qualitative analysis is conducted, pinpointing the limitations of several well-known techniques, followed by a demonstration that the adoption of a single technique may compromise the overall quality of the estimates. Subsequently, two novel multi-model power macromodeling techniques are proposed, which exploit the strengths of each single-model technique in order to optimize the accuracy of power estimation. The obtained results revealed substantial improvements in accuracy, which becomes 7 times better for the average errors, while the overall maximum estimation error is divided by 9. The second part of this thesis is related to a topic which is gaining much attention recently in the multi-core era: the concurrent programming paradigm widely known as transactional memory, which aims at making the task of creating concurrent software simpler. Although this is a rather active area, researchers have invariably focused on performance, leaving other metrics such as power and energy unattended. This work presents a detailed power analysis of a state-of-the-art STM (Software Transactional Memory) implementation, being the first one in this context. Moreover, a novel DVFS-based (Dynamic Voltage and Frequency Scaling) contention management strategy is proposed, which reduces the energy consumption by exploiting the slack available in applications displaying high bus contention / Doutorado / Sistemas de Computação / Doutor em Ciência da Computação