Low drop out (LDO) voltage regulators are widely used for post regulating the switching ripples generated by the switched mode power supplies (SMPS). Due to demand for portable applications, industry is pushing for complete system on chip power management solutions. Hence, the switching frequencies of the SMPS are increasing to allow higher level of integration. Therefore, the subsequent post-regulator LDO must have good power supply rejection (PSR) up to switching frequencies of SMPS. Unfortunately, the conventional LDOs have poor PSR at high frequencies. The objective of this research is to develop novel LDO regulators that can achieve good high frequency PSR performance. In this thesis, two PSR improvement methods are presented. The first method proposes a novel power supply noise-cancelling scheme to improve the PSR of an external-capacitor LDO. The proposed power supply noise-cancelling scheme is designed using adaptive power consumption, thereby not degrading the power efficiency of the LDO. The second method proposes a feed forward ripple cancellation technique to improve the PSR of capacitor-less LDO; also a dynamically powered transient improvement scheme has been proposed. The feed forward ripple cancellation is designed by reusing the load transient improvement block, thus achieving the improvement in PSR with no additional power consumption. Both the projects have been designed in TSMC 0.18 μm technology. The first method achieves a PSR of 66 dB up to 1 MHz where as the second method achieves a 55 dB PSR up to 1 MHz.

Low Dropout Regulators (LDOs) are extensively used in portable applications like mobile phones, PDAs and notebooks. These portable applications demand high power efficiency and low output voltage ripple. In addition to these, the radio circuits in these applications demand high power supply rejection (PSR). The output voltage of a conventional DC/DC converter (generally switched mode) has considerable ripple which feeds as input to these LDOs. And the challenge is to suppress these ripples for wide range of frequencies (for radio units) to provide clean supply. Enhanced buffer based compensation is proposed for the fully on-chip CMOS LDO which stabilizes the loop for different load conditions as well as improve the power supply rejection (PSR) until frequencies closer to open loop‟s unity-gain frequency. The stability and PSR are totally valid even for load capacitor varying from 0 to 100 pF. The proposed capacitor-less LDO is fabricated in On-Semi 0.5 μm fully CMOS process. Experimental results confirm a PSR of -30 dB till 420 KHz for the maximum load current of 50mA. The load transients of the chip shows transient glitches less than 90 mV independent of output capacitance.

The first topic of this thesis is a novel NTSC video sync separator (NSS) with a high-PSR (power supply rejection) bias generation circuitry (BGC) comprising a temperature compensation circuitry. The proposed BGC is composed of step-down regulators and a bandgap-based bias with cascode current control. The clamping voltages required for sync separation from an NTSC signal are generated. The second topic is a temperature-compensated 6th order transconductance-C (Gm-C) anti-aliasing filter (AAF) with digitally tunable bandwidth which can be applied in the analog front-end circuit of DVB-T receivers. The proposed AAF is controlled by digital signals to provide three different baseband bandwidth (6, 7, 8 MHz) selection. A regulator with a bandgap circuitry supplies a stable voltage to suppress the variations of power and temperature. Moreover, a temperature -compensated circuitry is used to neutralize bandwidth drifting caused by the temperature variation. The bandwidth accuracy of the proposed design verified by HSPICE post-layout simulations is better than 3.28% at every PVT (process, supply voltage, temperature) corner. It is adequate for the DVB-T receivers¡¦ baseband processing.

Ring oscillators provide a central role in timing circuits for today?s mobile devices and desktop computers. Increased integration in these devices exacerbates switching noise on the supply, necessitating improved supply resilience. Furthermore, reduced voltage headroom in submicron technologies limits the number of stacked transistors available in a delay cell. Hence, conventional single-loop oscillators offer relatively few design options to achieve desired specifications, such as supply rejection. Existing state-of-the-art supply-rejection- enhancement methods include actively regulating the supply with an LDO, employing a fully differential or current-starved delay cell, using a hi-Z voltage-to-current converter, or compensating/calibrating the delay cell. Multiloop ring oscillators (MROs) offer an additional solution because by employing a more complex ring-connection structure and associated delay cell, the designer obtains an additional degree of freedom to meet the desired specifications. Designing these more complex multiloop structures to start reliably and achieve the desired performance requires a systematic analysis procedure, which we attack on two fronts: (1) a generalized delay-cell viewpoint of the MRO structure to assist in both analysis and circuit layout, and (2) a survey of phase-noise analysis to provide a bank of methods to analyze MRO phase noise. We distill the salient phase-noise-analysis concepts/key equations previously developed to facilitate MRO and other non-conventional oscillator analysis. Furthermore, our proposed analysis framework demonstrates that all these methods boil down to obtaining three things: (1) noise modulation function (NMF), (2) noise transfer function (NTF), and (3) current-controlled-oscillator gain (KICO). As a case study, we detail the design, analysis, and measurement of a proposed multiloop ring oscillator structure that provides improved power-supply isolation (more than 20dB increase in supply rejection over a conventional-oscillator control case fabricated on the same test chip). Applying our general multi-loop-oscillator framework to this proposed MRO circuit leads both to design-oriented expressions for the oscillation frequency and supply rejection as well as to an efficient layout technique facilitating cross-coupling for improved quadrature accuracy and systematic, substantially simplified layout effort.

This thesis includes three topics. The first topic is a low-variation 1 MHz clock generator. The second one is a high sensitivity linear voltage-to-frequency converter. The last one is a high-PSR bias circuit for NTSC SYNC separation. All of the circuits can be applied to related consumer electronic products. The low-variation 1 MHz clock generator includes a bias circuit which automatically compensates the drifting caused by temperature variations. Furthermore, the circuit contains neither BJTs nor diodes to reduce the area cost. The frequency variation is measured to be less than 2.55\% in the range of 0¢J~90¢J. The high sensitivity linear voltage-to-frequency converter is mainly constructed by a window comparator[11]. We analyze and improve the performance of accuracy to achieve both high accuracy and high sensitivity. The accuracy error is less than 1% and sensitivity is 84 KHz/V in the voltage range of 0.1V~0.8V. The high-PSR bias circuit for NTSC SYNC Separation is implemented by a bandgap reference which is controlled by a feedback loop to reduce the interference of the environment. The measurement variation of the bandgap reference is less than 1\% when the variation of power supply is 10\%. The sensitivity of the bandgap reference to temperature is measured to be 0.0006V/¢J.

Abstract Class A and class AB operational amplifiers are an essential part of a mixed- signal chip, where they are used as active filter sub-blocks, compensators, reference current generators and voltage buffers, to name just a few of many applications. For analog circuits such as operational amplifiers a mixed-signal chip is a very unfriendly operating environment, where the power supply is often corrupted by high current switching circuits. In addition, power supply voltages for analog blocks are shrinking, because of the deployment of new battery technologies and fine line length integrated circuit processes, which can reduce the amplifier dynamic range a problem requiring supply insensitive low voltage compatible amplifier topologies and other analog blocks. The aims of this thesis were to further develop the low voltage compatible class AB amplifier topologies published earlier by other authors, to improve their bandwidth efficiency by means of re-examining two- and three-stage amplifier compensation techniques and to find solutions for enhancing the high frequency power supply noise rejection performance of class A and class AB amplifiers without degrading their signal path stability. The class AB amplifier cores presented here improve the amplifier’s power supply noise insensitivity at high frequencies and increase bandwidth efficiency when compared to the commonly used two-stage Miller compensated amplifier, enabling the construction of better buffers and more power-efficient and reliable low voltage mixed signal chips.

abstract: With the push for integration, a slew of modern switching power management circuits are operating at higher switching frequencies in order to reduce passive filter sizes. But while these switching regulators provide power conversion at high efficiencies, their output is prone to ripples due to the inherent switching behavior. These switching regulators use linear-low dropout regulators (LDOs) downstream to provide clean supplies. Typically, these LDOs have good power supply rejection (PSR) at lower frequencies but this degrades at higher frequencies. Therefore, some residual ripple is still manifested on the output. Because of this, high power supply rejection (PSR) with a wide rejection frequency band is becoming a critical requirement in linear low-dropout regulators (LDOs) used in complex systems- on-chip (SOCs). Typical LDOs achieve higher PSR within their loop-bandwidth; however, their supply rejection performance degrades with reduced loop-gain outside their loop- bandwidth. The LDOs with external filtering capacitors may also have spectral peaking in their PSR response, causing excess system- level supply noise. This work presents an LDO design approach, which achieves a PSR of higher than 68 dB up to 2 MHz frequency and over a wide range of loads up to 250 mA. The wide PSR bandwidth is achieved using a current-mode feedforward ripple canceller (CFFRC) amplifier which provides up to 25 dB of PSR improvement. The feedforward path gain is inherently matched to the forward gain of the LDO, not requiring calibration. The LDO has a fast load transient response with a recovery time of 6.1μs and has a quiescent current of 5.6μA. For a full load transition, the LDO achieves settling with overshoot and undershoot voltages below 27.6 mV and 36.36 mV, respectively. The LDO is designed and fabricated in a 180 nm bipolar/CMOS/DMOS (BCD) technology. The CFFRC amplifier helps to achieve low quiescent power due to its inherent current mode nature, eliminating the need for supply ripple summing amplifiers and adaptive biasing. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2020

Power management components can be found in a host of different applications ranging from portable hand held gadgets to modern avionics to advanced medical instrumentations, among many other applications. Low-dropout (LDO) linear regulators are particularly popular owing to their: ease of use, low cost, high accuracy, low noise, and high bandwidth. With all its glory, however, it tends to underperform switched-mode power supplies (SMPS) when with comes to power conversion efficiency, although the later generates a lot of ripple at its output. With the growing need to improve system efficiency (hence longer battery life) without degrading system performance, many high end (noise sensitive) applications such as data converters, RF transceivers, precision signal conditioning, among others, use high efficiency SMPS with LDO regulators as post-regulators for rejecting the ripple generated by SMPS. This attribute of LDO regulators is known as power supply rejection (PSR). With the trend towards increasing switching frequency for SMPS, to minimize PC board real estate, it is becoming ever more difficult for LDO regulators to suppress the associate high frequency ripple since at such high frequencies, different parasitic components of the LDO regulator start to deteriorate its PSR performance. There have been a handful of different techniques suggested in the literature that can be used to achieve good PSR performance at higher frequencies. However, each of these techniques suffers from a number of drawbacks ranging from reduced efficiency to increased cost to increased solution size, and with the growing demand for higher efficiency and smaller power supplies, these techniques have their clear limitations. The objective of this research project is to develop a novel current-mode LDO regulator that can achieve good high frequency PSR performance without suffering from the afore mentioned drawbacks. The proposed architecture was fabricated using a proprietary 1.5 um Bipolar process technology, and the measurement results show a PSR improvement of 20dB (at high frequencies) over conventional regulators. Moreover, the proposed LDO regulator requires a small 15nF output capacitor for stability, which is far smaller than some of the currently used techniques.