Quadrature LO signal is a key element in many of the RF transceivers which tend to dominate today’s wireless communication technology. The design of a quadrature LC VCO with better phase noise and lower power consumption forms the core of this work. This thesis investigates a coupling mechanism to implement a quadrature voltage controlled oscillator using indirect injection method. The coupling network in this QVCO couples the two LC cores with their super-harmonic and it recycles its bias current back into the LC tank such that the power consumed by the coupling network is insignificant. This recycled current enables the oscillator to achieve higher amplitude of oscillation for the same power consumption compared to conventional design, hence assuring better phase noise. Mathematical analysis has been done to study the mechanism of quadrature operation and mismatch effects of devices on the quadrature phase error of the proposed QVCO. The proposed quadrature LC VCO is designed in TSMC 0.18 μm technology. It is tunable from 2.61 GHz - 2.85 GHz with sensitivity of 240 MHz/V. Its worst case phase noise is -120 dBc/Hz at 1 MHz offset. The total layout area is 1.41 mm^2 and the QVCO core totally draws 3 mA current from 1.8 V supply.

The advent of high-fT silicon CMOS/BiCMOS technologies has led to a dramatic upsurge in the research and development of radio and microwave frequency integrated circuits (ICs) in silicon. The integration of silicon-germanium heterojunction bipolar transistors (SiGe HBTs) into established "digital" CMOS processes has provided analog performance in silicon that is not only competitive with III-V compound-semiconductor technologies, but is also potentially lower in cost. Combined with improvements in silicon on-chip passives, such as high-Q metal-insulator-metal (MIM) capacitors and monolithic spiral inductors, these advanced RF CMOS and SiGe BiCMOS technologies have enabled complete silicon-based RF integrated circuit (RFIC) solutions for emerging wireless communication standards; indeed, both the analog and digital functionalities of an entire wireless system can now be combined in a single IC, also known as a wireless "system-on-a-chip" (SoC). This approach offers a number of potential benefits over multi-chip solutions, such as reductions of parasitics, size, power consumption, and bill-of-materials; however, a number of critical challenges must be considered in the integration of such SoC solutions. The focus of this research is the application of SiGe BiCMOS technology to on-going challenges in the development of receiver components for high speed wireless data networks. The research seeks to drive SoC integration by investigating circuit topologies that eliminate the need for off-chip components and are amenable to complete on-chip integration. The first part of this dissertation presents the design, fabrication, and measurement of a 5--6GHz sub-harmonic direct-conversion-receiver (DCR) front-end, implemented in the IBM 0.5um 5HP SiGe BiCMOS process. The design consists of a fully-differential low-noise amplifier (LNA), a set of quadrature (I and Q)x~2 sub-harmonic mixers, and an LO conditioning chain. The front-end design provides a means to address performance limitations of the DCR architecture (such as DC-offsets, second-order distortion, and quadrature phase and amplitude imbalances) while enabling the investigation of high-frequency IC design complications, such as package parasitics and limited on-chip isolation. The receiver front-end has a measured conversion gain of ~18dB, an input second-order intercept point of +17.5dBm, and a noise figure of 7.2dB. The quadrature phase balance at the sub-harmonic mixer IF outputs was measured in the presence of digital switching noise; 90<degree> balance was achieved, over a specific range of LO power levels, with a square wave noise signal injected onto the mixer DC supply rails. The susceptibility of receiver I/Q balance to mixed-signal effects in a SoC environment motivates the second part of this dissertation --- the design of a phase and amplitude tunable, quadrature voltage-controlled oscillator (QVCO) for the on-chip synthesis of quadrature signals. The QVCO design, implemented in the Freescale (formerly Motorola) 0.18um SiGe:C RFBiCMOS process, uses two identical, differential LC-tank VCOs connected such that the two oscillator outputs lock in quadrature to the same frequency. The QVCO designs proposed in this work provide the additional feature of phase-tunability, i.e. the relative phase balance between the quadrature outputs can be adjusted dynamically, offering a simulated tuning range of ~90<degree>+/-10â ¹degree> in addition, a variable-gain buffer/amplifier circuit that provides amplitude tunability is introduced. One potential application of the QVCO is in a self-correcting RF receiver architecture, which, using the phase and amplitude tunability of the QVCO, could dynamically adjust the IF output quadrature phase and amplitude balance, in near real-time, in the analog-domain. The need for high-quality inductors in both the DCR and QVCO designs motivates the third aspect of this dissertation --- the characterization and modeling of on-chip spiral inductors with patterned ground shields, which are placed between the inductor coil and the underlying substrate in order to improve the inductor quality factor (Q). The shield prevents the coupling of energy away from the inductor spiral to the typically lossy Si substrate, while the patterning disrupts the flow of induced image currents within the shield. The experimental effort includes the fabrication and testing of a range of inductors with different values, and different types of patterned ground shields in different materials. Two-port measurements show a ~50% improvement in peak-Q and a ~20% degradation in self-resonant frequency for inductors with shields. From the measured results, a scalable lumped element model is developed for the rapid simulation of spiral inductors with and without patterned ground shields. The knowledge gained from this work can be combined and applied to a range of future RF/wireless SoC applications. The designs developed in this dissertation can be ported to other technologies (e.g. RF CMOS) and scaled to other frequency ranges (e.g. 24GHz ISM band) to provide solutions for emerging applications that require low-cost, low-power RF/microwave circuit implementations. / Ph. D.