A grid graph is a finite embedded subgraph of the infinite integer grid. A solid grid graph is a grid graph without holes, i.e., each bounded face of the graph is a unit square. The reconfiguration problem for Hamiltonian cycle or path in a sold grid graph G asks the following question: given two Hamiltonian cycles (or paths) of G, can we transform one cycle (or path) to the other using some "operation" such that we get a Hamiltonian cycle (or path) of G in the intermediate steps (i.e., after each application of the operation)? In this thesis, we investigate reconfiguration problems for Hamiltonian cycles and paths in the context of two types of solid graphs: rectangular grid graphs, which have a rectangular outer boundary, and L- shaped grid graphs, which have a single reflex corner on the outer boundary, under three operations we define, flip, transpose and switch, that are local in the grid. Reconfiguration of Hamiltonian cycles and paths in embedded grid graphs has potential applications in path planning, robot navigation, minimizing turn costs in milling problems, minimizing angle costs in TSP, additive manufacturing and 3D printing, and in polymer science. In this thesis, we introduce a complexity measure called bend complexity for Hamiltonian paths and cycles in grid graphs, and using those measures we measure complexity of a grid graph G and give upper and lower bounds on the maximum bend complexity of an mxn grid graph. We define three local operations, flip, transpose and switch, where local means that the operations are applied on vertices that are close in the grid graph but may not be close on the path or cycle. We show that any Hamiltonian cycle or path can be reconfigured to any other Hamiltonian cycle or path in an mxn rectangular grid graph, where m <= 4, using O(|G|) flips and transposes, regardless of the bend complexities of the two cycles. We give algorithms to reconfigure 1-complex Hamiltonian cycles in a rectangular or L-shaped grid graph G using O(|G|) flips and transposes, where the intermediate steps are also 1-complex Hamiltonian cycles. Finally, we establish the structure of 1-complex Hamiltonian paths between diagonally opposite corners s and t of a rectangular grid graph, and then provide a strategy, based on work in progress, for designing an algorithm to reconfigure between any two 1-complex s, t Hamiltonian paths using switch operations. / Graduate

Circuit designs for field-programmable gate arrays (FPGAs) are typically compiled by FPGA vendor tools, such as Xilinx's Vivado Design Suite. In recent years, partial reconfiguration (PR) has emerged as a popular technique that allows portions of an FPGA to be dynamically reconfigured after the complete device has been configured with an initial bitstream. However, the nature of current FPGA vendor tools limits further innovation and possible usage models of PR.This thesis presents Maverick, an open-source proof-of-concept computer-aided design (CAD) flow for generating reconfigurable modules (RMs) which target PR regions in FPGA designs. Maverick builds upon existing open source tools (Yosys, RapidSmith2, and Project X-Ray) to form an end-to-end compilation flow. After an initial static design and PR region are created with Xilinx's Vivado PR flow, Maverick can then compile and configure RMs onto that PR region-without the use of vendor tools. In addition, this work enables users to import and export RMs between Vivado and RapidSmith2.Furthermore, this thesis demonstrates Maverick compiling RMs on both a desktop computer and on the embedded PYNQ-Z1 board, which contains a Zynq 7020 system on chip (SoC). Maverick runs on the ARM processor embedded within the processing system (PS) of the Zynq device, generating partial bitstreams which can then be configured onto a PR region within the programmable logic (PL) fabric of the same Zynq device. This unique case, not possible with current vendor tools like Vivado, demonstrates the feasibility of a single-chip embedded system which can both compile HDL designs to bitstreams and then configure them onto its own programmable fabric.

Emerging reconfiguration techniques that include partial dynamic reconfiguration and partial bitstream relocation have been addressed in the past in order to expose the flexibility of field programmable gate array at runtime. Partial bitstream relocation is a technique used to target a partial bitstream of a partial reconfigurable region (PRR) onto other identical reconfigurable regions inside an FPGA, while partial dynamic reconfiguration is used to target a single reconfigurable region. Prior works in this domain aim to minimize "relocation time" with the help of on-chip or on-line processing. In this thesis, a novel PRR-PRR relocation algorithm is proposed and implemented both in software and hardware. Dedicated hardware architecture, called the accelerated relocation circuit (ARC), is designed and presented for fast relocation. An analytical model is also proposed to evaluate the performance of the PRR-PRR relocation algorithm and highlight the speed-up obtained by the proposed hardware implementation. ARC has been tested on two categories of designs: dynamically scalable systolic array designs and fault tolerant designs. It has been compared against the software implementation of the algorithm, BiRF, hardware architecture for bitstream relocation, and a software solution for bitstream relocation. An average speed-up of 153x for ARC over BiRF is observed, with the additional advantage of not storing any bitstreams, thus saving invaluable block random access memory (BRAMs). Accuracy of proposed analytical model was found to be more than 95% for all the test cases.

Optimization techniques are widely applied in the power system planning and operation to achieve more efficient and reliable power supply. With the introduction of new technologies, the complexity of today’s power system increased significantly. Intelligent optimization techniques, such as Particle Swarm Optimization (PSO), can efficiently deal with the new challenges compared to conventional optimization techniques. This thesis presents applications of discrete PSO in two specific environments. The first one is for day-ahead optimal scheduling of the reconfigurable gird with distributed energy resources. The second one is a two-step method for rapid reconfiguration of shipboard power system. Effective techniques, such as graph theory, optimal power flow and heuristic mutation, are employed to make the PSO algorithm more suitable to application environments and achieve better performance.

This work presents an energy efficient adaptive error correction system utilizing the Reed-Solomon errors-and-erasures algorithm, targeted to an Altera Stratix FPGA device. The system adapts to changing channel conditions by reconfiguring the system with different decoders to allow for the lowest possible energy consumption rate that the current channel conditions will allow. A series of energy saving optimizations were applied to a set of previous designs, resulting in a reduction in the energy required to decode a megabit of data of more than 70%. In addition, a new channel model was used to assess the effects of differing reconfiguration rates on codeword error rate, energy consumption, and decoding speed.

Partial reconfiguration (PR) is the process of configuring a subset of resources on a Field Programmable Gate Array (FPGA) while the remainder of the device continues to operate. PR extends the usability of FPGAs and makes it possible to perform design bootstrapping. Just like bootstrapping in PCs, bootstrapping in FPGAs consists of using a small application to initialize basic services and load a larger, more complex application to the device. Bootstrapping allows for unique design applications that can be used to maintain communication services, increase design security, reduce initial configuration time, and reduce nonvolatile configuration memory storage. This thesis presents a generic bootstrap framework that can be used to construct a variety of bootstrap designs. This thesis also discusses necessary PR design rules and techniques for bootstrap design creation. Additionally, this thesis presents two applications that demonstrate the feasibility of bootstrapping. One application is a bootstrap loader featuring a PCI Express endpoint; this loader is capable of reconfiguring a subset of the hardware on an as-need basis. The other application is a prototype designed to demonstrate the bootstrapping for nonvolatile configuration memory reduction in space-bound payloads. While bootstrap design is more complex than standard FPGA designs, bootstrapping increases the flexibility and capability of FPGAs.

In this dissertation, a novel self-repair approach based on Consensus Based Evaluation (CBE) for autonomous repair of SRAM-based Field Programmable Gate Arrays (FPGAs) is developed, evaluated, and refined. An initial population of functionally identical (same input-output behavior), yet physically distinct (alternative design or place-and-route realization) FPGA configurations is produced at design time. During run-time, the CBE approach ranks these alternative configurations after evaluating their discrepancy relative to the consensus formed by the population. Through runtime competition, faults in the logical resources become occluded from the visibility of subsequent FPGA operations. Meanwhile, offspring formed through crossover and mutation of faulty and viable configurations are selected at a controlled re-introduction rate for evaluation and refurbishment. Refurbishments are evolved in-situ, with online real-time input-based performance evaluation, enhancing system availability and sustainability, creating an Organic Embedded System (OES). A fault tolerance model called N Modular Redundancy with Standby (NMRSB) is developed which combines the two popular fault tolerance techniques of NMR and Standby fault tolerance in order to facilitate the CBE approach. This dissertation develops two of instances of the NMRSB system - Triple Modular Redundancy with Standby (TMRSB) and Duplex with Standby (DSB). A hypothetical Xilinx Virtex-II Pro FPGA model demonstrates their viability for various applications including a 3-bit x 3-bit multiplier, and the MCNC91 benchmark circuits. Experiments conducted on the model iii evaluate the performance of three new genetic operators and demonstrate progress towards a completely self-contained single-chip implementation so that the FPGA can refurbish itself without requiring a PC host to execute the Genetic Algorithm. This dissertation presents results from the simulations of multiple applications with a CBE model implemented in the C++ programming language. Starting with an initial population of 20 and 30 viable configurations for TMRSB and DSB respectively, a single stuck-at fault is introduced in the logic resources. Fault refurbishment experiments are conducted under supervision of CBE using a fitness state evaluation function based on competing outputs, fitness adjustment, and different level threshold. The device remains online throughout the process by which a complete repair is realized with Hamming Distance and Bitweight voting schemes. The results indicate a Hamming Distance TMRSB approach can prevent the most pervasive fault impacts and realize complete refurbishment. Experimental results also show that the Autonomic Layer demonstrates 100% faulty component isolation for both Functional Elements (FEs) and Autonomous Elements (AEs) with randomly injected single and multiple faults. Using logic circuits from the MCNC-91 benchmark set, availability during repair phases averaged 75.05%, 82.21%, and 65.21% for the z4ml, cm85a, and cm138a circuits respectively under stated conditions. In addition to simulation, the proposed OES architecture synthesized from HDL was prototyped on a Xilinx Virtex II Pro FPGA device supporting partial reconfiguration to demonstrate the feasibility for intrinsic regeneration of the selected circuit.

Yes / Here we present an in-depth analysis of structural factors that modulate peptide-capped nanoparticle catalytic activity via optically driven structural reconfiguration of the biointerface present at the particle surface. Six different sets of peptide-capped Au nanoparticles were prepared, in which an azobenzene photoswitch was incorporated into one of two well-studied peptide sequences with known affinity for Au, each at one of three different positions: The N- or C-terminus, or mid-sequence. Changes in the photoswitch isomerization state induce a reversible structural change in the surface-bound peptide, which modulates the catalytic activity of the material. This control of reactivity is attributed to changes in the amount of accessible metallic surface area available to drive the reaction. This research specifically focuses on the effect of the peptide sequence and photoswitch position in the biomolecule, from which potential target systems for on/off reactivity have been identified. Additionally, trends associated with photoswitch position for a peptide sequence (Pd4) have been identified. Integrating the azobenzene at the N-terminus or central region results in nanocatalysts with greater reactivity in the trans and cis conformations, respectively; however, positioning the photoswitch at the C-terminus gives rise to a unique system that is reactive in the trans conformation and partially deactivated in the cis conformation. These results provide a fundamental basis for new directions in nanoparticle catalyst development to control activity in real time, which could have significant implications in the design of catalysts for multistep reactions using a single catalyst. Additionally, such a fine level of interfacial structural control could prove to be important for applications beyond catalysis, including biosensing, photonics, and energy technologies that are highly dependent on particle surface structures. / Air Office of Scientific Research, grant number FA9550-12- 1-0226.

The work of this thesis is concerned with the aggregation and advancement of modelling practise as used within modern day product development and optimisation environments making use of Model Based Design (¿MBD¿) and similar procedures. A review of model development and use forms the foundation of the work, with the findings being aggregated into two unique approaches for rapid model development and reconfiguration; the Plug-and-Simulate (¿PaS¿) approach and the Paradigm for Large Model Creation (¿PLMC¿); each shown to posses its own advantages. To support the MBD process a model optimisation algorithm that seeks to eliminate parameters that are of little or no significance to a simulation is developed. Eliminations are made on the basis of an energy analysis which determines the activity of a number of energy elements. Low activity elements are said to be of less significance to the global dynamics of a model and thus become targets for elimination. A model configuration tool is presented that brings together the PLMC and parameter elimination algorithm. The tool is shown to be useful for rapid configuration and reconfiguration of models and is capable of automatically running the optimisation algorithms thus producing a simulation model that is parametrically and computationally optimised. The response of the plug-and-simulate drivetrain submodels, assembled to represent a front wheel drive drivetrain, is examined. The resulting model is subjected to a torque step-input and an empirically obtained torque curve that characterises the input to a drivetrain undergoing steady acceleration. The model displays the expected response in both its full parameter and parameter reduced versions with simulation efficiency gains observed in the parameter reduced version. / EPSRC

Future all-electric warships with an integrated power system (IPS) are capable of unlocking large amounts of power dedicated to propulsion and redirecting this power for service loads, weapon loads, and other loads. The IPS for all-electric ships combines the power generation system, electric propulsion system, power distribution system, and power control and management system all together. The move to IPS design will significantly improve efficiency, effectiveness, and survivability. To meet the needs of the US Navy, enhancing survivability by reducing susceptibility to damage, a IPS prefers decentralized reconfiguration system is preferred for IPS instead of traditional reconfiguration techniques used for terrestrial power grids. A multi-agent system (MAS) is a loosely coupled network composed of several agents. These agents interact with their environments and communicate with each other to solve problems that are beyond the individual capabilities or knowledge of each single agent. Because of its decentralized feature and lack of a global control feature, MAS appears to be the best candidate for IPS reconfiguration. This research work proposes a new model of an IPS, based on the Naval Combat Survivability, DC Distribution Test-bed (NCS DCDT). The new model combines the electric power generation system, electric propulsion system, and AC-DC zonal distribution system. To decrease the probability of distribution zones losing power, the new model modifies original design of the zonal distribution system in NCS DCDT. Another main endeavor of this research work is to design a MAS for reconfiguration of an IPS with AC-DC zonal distribution system. The MAS consists of three sub-MAS, named power generation MAS, propulsion MAS, and distribution MAS, and includes forty-one different agents which are instances of nineteen different abstract agent classes. The MAS is implemented with JAVA/JADE software and simulated on a platform of JADE 3.4.1 and JAVA jdk 1.5.0_08. Simulation results show that the MAS can execute reconfiguration functions such as fault area isolation, automatic switching, and load shedding.