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<p> Architecture Description Languages were developed to support the abstract level of software structuring that is the subject matter of software architecture. CommUnity is an ADL built on co-ordination principles and a categorical framework to support the composition of specifications of components to form the system's specification. However, an important problem of CommUnity is the lack of support for specifying the system's architectural changes in both the set of components and the connections between them.</p> <p> This thesis presents DynaComm, an extension of CommUnity to support hierarchical design and dynamic reconfiguration of component based systems. Several new language constructs are introduced into DynaComm: subsystems are coarse grained components which are considered as the basic unit for the construction of systems, connectors encapsulate a component interaction pattern that can organize the possibly complicated interactions between the components of a subsystem. We also propose the idea of interface manager to solve the problem of incorrectly synchronized actions in CommUnity, and the concept of population manager to manage the live instances of components in a subsystem, through which we can model potentially complicated dynamic reconfigurations in a system.</p> <p> To use the semantics of CommUnity in defining the semantics of DynaComm, a "normalization" technique is introduced to transform the parameterized (indexed) actions into "normal" actions of CommUnity and reduce the specification of connectors and subsystems to flat CommUnity designs, so that we can derive the system's semantics in a certain state.</p> <p> Two illustrative examples, fault-tolerant dynamic client-server and vending machine systems, are also given to show the usage of DynaComm in modeling complicated and dynamic systems.</p> / Thesis / Master of Science (MSc)

Network processors are becoming a predominant feature in the field of network hardware. As new network protocols emerge and data speeds increase, contemporary general-purpose network processors are entering their second generation and academic research is being actively conducted into new techniques for the design and implementation of these systems. At the same time, systems ranging from secured military communications equipment to consumer devices are being updated to provide network connectivity. Many of these devices require, or would benefit from, the inclusion of device security in addition to data security. Whether it is a top-secret encryption scheme that must be concealed or a personal device that needs protection against unauthorized use, security of the device itself is becoming an important factor in system design. Unfortunately, current network processor solutions were not developed with device security in mind. A secure adaptive network processor can provide the means to fill this gap while continuing to provide full support for emerging communication protocols. This dissertation describes the concept and structure of one such device. Analysis of the hardware security provided by the proposed device is provided to highlight strengths and weaknesses, while a prototype system is developed to allow it to be embedded into practical applications for investigation. Two such applications are developed, using the device to provide support for both a secure network edge device and a user-adaptable network gateway. Results of these experiments indicate that the proposed device is useful both as a hardware security measure and as a basis for user adaptation of information-handling systems. / Ph. D.

There is currently a strong trend towards embedding Internet capabilities into electronics and everyday appliances. Most network controllers used in small appliances or for specialized purposes are built using micro controllers. However there are many applications where a hardware-oriented approach using Application Specific Integrated Circuits (ASICs) or Field Programmable Gate Arrays (FPGAs) is more suitable. One of the features of FPGAs that cannot be integrated into ASICs is runtime reconfiguration in which, certain portions of the chip are reconfigured at runtime while the other parts continue to operate normally. This feature is required for network controllers with multiple data transfer channels that need to preserve the state of the static channels while reconfiguration is taking place. It is also required for controllers with space constraints in terms of FPGA resources or time constraints in terms of reconfiguration times. This thesis explores the impact of partial reconfiguration on the performance of a network controller. An FPGA-based network controller that supports partial reconfiguration has been designed and constructed. Partial bitstreams that can configure certain channels of the network controller without a ecting the functioning of others have been created. Experiments have been performed that quantify the manner in which, the performance of the controller can be changed by loading these partial bitstreams onto the FPGA. These experiments demonstrated the advantages of using partial reconfiguration to change network-related parameters at runtime to optimize performance of the network controller. / Master of Science

The Xilinx Partial Reconfiguration tool kits have been instrumental for performing a wide variety of research on Xilinx FPGAs. These tool kits provide a methodology for creating rectangular partial reconfiguration modules that can be swapped in and out of a static baseline design with one or more PR slots. This thesis presents a new PR toolkit called OpenPR that, for starters, provides similar functionality to the Xilinx PR tool kits. The distinguishing feature of this toolkit is that it is being released as open source, and is intended to be customizable to the needs of researchers. OpenPR has been designed to be easy to use, extensible, portable, and compatible with a wide range of Xilinx software and devices. Aside from supporting the slot-based PR paradigm, OpenPR also provides a solid base for further research into partial reconfiguration and FPGA productivity oriented design tools. / Master of Science

Agile manufacturing has become a topic of great interest over the past several years. The entire domain of modeling and analyzing different types of agile manufacturing environments and systems, however, remain largely unexplored. The objective of this research is to provide fundamental insight into how manufacturing systems should be designed and reconfigured over time in order to cope with different agile manufacturing environments. To achieve this objective, three approaches are developed and integrated into one simulation-based model. The first approach is used to model different agile manufacturing environments. The second approach is used to define various ways in which manufacturing systems can be designed and reconfigured (i.e., design/reconfiguration strategies). The third comprises the cost and objective functions used to measure system performance when different design/reconfiguration strategies are used in different agile manufacturing environments. Based upon the assumptions adopted during this thesis, the experimental work performed suggests that despite the fact that agility incurs high costs, agile manufacturing systems are indeed necessary for certain manufacturing environments in which product life cycles are short yet demand per product type is high. Therefore, it is important in certain manufacturing environments to focus on reconfiguration in short periods of time, even at the expense of higher reconfiguration costs. / Master of Science

Yes / Here we present an in-depth analysis of structural factors that modulate peptide-capped nanoparticle catalytic activity via optically driven structural reconfiguration of the biointerface present at the particle surface. Six different sets of peptide-capped Au nanoparticles were prepared, in which an azobenzene photoswitch was incorporated into one of two well-studied peptide sequences with known affinity for Au, each at one of three different positions: The N- or C-terminus, or mid-sequence. Changes in the photoswitch isomerization state induce a reversible structural change in the surface-bound peptide, which modulates the catalytic activity of the material. This control of reactivity is attributed to changes in the amount of accessible metallic surface area available to drive the reaction. This research specifically focuses on the effect of the peptide sequence and photoswitch position in the biomolecule, from which potential target systems for on/off reactivity have been identified. Additionally, trends associated with photoswitch position for a peptide sequence (Pd4) have been identified. Integrating the azobenzene at the N-terminus or central region results in nanocatalysts with greater reactivity in the trans and cis conformations, respectively; however, positioning the photoswitch at the C-terminus gives rise to a unique system that is reactive in the trans conformation and partially deactivated in the cis conformation. These results provide a fundamental basis for new directions in nanoparticle catalyst development to control activity in real time, which could have significant implications in the design of catalysts for multistep reactions using a single catalyst. Additionally, such a fine level of interfacial structural control could prove to be important for applications beyond catalysis, including biosensing, photonics, and energy technologies that are highly dependent on particle surface structures. / Air Office of Scientific Research, grant number FA9550-12- 1-0226.

Yes / Electricity providers aims to deliver uninterrupted electrical services to their customers at minimum cost while providing a satisfactory quality service. Therefore, the power system reliability is essential in power distribution network planning, design, and operation. This paper proposes a novel mathematical model to improve the reliability of reconfigurable distribution networks via investing and operating tie-lines. While the failure is being repaired, tie-lines allow the network operator to transfer loads from failed zones to healthy zones. Constructing new tie-lines could improve the network’s flexibility, aiming to reduce the cost of expected energy not supplied (EENS). The objective function of the proposed method is a trade-off between the investment cost of tie-lines construction in the planning stage, the cost of tie-lines operation (e.g., opening/closing), and the cost of EENS in the operational stage. The model simultaneously evaluates the best combination of investments and network configuration for each contingency while considering network constraints. A multistage mathematical model is developed as mixed-integer linear programming (MILP) to overcome the computational complexity and maintain solver traceability for utility-scale realistic networks. The model can handle the network reconfiguration (NR) considering N-x contingency analysis in the operation stage while deciding the investment in tie-lines in the planning stage. The optimal investment and operation in tie-lines, according to numerical results, can reduce the cost of the Distribution System (DS) while responding with contingencies by 51 to 70%.

Wireless communication serves as the foundation for a wide range of services that have become an integral part of human life in this day and age. Driven by the desire to have a single piece of hardware that can provide multiple wireless services, attention has been directed to SDRs due to their programmable nature and the flexibility they can offer in operating over multiple standards. In addition, they can provide effective solutions to current challenges in wireless communication, such as spectrum overcrowding and inter-standard operability, as well as future challenges to come due to their upgradeability. Although SDRs have been around in the research community for over a decade, they have not reached the point of transitioning to the mass consumer market, size being one of the major obstacles. Numerous SDR hardware platforms have been developed demonstrating successful functionality, yet to this day most of them remain trapped in desktop/benchtop form factors which are not suited for mobility. A main factor contributing to the size of SDR units is the RF front end. Using current technology, wide-band operation of SDR RF front-ends is achieved by aggregating multiple dedicated components, each covering a portion of the frequency range. Recent technology advances have enabled the integration of wide frequency functionality inside a single integrated package. One example is a prototype RFIC transceiver chip from Motorola Research Labs which contains a complete direct conversion RF transceiver in a single chip, with a frequency coverage range of 100MHz-2.4GHz. RFIC5, the latest version of the chip, has additionally integrated high speed ADC and DAC units, leading to a significant reduction in the component count and the overall size of the SDR hardware. This thesis describes the implementation of a highly compact, SDR PC plug-in card, known as PicoRF. PicoRF is based on the Motorola's RFIC chip for the RF front-end functionality, while the combined computational power of a V5 FPGA and a PC host is used for waveform signal processing. An overlay gird consisting of an interconnection of PR slots is reserved on the FPGA to host the components of a signal processing pipeline which can be modified during run-time. Through a high speed PCIe connection, partial bitstreams can be downloaded from the host PC to the FPGA at a very high speed making it possible for the radio to modify its function in very short time intervals and greatly reducing the service interruption time. Control software running on the PC host manages the overall system operation including the RFIC which is controlled through a custom developed API. The combination of the laptop host and the plug-in card form a small form factor, mobile SDR node that is one step towards satisfying both the performance and ergonomics demand of the consumer market. / Master of Science

Configurable Computing is a technology which attempts to increase computational power by customizing the computational platform to the specific problem at hand. An experimental computing model known as wormhole run-time reconfiguration allows for partial reconfiguration and is highly scalable. In this approach, configuration information and data are grouped together in a computing unit called a stream, which can tunnel through the chip creating a series of interconnected pipelines. The Colt/Stallion project at Virginia Tech implements this computing model into integrated circuits. In order to create applications for this platform, a compiler is needed which can convert a human readable description of an algorithm into the sequences of configuration information understood by the chip itself. This thesis covers two compilers which perform this task. The first compiler, Tier1, requires a programmer to explicitly describe placement and routing inside of the chip. This could be considered equivalent to an assembler for a traditional microprocessor. The second compiler, Tier2, allows the user to express a problem as a dataflow graph. Actual placing and routing of this graph onto the physical hardware is taken care of through the use of a genetic algorithm. A description of the two languages is presented, followed by example applications. In addition, experimental results are included which examine the behavior of the genetic algorithm and how alterations to various genetic operator probabilities affects performance. / Master of Science