Thesis (M.S.)--Mississippi State University. Department of Electrical and Computer Engineering. / Title from title screen. Includes bibliographical references.

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The semiconductor industry is highly competitive environment where modest improvements in the manufacturing process can translate to significant cost savings. An area where improvements can be realized is reducing the number of wafers that fail to meet their electrical specifications. Wafers that fail to meet electrical specifications are scrapped, which negatively impacts yield and increases manufacturing costs. Most of the existing semiconductor process control research has focused on controlling individual steps during the manufacturing process via run-to-run control, but almost no work has looked at directly controlling device electrical characteristics. Since meeting electrical specifications is so critical to reducing scrap a fab-wide electrical parameter control scheme is proposed to directly control electrical parameter values. The goal of the controller is reducing the variation in the electrical parameters. The control algorithm uses a model to predict electrical parameter values after each processing step. Based on this prediction the decision to make a control move is made. If a control move is necessary, optimal adjustments for the subsequent processing steps are determined. The process model is continually updated so that it reflects the current process. A simple implementation using a least squares model is first proposed. Simulations and an industrial case study demonstrate the potential improvements that can be achieved with the algorithm and the limitations of the simple implementation are discussed. A partial least squares modeling and control algorithm combined with missing data algorithms are proposed as enhancements to the electrical parameter control algorithm to address many of the issues faced when implementing such a control strategy in real manufacturing environments. The enhancements take the input variable correlations into account when making control moves and utilize the correlation structure to make better model predictions. Simulations are performed to determine the effectiveness of the enhancements. A cost function formulation and a Bayesian based alternative are also presented and evaluated. The cost function implementation uses a different method to determine the optimal set points for the subsequent processing steps than the other implementations use. Simulations are used to compare the cost function formulation with the other methods presented. The Bayesian implementation addresses the stochastic nature of the manufacturing process by dealing with the probabilities of events occurring. A simulation of the Bayesian algorithm is preformed and the algorithms limitations are discussed.

The goal of this research was to examine the relationship between dislocation density and in-plane residual stress in edge-defined film-fed growth (EFG) silicon wafers. Previous research has shown models for linking dislocation density and residual stress based on temperature gradient parameters during crystal growth. Residual stress and dislocation density have a positive relationship for wafers with very low dislocation density such as Cz wafers. There has been limited success in experimental verifications of residual stress for EFG wafers, without any reference to dislocation density. No model of stress relaxation has been verified experimentally in post production wafers. A model that assumes stress relaxation and links residual stress and dislocation density without growth parameters will be introduced here. Dislocation density and predominant grain orientation of EFG wafers have been measured by the means of chemical etching/optical microscope and x-ray diffraction, respectively. The results have been compared to the residual stress obtained by a near infrared transmission polariscope. A model was established to explain the results linking dislocation density and residual stress in a randomly selected EFG wafer.

Thesis (M.S.)--San Jose State University, 1995. / Adviser: Guna S. Selvaduray. Includes bibliographical references.

We investigate some of the mechanical design factors of wafers and the effect on strength. Thin, solid, pre-stressed films are proposed as a means to improve the bulk mechanical properties of a wafer. Three-point bending was used to evaluate the laser scribe density and chemical processing effect on wafer strength. Drop and strike tests were employed to investigate the edge bevel profile effect on the mechanical properties of the wafer. To characterize the effect of thin films on strength, one-micron ceramic films were deposited on wafers using PECVD. Coated samples were prepared by cleaving and were tested using four-point bending. Film adhesion was characterized by notched four-point bending. RBS and FTIR were used to obtain film chemistry, and nanoindentation was used to investigate thin film mechanical properties. A stress measurement gauge characterized residual film stress. Mechanical properties of the wafers correlated to the residual stress in the film.

Semiconductor devices are built using hyperpure silicon and very controlled levels of doping to create desired electrical properties. Contamination can alter these precisely controlled electrical properties that can render the device non-functional or unreliable. It is desirable to determine what impurities impact the device and control them. This study consists of four parts: a) determination of acceptable SCI (Standard Clean 1) bath contamination levels using VPD-DSE-GFAAS (Vapor Phase Decomposition Droplet Surface Etching Graphite Furnace Atomic Absorption Spectroscopy), b) copper deposition from various aqueous HF solutions, c) anion contamination from fluoropolymers used in chemical handling and d) metallic contamination from fluoropolymers and polyethylene used in chemical handling. A technique was developed for the determination of metals on a silicon wafer source at low levels. These levels were then correlated to contamination levels in a SCI bath. This correlation permits the determination of maximum permissible solution contaminant levels. Copper contamination is a concern for depositing on the wafer surface from hydrofluoric acid solutions. The relationship between copper concentration on the wafer surface and hydrofluoric acid concentration was determined. An inverse relationship exists and was explained by differences in diffusion rates between the differing copper species existing in aqueous hydrofluoric acid solutions. Finally, sources of contamination from materials used in chemical handling was studied. The predominant anion contamination from fluoropolymers was found to be fluorides. Metallic contamination from fluoropolymers and polyethylene was also studied. The primary metal contamination comes from the actual fabrication of the polymer and not from the polymer resin.

Photovoltaic manufacturing is material intensive with the cost of crystalline silicon wafer, used as the substrate, representing 40% to 60% of the solar cell cost. Consequently, there is a growing trend to reduce the silicon wafer thickness leading to new technical challenges related to manufacturing. Specifically, wafer breakage during handling and/or transfer is a significant issue. Therefore improved methods for breakage-free handling are needed to address this problem. An important pre-requisite for realizing such methods is the need for fundamental understanding of the effect of handling device variables on the deformation, stresses, and fracture of crystalline silicon wafers. This knowledge is lacking for wafer handling devices including the Bernoulli gripper, which is an air flow nozzle based device. A computational fluid dynamics model of the air flow generated by a Bernoulli gripper has been developed. This model predicts the air flow, pressure distribution and lifting force generated by the gripper. For thin silicon wafers, the fluid model is combined with a finite element model to analyze the effects of wafer flexibility on the equilibrium pressure distribution, lifting force and handling stresses. The effect of wafer flexibility on the air pressure distribution is found to be increasingly significant at higher air flow rates. The model yields considerable insight into the relative effects of air flow induced vacuum and the direct impingement of air on the wafer on the air pressure distribution, lifting force, and handling stress. The latter effect is found to be especially significant when the wafer deformation is large. In addition to silicon wafers, the model can also be used to determine the lifting force and handling stress produced in other flexible materials. Finally, a systematic approach for the analysis of the total stress state (handling plus residual stresses) produced in crystalline silicon wafers and its impact on wafer breakage during handling is presented. Results confirm the capability of the approach to predict wafer breakage during handling given the crack size, location and fracture toughness. This methodology is general and can be applied to other thin wafer handling devices besides the Bernoulli gripper.

This dissertation focuses on high-performance LC-tank CMOS VCO design at 2 GHz. The high-Q inductors are realized using wiring metal lines in advanced packages. Those inductors are used in the resonator of the VCO to achieve low phase noise, low power consumption, and a wide frequency tuning range. In this dissertation, a fine-pitch ball-grid array (FBGA) package, a multichip module (MCM)-L package, and a wafer-level package (WLP) are incorporated to realize the high-Q inductor. The Q-factors of inductors embedded in packages are compared to those of inductors monolithically integrated on Si and GaAs substrates. All the inductors are modeled with a physical, simple, equivalent two-port model for the VCO design as well as for phase noise analysis. The losses in an LC-tank are analyzed from the phase noise perspective. For the implementation of VCOs, the effects of the interconnection between the embedded inductor and the VCO circuit are investigated. The VCO using the on-chip inductors is designed as a reference. The performance of VCOs using the embedded inductor in a FBGA and a WLP is compared with that of a VCO using the on-chip inductor. The VCO design is optimized from the high-Q perspective to enhance performance. Through this optimization, less phase noise, lower power consumption, and a wider frequency tuning range are obtained simultaneously.