The thesis demonstrates a low-cost, low-bandwidth and low-resolution Analog-to- Digital Converter(ADC) in 0.35 um CMOS Process. A second-order Sigma-Delta modulator is used as the basis of the A/D Converter. A Semi-Uniform quantizer is used with the modulator to take advantage of input distributions that are dominated by smaller-amplitude signals e.g. Audio, Voice and Image-sensor signals. A Single-bit feedback topology is used with a multi-bit quantizer in the modulator. This topology avoids the use of a multi-bit DAC in the feedback loop – hence the system does not need to use digital correction techniques to compensate for a multi-bit DAC nonlinearity. High-Level Simulations of the second-order Sigma-Delta modulator single-bit feedback topology along with a Semi-Uniform quantizer are performed in Cadence. Results indicate that a 5-bit Semi-Uniform quantizer with a Over-Sampling Ratio of 32, can achieve a resolution of 10 bits, in addition, a semi-uniform quantizer exhibits a 5-6 dB gain in SNR over its uniform counterpart for input amplitudes smaller than –10 dB. Finally, this system is designed in 0.35um CMOS process.

Comparator is the main building block in an ADC architecture. Main purpose of the comparator is to compare a signal with a reference signal and produce an output depending on whether the input signal is greater or smaller than reference. Many architectures for comparators exist for various purposes. In this thesis, Latched comparator architecture is used for sigma delta modulator. This particular design has two main characteristics that are very important for sigma delta application. First characteristic is the cancellation of memory effect which increases the speed and reliability of the system and the second is, with this architecture, high sensitivity can be achieved. The design and implementation of lathed comparator for sigma delta modulator is presented in this thesis work. Various non-linearities and performance parameters are discussed in detail. Practical implementation and circuit design issues are highlighted to achieve maximum sensitivity along with reasonable speed and accuracy.

The sigma-delta modulator is a popular signal amplitude quantization error (or noise) shaper used in oversampling analogue-to-digital and digital-to-analogue converter systems. The shaping of the noise frequency spectrum is performed by feeding back the quantization errors through a time delay element filter and feedback loop in the circuit, and by the addition of a possible stochastic dither signal at the quantizer. The aim in audio systems is to limit audible noise and distortions in the reconverted analogue signal. The formulation of the sigma-delta modulator as a discrete dynamical system provides a useful framework for the mathematical analysis of such a complex nonlinear system, as well as a unifying basis from which to consider other systems, from pseudorandom number generators to stochastic resonance processes, that yield equivalent formulations. The study of chaos and other complementary aspects of internal dynamical behaviour in previous research has left important issues unresolved. Advancement of this study is naturally facilitated by the dynamical systems approach. In this thesis, the general order feedback/feedforward sigma-delta modulator with multi-bit quantizer (no overload) and general input, is modelled and studied mathematically as a dynamical system. This study employs pertinent topological methods and relationships, which follow centrally from the symmetry of the circle map interpretation of the error state space dynamcis. The main approach taken is to reduce the nonlinear system into local or special case linear systems. Systems of sufficient structure are shown to often possess structured random, or random-like behaviour. An adaptation of Devaney's definition of chaos is applied to the model, and an extensive investigation of the conditions under which the associated chaos conditions hold or do not hold is carried out. This seeks, in part, to address the unresolved research issues. Chaos is shown to hold if all zeros of the noise transfer function lie outside the unit circle of radius two, provided the input is either periodic or persistently random (mod delta). When the filter satisfies a certain continuity condition, the conditions for chaos are extended, and more clear cut classifications emerge. Other specific chaos classifications are established. A study of the statistical properties of the error in dithered quantizers and sigma-delta modulators is pursued using the same state space model. A general treatment of the steady state error probability distribution is introduced, and results for predicting uniform steady state errors under various conditions are found. The uniformity results are applied to RPDF dithered systems to give conditions for a steady state error variance of delta squared over six. Numerical simulations support predictions of the analysis for the first-order case with constant input. An analysis of conditions on the model to obtain bounded internal stability or instability is conducted. The overall investigation of this thesis provides a theoretical approach upon which to orient future work, and initial steps of inquiry that can be advanced more extensively in the future.

Uppsatsens tema är hur man kan arbeta med kvalitetsstyrning och kvalitetsutveckling inom fallföretaget Genevads. I uppsatsen studeras förekomsten av kvalitetsbrister i produktionsprocessen. Diagnosen leder fram till uppsatsens andra steg där vi söker efter bättre kvalitetstyrning och kvalitetsutveckling. Teoretiskt fokus ligger på "lean six sigma" och kvalitetsutveckling enligt "lean"-principerna.

A dual-mode second-order Multirate Multibit Sigma Delta (MM-SD) modulator is implemented in a 90nm digital CMOS process for application in the baseband path of RF receivers. Low power consumption is achieved through a new integrator structure and a dedicated timing scheme along with aggressive capacitor scaling in the second stage of the modulator loop. Fabricated prototype achieves 68.6dB peak Signal-to-Noise and Distortion ratio (SNDR) in the 200 kHz GSM band and requires 1.1mA of total current from a 1.5V supply. This dual-mode design also achieves 42.8dB SNDR in the 1.94 MHz WCDMA band with only 1.9mA of total current consumption.

Abstract SMT process is the most critical process to influence products quality in electronic assembly house process. Especially,the solder paste printing control is the key process to determine the yield rate of SMT quality. To own the capability to control quality of solder paste printing is the important thing what assembly house have to face it¡C For the purpose of gaining good SMT yield & solder paste printing stability ,the study use six sigma management technique & procedure (DMAIC--Define¡BMeasure¡BAnalyze¡BImprove & Control) make the main factors of solder paste printing¡Aincluding Printing speed¡BScraper pressure¡BStencil clean frequency¡Ato be the experiment factors of DOE(Design of Experiment)¡CThe DOE minimize the experiment number of times and provide a way of 2 levels factorial design combine RSM(Response Surface Methodology) experiment to get the optimization combination of factors¡¦ levels. Then evaluate how the optimization combination of factor levels to influence the quality of SMT¡C The study final found that there are a surprised & satisfied result on SMT yield improvement caused by optimization combination of factors¡¦ levels which 2 levels factorial design combine RSM experiment generated. It can provide the procedure & methodology for SMT assembly house reference to improve yield rate .

After signing ECFA (Economic Cooperation Framework Agreement), all of the fundamental industries of Taiwan are going to face the serious impact. As a result, Refractory Industry can¡¦t skip out the pool. Although refractory industry still undercover by government policy, Chinese products are going to sweep across Taiwan market with price advantage after Taiwan and China government signed the significant economic agreement. Some companies consider reducing cost and improve quality via automatic manufacturing procedures. However, the further question is that can automation really improve the producing efficiency and reduce manpower demand? That will be the main discussion subject of this research. The research concentrates on the planning, construction and actual benefit contrasting of press machine in six months and take 6 Sigma and TPS (Toyota Production System) as the research method. We estimate that reasonable investment can create producing efficiency. We are going to compare the benefits of same press machine with and without automatic manufacturing procedure and also different types of press machine to produce same product in same condition at the same period. This research demonstrated that partial equipment automation or single old equipment automation doesn¡¦t really increase the production efficiency. The result of decreasing the cost of production, such as the cost of manpower, is not notable. In order to achieve the objective goal, we still need to inspect the whole manufacturing procedure, equipment assembling in detail, and arrange the perfect combination of people and machines, then the most synergy could be happened. As for the manufacture management concept and practice, we should abandon fixed frame, thought, and keep manufacture procedure improving. All in all, the improvement of concept and practice, the effect could be far over the benefit of auto equipment, the cost could be much lower than the investments of the equipments. Replacing the manpower by mechanical arms, it indeed reaches the goal of few staff trend and lowers the accident ratio. Few staff environment will cause the operator¡¦s working stability, improve the phenomenon of losing labor.

The thesis proposes a third order continuous-time sigma delta modulator used in GSM. We used a special 1.5bit quantizer, and to use its three different states to reach a differential feedback path. That can improve the resolution of our circuit. Oversampling and noise shaping are two keys of sigma delta modulator. In structure, the continuous-time features can reduce power consumption. The proposed sigma delta modulator uses TSMC 0.35 m CMOS process and its sampling frequency is 10.8MHz, bandwidth is200KHz and oversampling ratio is 32.

With the increasingly fierce industry competition and customers demanding higher quality products or service at the same time, top-notch companies and academic communities have continuously evolved many tools, methods, standards for seeking the improvements in the operational performances to bridge gaps in customers¡¦ expectations. Among these practices, Six Sigma has been recognized as a systematic and structured methodology that attempts to improve process capabilities through its focus on customers¡¦ needs. It has been described as an approach for organizational changes, which incorporates elements with quality management and business process re-engineering. However, adopting Six Sigma into effect is a costly investment, assessments of implementation performance shall be prudently made. This study is based on the perspectives of institutional theory, implementation climate, innovation-values fit, and innovation-abilities fit with some modified measures from the viewpoints of large manufacturing companies. 323 samples were taken by stratified random sampling. The major findings are (1) Normative pressure might influence the employees¡¦ intentions of innovation implementation, but not enough to cause real actions. (2) The influence of an organization¡¦s climate upon the innovation implementation is not evident. (3) Innovation -value fit has directly influenced upon the innovation implementation and can directly enhance the performance improvements. (4) The influence of Employees¡¦ current abilities upon innovation implementation is evident.

This thesis consists of two topics: A 2.45 GHz ZigBee Receiver Frontend design for home energy-saving systems and a Delta-Sigma ADC with constant-gm amplifier for Battery Management Systems (BMS). A 2.45 GHz ZigBee Receiver Frontend for home energy-saving systems is pre-sented in the first part of this thesis. The proposed ZigBee receiver can be used in areas where wireline solutions are hard to be realized. By employing an LNA at the very frontend of the receiver, the gain is simulated to be 17.376 dB at 2.45 GHz. Besides, by using the double-balanced Gilbert mixer with a current bleeding MOS transistor, the NF and the IIP3 of the mixer are only 5.074 dB and -7.234 dB, respectively. To reduce the phase noise of the receiver, a fractional-N frequency synthesizer with a complementary cross-coupled VCO is adopted. The phase noise of the fractional-N frequency synthe-sizer is 137.7 dBc/Hz. The proposed circuit is carried out and measured on silicon using the standard TSMC 0.18 £gm CMOS process. In the second topic, a Delta-Sigma ADC with constant-gm amplifier is presented. The proposed ADC is particularly designed for the voltage detection circuit in BMS. A constant-gm amplifier is also presented to resolve the nonlinearity of the amplifier de-grading the performance of Delta-Sigma modulator, which is the frontend of the Del-ta-Sigma ADC. With the 4 KHz signal bandwidth, 512 KHz sampling frequency, and 128 oversampling rate, it shows a 85.2 dB SNR, and 12-bit resolution. The backend of the ADC is the decimator, which reduces the sampling frequency compliant with the Nyquist rate rule. The decimator is realized by Verilog code and verified by FPGA. By following the mixed-signal flow, the ADC is realized on a single chip using the standard TSMC 0.25 £gm 60V HV CMOS process.