Continuous-time filters are critical components in the implementation of large bandwidth, high frequency, and high resolution continuous-time (CT) sigma-delta (ΣΔ) analog-to-digital converters (ADCs). The loop filter defines the noise-transfer function (NTF) and hence the quantization noise-shaping behavior of the ΣΔ modulator, and becomes the most critical performance determining part in ΣΔ ADC. This thesis work presents the design considerations for the loop filter in low-pass CT ΣΔ ADC with 12-bits resolution in 25MHz bandwidth and low power consumption using 0.18μm CMOS technology. Continuous-time filters are more suitable than discrete-time filters due to relaxed amplifier bandwidth requirements for high frequency ΣΔ ADCs. A fifth-order low-pass filter with cut-off frequency of 25 MHz was designed to meet the dynamic range requirement of the ADC. An active RC topology was chosen for the implementation of the loop filter, which can provide high dynamic range required by the ΣΔ ADC. The design of a summing amplifier and a novel method for adjusting the group delay in the fast path provided by a secondary feedback DAC of the ΣΔ ADC are presented in detail. The ADC was fabricated using Jazz 0.18μm CMOS technology. The implementation issues of OTAs with high-linearity and low-noise performance suitable for the broadband ADC applications are also analyzed in this work. Important design equations pertaining to the linearity and noise performance of the Gm-C biquad filters are presented. A Gm-C biquad with 100MHz center frequency and quality factor 10 was designed as a prototype to confirm with the theoretical design equations. Transistor level circuit implementation of all the analog modules was completed in a standard 0.18μm CMOS process.

The emergence of bandwidth-intensive services has created a need for high speed and high resolution data converters. Towards this end, system level design of a continuous-time sigma-delta modulator achieving 11 bits resolution over 100 MHz signal bandwidth by using a feed-forward topology is presented. The system is first built in the Simulink environment in MATLAB. The building blocks in the loop filter are modeled with non-idealities, and specifications for these blocks are obtained by simulations. An operational transconductor amplifier (OTA) with 100 mS transconductance, 70 dB linearity, and 34.2 mW power dissipation is designed to be used in the loop filter. Simulation results indicate that the 5th order loop filter implemented in the feed-forward architecture in transistor level shows lower power consumption, 105 mW, compared to the loop filter implemented by feedback architecture, 152 mW.

In the first, a time-variant modulus phase lock loop(PLL) model is established. Applying the model, Theorems of fractional-N synthesizers are introduced. We also explain theorems and simulations of Closed-Loop Modulation and Two-Point Delta Sigma Modulation with the model. In the end, a 2.4GHz FHSS transmitter using Two-Point Delta Sigma Modulation which meets Bluetooth specifications is demonstrated.

Bandpass sigma-delta modulators combine oversampling and noise shaping to get very high resolution in a limited bandwidth. They are widely used in applications that require narrowband high-resolution conversion at high frequencies. In recent years interests have been seen in wireless system and software radio using sigma-delta modulators to digitize signals near the front end of radio receivers. Such applications necessitate clocking the modulators at a high frequency (MHz or above). Therefore a loop filter is required in continuous-time circuits (e.g., using transconductors and integrators) rather than discretetime circuits (e.g., using switched capacitors) where the maximum clocking rate is limited by the bandwidth of Opamp, switch’s speed and settling-time of the circuitry. In this work, the design of a CMOS fourth-order bandpass sigma-delta modulator clocking at 500 MHz for direct conversion of narrowband signals at 125 MHz is presented. A new calibration scheme is proposed for the best signal-to-noise-distortion-ratio (SNDR) of the modulator. The continuous-time loop filter is based on Gm-C resonators. A novel transconductance amplifier has been developed with high linearity at high frequency. Qfactor of filter is enhanced by tunable negative impedance which cancels the finite output impendence of OTA. The fourth-order modulator is implemented using 0.35 mm triplemetal standard analog CMOS technology. Postlayout simulation in CADENCE demonstrates that the modulator achieves a SNDR of 50 dB (~8 bit) performance over a 1 MHz bandwidth. The modulator’s power consumption is 302 mW from supply power of ± 1.65V.

In this thesis, a switched-current integrator with active amplifier feedback and dummy switch is proposed to increase the operation speed and reduce the non-ideal effects in traditional switched-current circuit. The active amplifier is designed in low gain and high bandwidth so that the oscillation can be avoided. We improve the operation speed and transmission error by the active amplifier feedback and reduce the CFT error by the dummy switch so that high resolution can be achieved. Then we apply the proposed integrator to the switched-current sigma-delta modulator. The sigma-delta modulator is simulated using TSMC 0.35£gm CMOS process with 3.3V power supply. We obtain 67dB PSNR, 66dB dynamic range(DR), and 40KHz bandwidth. The sampling frequency is 10.24MHz, the power supply is 3.3V and the power consumption is 19mW.

La presente tesis, trata sobre el uso de la metodología Six Sigma para la optimización de un área de mantenimiento de planta. Al estar usando como referencia una metodología los capítulos que aquí se presentan siguen el esquema DMAMC, donde se Define el problema, se Mide el proceso, se Analiza la causa raíz, se Mejora el proceso y por ultimo se Controla el mismo por medio de indicadores de gestión. En la etapa de Medir se implementan diferentes ganancias rápidas al proceso; esto no implica que la metodología haya cumplido su objetivo, six sigma busca mejorar aquellas causas raíz que no están a la simple vista de las personas que trabajan en el área o gerencia. Por ultimo la presente tesis propone mejoras así como los controles que deben de llevarse en el área de mantenimiento de planta. Es aquí donde se ve el compromiso de la gerencia y la jefatura del área con el proyecto ya que de ellos depende que las mejoras y el control caminen y den paso a la optimización del proceso.

<p>Uppsatsens tema är hur man kan arbeta med kvalitetsstyrning och kvalitetsutveckling inom fallföretaget Genevads. I uppsatsen studeras förekomsten av kvalitetsbrister i produktionsprocessen. Diagnosen leder fram till uppsatsens andra steg där vi söker efter bättre kvalitetstyrning och kvalitetsutveckling. Teoretiskt fokus ligger på "lean six sigma" och kvalitetsutveckling enligt "lean"-principerna.</p>

This dissertation presents a novel [delta sigma] analog-to-digital converter architecture which replaces the operational amplifier-based integrator with a pair of tunable oscillators. A switched-capacitor V-I converter is used to combine the input voltage with a feedback DAC output and convert it into a current for two pseudo-differential current-controlled oscillators. The oscillator outputs are counted with a digital counter, and a digital back-end [delta sigma] modulator is used to truncate the high-resolution counter outputs for the feedback DAC path. This architecture has compelling advantages in deep sub-micron and emerging technologies where supply voltages are decreasing to a point that traditional analog architectures are no longer feasible. Additionally, this architecture takes advantage of the increased speed in these short-channel technologies. Measured results on a 6.08mW prototype in TSMC 0.18um achieving 63.5dB in a 2MHz bandwidth are presented. / text

This report describes the major steps used in the Army’s LSS methodology, provides a brief overview of the Unaccompanied Personnel Housing and the Army Family Housing and briefly describes some of the initial steps intended to start improving the process. In the improvement phase, two detailed models (The EOQ Model and the Hadley and Whitin (Q,r) Model) used for inventory management are discussed. This report also provides a series of recommendations that include suggestions for baseline inventory levels, some ideas for future data collection, example improvements to some data input sheets as well as a few tasks for UPH and AFH managers to reduce cost and improve the overall efficiency of the system. / text

Integrated temperature sensors play an important role in enhancing the performance of on-chip power and thermal management systems in today's highly-integrated system-on-chip (SoC) platforms, such as microprocessors. Accurate on-chip temperature measurement is essential to maximize the performance and reliability of these SoCs. However, due to non-uniform power consumption by different functional blocks, microprocessors have fairly large thermal gradient (and variation) across their chips. In the case of multi-core microprocessors for example, there are task-specific thermal gradients across different cores on the same die. As a result, multiple temperature sensors are needed to measure the temperature profile at all relevant coordinates of the chip. Subsequently, the results of the temperature measurements are used to take corrective measures to enhance the performance, or save the SoC from catastrophic over-heating situations which can cause permanent damage. Furthermore, in a large multi-core microprocessor, it is also imperative to continuously monitor potential hot-spots that are prone to thermal runaway. The locations of such hot spots depend on the operations and instruction the processor carries out at a given time. Due to practical limitations, it is an overkill to place a big size temperature sensor nearest to all possible hot spots. Thus, an ideal on-chip temperature sensor should have minimal area so that it can be placed non-invasively across the chip without drastically changing the chip floor plan. In addition, the power consumption of the sensors should be very low to reduce the power budget overhead of thermal monitoring system, and to minimize measurement inaccuracies due to self-heating. The objective of this research is to design an ultra-small size and ultra-low power temperature sensor such that it can be placed in the intimate proximity of all possible hot spots across the chip. The general idea is to use the leakage current of a reverse-bias p-n junction diode as an operand for temperature sensing. The tasks within this project are to examine the theoretical aspect of such sensors in both Silicon-On-Insulator (SOI), and bulk Complementary Metal-Oxide Semiconductor (CMOS) technologies, implement them in deep sub-micron technologies, and ultimately evaluate their performances, and compare them to existing solutions. / text