La miniaturisation des gravures des transistors résulte en une augmentation de la sensibilité aux soft-erreurs des circuits intégrés face aux particules énergétiques présentes dans l’environnement dans lequel ils opèrent. Une expérimentation, présentée au cours de cette thèse, concernant l'étude de la sensibilité face aux soft-erreurs, dans l'environnement réel, des mémoires SRAM provenant de deux générations de technologies successives, a mis en évidence la criticité de cette thématique. Cela pour montrer la nécessité de l'évaluation des circuits faces aux effets des radiations, surtout les circuits commerciaux qui sont de plus en plus utilisés dans les applications spatiales et avioniques et même dans les hautes altitudes, afin de trouver les méthodologies permettant leurs durcissements. Plusieurs méthodes d'injection de fautes, ayant pour but l'évaluation de la sensibilité des circuits intégrés face aux soft-erreurs, ont été le sujet de plusieurs recherches. Les travaux réalisés au cours de cette thèse ont eu pour but le développement d'une méthode automatisable, avec son outil, permettant l'émulation des effets des radiations sur des circuits dont on dispose de leurs codes HDL. Cette méthode, appelée NETFI (NETlist Fault Injection), est basée sur la manipulation de la netlist du circuit synthétisé pour permettre l'injection de fautes de types SEU, SET et Stuck_at. NETFI a été appliquée sur plusieurs architectures pour étudier ses potentialités ainsi que son efficacité. Une étude sur un algorithme tolérant aux fautes, dit self-convergent, exécuté par un processeur LEON3, a été aussi présenté dans le but d'effectuer une comparaison des résultats issus de NETFI avec ceux issus d'une méthode de l'état de l'art appelée CEU (Code Emulated Upset). / Reducing the dimensions of transistors increases the soft-errors sensitivity of integrated circuits to energetic particles present in the environments in which they operate. An experiment, presented in this thesis, aiming to study soft-errors sensitivity, in real environment, of SRAM memories issued from two successive technologies, put in evidence the criticality of this thematic. This is to show the need to evaluate circuit's sensitivity to radiation effects, especially commercial circuits that are used more and more for space and avionic applications and even at high altitudes, in order to find the appropriate hardening methodologies. Several fault-injection methods, aiming at evaluating the sensitivity to soft-errors of integrated circuits, were goals for many researches. In this thesis was developed an automated method, and its corresponding tool, allowing the emulation of radiation effects on HDL-based circuits. This method, so-called NETFI (NETlist Fault-Injection), is based on modifying the netlist of the synthesized circuit to allow injecting faults of different types (SEU, SET and Stuck_at). NETFI was applied on different architectures in order to assess its efficiency and put in evidence its capabilities. A study on a fault-tolerant algorithm, so-called self-convergent, executed by a LEON3 processor, was also presented in order to perform an objective comparison between the results issued from NETFI and those issued from another state-of-the-art method, called CEU (Code Emulated Upset).

Este trabalho consiste no estudo e análise da suscetibilidade a efeitos da radiação em projetos de circuitos gerados por ferramenta de Síntese de Alto Nível para FPGAs (Field Programmable Gate Array), ou seja, circuitos programáveis e sistemas em chip, do inglês System-on-Chip (SOC). Através de um injetor de falhas por emulação usando o ICAP (Internal Configuration Access Port) localizado dentro do FPGA é possível injetar falhas simples ou acumuladas do tipo SEU (Single Event Upset), definidas como perturbações que podem afetar o funcionamento correto do dispositivo através da inversão de um bit por uma partícula carregada. SEU está dentro da classificação de SEEs (Single Event Effects), efeitos transitórios em tradução livre, podem ocorrer devido a penetração de partículas de alta energia do espaço e do sol (raios cósmicos e solares) na atmosfera da Terra que colidem com átomos de nitrogênio e oxigênio resultando na produção de partículas carregadas, na grande maioria nêutrons. Dentro deste contexto além de analisar a suscetibilidade de projetos gerados por ferramenta de Síntese de Alto Nível, torna-se relevante o estudo de técnicas de redundância como TMR (Triple Modular Redundance) para detecção, correção de erros e comparação com projetos desprotegidos verificando a confiabilidade. Os resultados mostram que no modo de injeção de falhas simples os projetos com redundância TMR demonstram ser efetivos. Na injeção de falhas acumuladas o projeto com múltiplos canais apresentou melhor confiabilidade do que o projeto desprotegido e com redundância de canal simples, tolerando um maior número de falhas antes de ter seu funcionamento comprometido. / This work consists of the study and analysis of the susceptibility to effects of radiation in circuits projects generated by High Level Synthesis tool for FPGAs Field Programmable Gate Array (FPGAs), that is, system-on-chip (SOC). Through an emulation fault injector using ICAP (Internal Configuration Access Port), located inside the FPGA, it is possible to inject single or accumulated failures of the type SEU (Single Event Upset), defined as disturbances that can affect the correct functioning of the device through the inversion of a bit by a charged particle. SEU is within the classification of SEEs (Single Event Effects), can occur due to the penetration of high energy particles from space and from the sun (cosmic and solar rays) in the Earth's atmosphere that collide with atoms of nitrogen and oxygen resulting in the production of charged particles, most of them neutrons. In this context, in addition to analyzing the susceptibility of projects generated by a High Level Synthesis tool, it becomes relevant to study redundancy techniques such as TMR (Triple Modular Redundancy) for detection, correction of errors and comparison with unprotected projects verifying the reliability. The results show that in the simple fault injection mode TMR redundant projects prove to be effective. In the case of accumulated fault injection, the multichannel design presented better reliability than the unprotected design and with single channel redundancy, tolerating a greater number of failures before its operation was compromised.

Conversores A/D do tipo aproximações sucessivas (SAR) baseados em redistribuição de carga são frequentemente utilizados em aplicações envolvendo a aquisição de sinais, principalmente as que exigem um baixo consumo de área e energia e boa velocidade de conversão. Esta topologia está presente em diversos dispositivos programáveis comerciais, como também em circuitos integrados de propósito geral. Tais dispositivos, quando expostos a ambientes suscetíveis a radiação, como é o caso de aplicações espaciais, estão sujeitos à colisão com partículas capazes de ionizar o silício. Estes podem causar falhas temporárias, como um efeito transiente, uma inversão de bit em um elemento de memória, ou até mesmo danos permanentes no circuito. Este trabalho visa descrever o comportamento do conversor SAR baseado em redistribuição de carga após a ocorrência de efeitos transientes causados por radiação, por meio de simulação SPICE. Tais efeitos podem causar falhas nos componentes da topologia: chaves, lógica de controle e comparador. Estes são propagados por todo o estágio de conversão, devido à sua característica sequencial de conversão. Por fim, uma discussão sobre as possíveis técnicas de mitigação de falhas para esta topologia é apresentada. / Successive Approximation Register (SAR) Analog to Digital Converters (ADCs) based on charge redistribution are frequently used in data acquisition systems, especially those requiring low power and low area, and good conversion speed. This topology is present on several mixed-signal programmable devices. These devices, when exposed to harsh environments, such as radiation, which is the case for space applications, are prone to Single Event Effects (SEEs). These effects may cause temporary failures, such as transient effects or memory upsets or even permanent failures on the circuit. This work presents the behavior of this type of converter after the occurrence of a transient fault on the circuit, by means of SPICE simulations. These transient faults may cause an inversion on the conversion due to a transient on the control logic of the switches, or a charge or discharge of the capacitors when a transient occur on the switches, as well as a failure on the comparator, which may propagate to the remainder stages of conversion, due to the sequential nature of the converter. A discussion about the possible fault mitigation techniques is also presented.

Os efeitos da radiação ionizante em dispositivos eletrônicos é uma preocupação crescente na tecnologia de semicondutores, especialmente devido à contínua redução dos dispositivos e ainda maior, quando são destinados para uso em ambientes agressivos com alta radiação, tais como missões espaciais, aceleradores de partículas ou reatores nucleares. Dentre os vários efeitos causados pela radiação ionizante em dispositivos eletrônicos está aquele devido à Dose Acumulada (Total Ionizing Dose - TID), o qual a acumulação de danos de radiação no dispositivo muda seu funcionamento normal. O TID causado por fótons em transístores já foi estudado no Brasil, mas o efeito de prótons num transistor bipolar, apresentado neste trabalho é um trabalho pioneiro no país. As curvas características de um transistor 2N3733 foram medidas antes, durante e após a irradiação de prótons entre 1,5 e 3,8 MeV, para quantificar as alterações das especificações elétricas do dispositivo. Nestas energias, há uma correlação direta entre a mudança na resposta elétrica e a energia do próton, exceto em algumas energias específicas, onde o pico de Bragg ocorreu perto das junções ou no meio do cristal de silício, demonstrando a importância da correta caracterização da camada de passivação em estudos de TID em dispositivos eletrônicos. A recuperação dos transistores irradiados após o recozimento a 50°C durante 8 horas também foi maior para aqueles irradiados nessas energias. Existe um limite superior de dose para o qual não foi observada alteração significativa do transistor. Este limite, da ordem de Grad, excede a maioria das aplicações em ambientes terrestres, mas está dentro do intervalo esperado para missões espaciais a Júpiter ou em grandes aceleradores de partículas. / The effect of ionizing radiation on electronic devices is a growing concern in semiconductor technology, especially due to the continuous reduction of the devices and even greater when they are intended for use in aggressive environments with high radiation, such as space missions, particle accelerators or nuclear reactors. Among the various effects caused by ionizing radiation on electronic devices are the effects due to Total Ionizing Dose (TID), in which the accumulation of radiation damage in the device changes its normal functioning. The TID caused by photons has already been studied in Brazil, but the effect of protons on a bipolar transistor, presented in this work is a pioneer work in the country. The characteristic curves of a 2N3733 transistor were measured before, during and after proton irradiation between 1.5 and 3.8 MeV, to quantify changes of the electrical specifications of the device. At these proton energies, there is a direct correlation between the change in the electric response to the proton energy, except at some specific energies where the Bragg peak occurred near the junctions or in the middle of the silicon crystal, demonstrating the importance of the correct characterization of the passivation layer in TID studies of electronic devices. The recovery of transistors irradiated after annealing at 50 ° C for 8 hours was also higher for those irradiated at these energies. There is an upper dose limit for which no alteration of the transistor was observed. This limit, of the order of Grad, exceeds most applications in terrestrial environments, but is within the expected range for space missions to Jupiter or large particle accelerators.

Conversores A/D do tipo aproximações sucessivas (SAR) baseados em redistribuição de carga são frequentemente utilizados em aplicações envolvendo a aquisição de sinais, principalmente as que exigem um baixo consumo de área e energia e boa velocidade de conversão. Esta topologia está presente em diversos dispositivos programáveis comerciais, como também em circuitos integrados de propósito geral. Tais dispositivos, quando expostos a ambientes suscetíveis a radiação, como é o caso de aplicações espaciais, estão sujeitos à colisão com partículas capazes de ionizar o silício. Estes podem causar falhas temporárias, como um efeito transiente, uma inversão de bit em um elemento de memória, ou até mesmo danos permanentes no circuito. Este trabalho visa descrever o comportamento do conversor SAR baseado em redistribuição de carga após a ocorrência de efeitos transientes causados por radiação, por meio de simulação SPICE. Tais efeitos podem causar falhas nos componentes da topologia: chaves, lógica de controle e comparador. Estes são propagados por todo o estágio de conversão, devido à sua característica sequencial de conversão. Por fim, uma discussão sobre as possíveis técnicas de mitigação de falhas para esta topologia é apresentada. / Successive Approximation Register (SAR) Analog to Digital Converters (ADCs) based on charge redistribution are frequently used in data acquisition systems, especially those requiring low power and low area, and good conversion speed. This topology is present on several mixed-signal programmable devices. These devices, when exposed to harsh environments, such as radiation, which is the case for space applications, are prone to Single Event Effects (SEEs). These effects may cause temporary failures, such as transient effects or memory upsets or even permanent failures on the circuit. This work presents the behavior of this type of converter after the occurrence of a transient fault on the circuit, by means of SPICE simulations. These transient faults may cause an inversion on the conversion due to a transient on the control logic of the switches, or a charge or discharge of the capacitors when a transient occur on the switches, as well as a failure on the comparator, which may propagate to the remainder stages of conversion, due to the sequential nature of the converter. A discussion about the possible fault mitigation techniques is also presented.

The interaction of radiation with integrated circuits can provoke transient faults due to the deposit of charge in sensitive nodes of transistors. Because of the decrease the size in the process technology, charge sharing between transistors placed close to each other has been more and more observed. This phenomenon can lead to multiple transient faults. Therefore, it is important to analyze the effect of multiple transient faults in integrated circuits and investigate mitigation techniques able to cope with multiple faults. This work investigates the effect known as single-event-induced charge sharing in integrated circuits. Two main techniques are analyzed to cope with this effect. First, a placement constraint methodology is proposed. This technique uses placement constraints in standard cell based circuits. The objective is to achieve a layout for which the Soft-Error Rate (SER) due charge shared at adjacent cell is reduced. A set of fault injection was performed and the results show that the SER can be minimized due to single-event-induced charge sharing in according to the layout structure. Results show that by using placement constraint, it is possible to reduce the error rate from 12.85% to 10.63% due double faults. Second, Triple Modular Redundancy (TMR) schemes with different levels of granularities limited by majority voters are analyzed under multiple faults. The TMR versions are implemented using a standard design flow based on a traditional commercial standard cell library. An extensive fault injection campaign is then performed in order to verify the softerror rate due to single-event-induced charge sharing in multiple nodes. Results show that the proposed methodology becomes crucial to find the best trade-off in area, performance and soft-error rate when TMR designs are considered under multiple upsets. Results have been evaluated in a case-study circuit Advanced Encryption Standard (AES), synthesized to 90nm Application Specific Integrated Circuit (ASIC) library, and they show that combining the two techniques, the error rate resulted from multiple faults can be minimized or masked. By using TMR with different granularities and placement constraint methodology, it is possible to reduce the error rate from 11.06% to 0.00% for double faults. A detailed study of triple, four and five multiple faults combining both techniques are also described. We also tested the TMR with different granularities in SRAM-based FPGA platform. Results show that the versions with a fine grain scheme (FGTMR) were more effectiveness in masking multiple faults, similarly to results observed in the ASICs. In summary, the main contribution of this master thesis is the investigation of charge sharing effects in ASICs and the use of a combination of techniques based on TMR redundancy and placement to improve the tolerance under multiple faults.

Aplicações em ambientes expostos a elevados níveis de radiação ionizante impõem uma série de desafios ao desenvolvimento de projetos de circuitos integrados na tecnologia Complementary Metal–Oxide–Semiconductor (CMOS), uma vez que circuitos CMOS estão sujeitos às falhas transientes oriundas de radiação externa. Num circuito do tipo CMOS, as áreas sensíveis aos efeitos da incidência de partículas ionizantes são as regiões dreno-substrato reversamente polarizadas, existentes nos transistores em regime de corte (VARGAS; NICOLAIDIS, 1994). Com o avanço tecnológico e consequente diminuição das dimensões dos dispositivos semicondutores, estes efeitos degradantes tornam-se uma preocupação constante devido às menores características físicas dos transistores (WANG et al., 2007). Os circuitos integrados apresentam, durante a sua vida útil, um processo de degradação das suas características iniciais. Assim, a esse processo de degradação também chamamos de envelhecimento (aging). É um processo lento e cumulativo provocado por todos os mecanismos que acabam por alterar os parâmetros físicos e eléctricos dos circuitos, diminuindo o seu tempo de vida útil (FU; LI; FORTES, 2008). Dentre os efeitos de variabilidade temporal, os que mais têm causado interesse da comunidade científica são o Randon Telegraph Noise (RTN) com sua origem na atividade de traps (armadilhas) de interface e Single Event Transients (SET) com sua origem na radiação ionizante ao qual o circuito é exposto. Em relação aos efeitos de degradação destaca-se o efeito Bias Temperature Instability (BTI) (VALDUGA, 2012), que da mesma forma que o RTS, tem sua origem vinculada aos efeitos das traps.Modelos padrão para simulação elétrica de circuitos não levam em consideração os efeitos causados por armadilhas de cargas tais como Bias Temperature Instability (BTI) e Random Telegraph Noise (RTN). Tais variabilidades em nível de dispositivo podem causar perda de confiabilidade, como por exemplo, o surgimento de Propagation-Induced Pulse Broadening (PIPB). Conforme o escalonamento (scaling) tecnológico, a velocidade das portas lógicas aumenta e os SETs podem ser propagados através de circuito combinacional e, inclusive, sofrer alargamento, caso a largura do pulso transiente supere um valor mínimo crítico que depende da tecnologia (DODD et al., 2004), caracterizando assim um PIPB. Com base nisso, técnicas de injeção de falhas usadas em circuitos complexos não se mostram eficientemente previsíveis, levando a uma subestimativa da sensibilidade de circuitos à propagação de SETs. Com a utilização de um simulador elétrico que agrega a análise de BTI, temos melhores estimativas dos efeitos de PIPB na degradação de um circuito, que pode provocar violações de temporização em sistemas síncronos. Dessa forma, pode-se então trabalhar em uma projeção do circuito de forma a torná-lo mais robusto em relação aos efeitos de envelhecimento e na proteção às falhas transientes. Com base no que foi anteriormente apresentado, este trabalho analisa o comportamento de circuitos através de simulações elétricas de radiação ionizante, permitindo avaliações da suscetibilidade e confiabilidade de circuitos integrados aos efeitos de falhas transientes. Para a realização destes experimentos, foram realizadas simulações elétricas considerando-se os efeitos de envelhecimento. Para uma cadeia lógica de 2000 inversores sequencialmente dispostos na tecnologia 32nm pode-se prever que o pulso transiente está sujeito a um alargamento de sete vezes sua largura inicial no momento da incidência, para transistores em suas dimensões mínimas. A partir da proposta apresentada, pode-se determinar a possibilidade de alargamento ou atenuação de um SET ao longo do circuito de maneira eficiente para que as devidas precauções possam ser tomadas. / Applications in environments exposed to high levels of ionizing radiation impose a number of challenges for the development of integrated circuit designs in CMOS technology. CMOS circuits are vulnerable to transient faults from external radiation. In a CMOS circuit, areas sensitive to the effects of ionizing particle incidence are as reverse polarized drain-substrate regions in the transistors at cut-off (VARGAS; NICOLAIDIS, 1994). The technological advance and consequent downscaling of semiconductor devices, these degrading factors become a constant concern due to the higher vulnerability to transient faults (WANG et al., 2007). The integrated circuits have during their useful life a process of degradation of their initial characteristics. Thus, this process of degradation is also called aging. It is a slow and cumulative process caused by all the mechanisms that end up changing the physical and electrical parameters of the circuits, decreasing their useful timing life (FU; LI; FORTES, 2008). Among the temporal variability effects, the Randon Telegraph Noise (RTN) with its origin in the activity of traps (interface traps) and Single Event Transients (SET) with their origin in the ionizing radiation circuit is exposed. In terms of the effects of degradation, the Bias Temperature Instability (BTI) effect (VALDUGA, 2012) stands out, which, like the RTS, has its origin linked to the effects of the traps. Standard electrical simulation models do not take into account the effects caused by charged traps such as Bias temperature instability (BTI) and random telegraph noise (RTN). Such device-level variability can cause reduced reliability, for example, the Propagation-Induced Pulse Broadening (PIPB). According to the technological scaling, the speed of the logic gates increases and the SETs can be propagated through a combinational circuit and even may suffer broadening if the transient pulse width exceeds a critical minimum value that depends on the technology (DODD et al., 2004 ), characterizing a PIPB. Based on this, fault injection techniques in complex circuits are not efficiently in predicting, leading to an underestimation of circuit sensitivity to propagation of Single Event Transients (SETs). Using an electrical simulator that aggregates a BTI analysis, we have better estimates of PIPB effects on circuit degradation, which may lead to timing violations in synchronous systems. Then we can put effort in circuit design in order to make it more robust regarding to aging effects and transient faults protection. Based on what has been previously presented, this thesis analyzes the behavior of circuits through electrical simulations of ionizing radiation, allowing susceptibility and reliability evaluations of integrated circuits to the effects of transient faults using electrical simulations. For the accomplishment of these experiments, electrical simulations were performance considering the effects of aging. For a logic chain of 2000 inverters sequentially arranged in the 32nm technology it can be predicted that the transient pulse is subjected to a broadening of seven times its initial width at the time of incidence for transistors with minimum dimensions. From the analysis presented, we can evaluate the possibility of broadening or shrinking of SETs thought the circuit in an efficient way to improve radiation-hardening techniques.

<p>Nuclear particles hitting the silicon in a electronic device can cause a change in the data in a memory bit cell or in a flip-flop. The device is still working, but the data is corrupted and this is called a soft error. A soft error caused by a single nuclear particle is called a single event upset and is a growing problem. Research is ongoing at Saab aiming at how susceptible random access memories are to protons and neutrons.</p><p>This thesis describes the development of equipment for measuring cosmic-ray effects on DRAM in laboratories. The system is built on existing hardware with a FPGA as the core unit. A short history of soft errors is also given and what causes it. How a DRAM works and basic operation is explained and the difference between a SRAM. The result is a working system ready to be used.</p>

Complex reaction kinetics of the solid acid alkylation of isobutane with butenes over a proton-exchanged Y-zeolite has been modeled at the elementary step level. Starting with a computer algorithm that generated the reaction network based on the fundamentals of the carbenium ion chemistry, the formation of over 100+ product species has been modeled in order to gain understanding of the underlying phenomena leading to rapid catalyst deactivation and product selectivity shifts observed in experimental runs. An experimental investigation of the solid acid alkylation process was carried out in a fixed bed catalytic reactor operating with an excess of isobutane under isothermal conditions at moderate temperatures (353-393 K) in liquid phase. Experimental data varying with run-time for a set of butene space-times and reaction temperatures were collected for parameter estimation purposes. A kinetic model was formulated in terms of rate expressions at the elementary step level including a rigorous modeling of deactivation through site coverage. The single event concept was applied to each rate coefficient at the elementary step level to achieve a significant reduction in the number of model parameters. Based on the identification of structural changes leading to the creation or destruction of symmetry axes and chiral centers in an elementary step, formulae have been developed for the calculation of the number of single events. The Evans-Polanyi relationship and the concept of stabilization energy were introduced to account for energy levels in surface-bonded carbenium ions. A novel functional dependency of the stabilization energy with the nature of the carbenium ion and the carbon number was proposed to account for energy effects from the acid sites on the catalyst. Further reductions in the number of parameters and simplification of the equations for the transient pseudohomogeneous one-dimensional plug-flow model of the reactor were achieved by means of thermodynamic constraints. Altogether, the single event concept, the Evans-Polanyi relationship, the stabilization energy approach and the thermodynamic constraints led to a set of 14 parameters necessary for a complete description of solid acid alkylation at the elementary step level.

Two separate mechanistic kinetic models have been developed for the hydrocracking of complex feedstocks. The first model is targeted for the hydrocracking of vacuum gas oil. The second one addresses specifically the hydrocracking of long-chain paraffins, but at a more fundamental level as compared to the first one. Both models are based on an exhaustive computer generated reaction network of elementary steps. In the first model, the dehydrogenation/hydrogenation steps occurring on the metal sites to generate/consume the reactive olefinic intermediates are assumed to be very fast so that the acid site steps are considered as the rate determining steps. The frequency factors for acid site steps are modeled using the single-event concept and the activation energies based on the nature of the reactant and product carbenium ions. This model utilizes a detailed composition of the vacuum gas oil characterized by 16 different molecular classes up to carbon number 40. These classes are divided into 45 subclasses by distinguishing the isomers of a class according to the number of methyl branches. The kinetic model is plugged into an adiabatic multi-bed trickle flow reactor model. The model contains 33 feedstock and temperature independent parameters which have been estimated from the experimental data. The model has been used to study the effect of the operating conditions on the yield and composition of various products. A sensitivity analysis of the distribution of isomers of a class among its different subclasses has been performed showing that the total conversion increases when the content of isomers with a higher degree of branching is increased in the feed. In the second model, the dehydrogenation/hydrogenation steps on the metal sites are also assumed to be rate determining. The rate coefficients for the dehydrogenation steps are modeled depending on the nature of the carbon atoms forming the double bond. The frequency factors for the acid site steps are modeled using the single-event concept. A more rigorous approach has been selected to model the activation energies of the acid site steps by implementing the Evans-Polanyi relationship. The 14 model parameters, which are independent of the temperature and feedstock composition, have been estimated from the experimental data. The model elucidates the effect of the relative metal/acid activity of the catalyst on the isomerization/cracking selectivities and on the carbon number distribution of the products.