No description available.

Electrically conductive adhesives (ECA) are discussed and studied with everincreasing interest as an environmentally friendly alternative to solder interconnection in microelectronics circuit packaging. They are used to attach surface mount devices (SMD), Integrated Circuits (IC) and Flip chips in electronic assembly. The use of ECAs brings some benefits like flexibility, mild processing conditions and process simplicity. Multi walled carbon nanotubes (MWCNT) are used instead of metal fillers because of their novel properties such as light weight, high aspect ratio, corrosion resistant, reduced processing temperature, lead free, good electrical conduction and mechanical strength. The purpose of the present work is to investigate the aging behavior of MWCNT filled adhesives based on anhydride cured epoxy systems and their dependence on loading. Composites with different loadings of MWNT in epoxy and epoxy: heloxy are prepared and then stencil printed onto different surface finished boards like gold, silver and tin to prepare contact resistance samples and onto aluminum oxide boards to prepare volume resistivity samples. These samples are kept at room temperature for about 90 days and then placed in a temperature chamber to observe the behavior of these samples after accelerated aging. The readings are taken for as prepared samples, after 45 days, after 90 days and after accelerated aging. The results are summarized and different trends are observed for different loadings of MWNT, different combinations of epoxy: heloxy and for different surface finished boards.

No description available.

The objectives of this thesis are to develop and validate laser ultrasonic inspection methods for on-line testing of microelectronic devices. Electronic packaging technologies such as flip chips and BGAs utilize solder bumps as electrical and mechanical connections. Since they are located hidden from view between the device and the substrate, defects such as cracks, voids, misalignments, and missing bumps are difficult to detect using non-destructive methods. Laser ultrasonic inspection is capable of detecting such defects by utilizing a high power laser pulse to induce vibrations in a microelectronic device while measuring the out of plane displacement using an interferometer. Quality can then be assessed by comparing the vibration response of a known-good device to the response of the sample under inspection. The main limitation with the implementation of laser ultrasonic inspection in manufacturing applications is the requirement to establish a known-good reference device utilizing other non-destructive methods. My work will focus on developing a method to inspect flip chip devices without requiring a previously established reference. The method will automatically examine measurement data from a large sample set to identify those devices which are most similar. The selected devices can then be utilized to compose a hybrid reference signal which can be used for comparison and defect detection. Current trends in the electronic packaging industry continue to drive toward increased solder bump density, making it increasingly difficult to generate strong ultrasonic signals in these stiffer devices. To overcome this difficulty, I propose a new excitation method which places the source of ultrasound at the inspection location for each test point on the device surface. This ensures that the same power is available for each inspection location while also increasing the signal to noise ratio. The hardware implementation of this method reduces the system complexity and required automation, which can significantly reduce equipment cost and inspection time. The implementation of the proposed excitation method in conjunction with the use of a hybrid reference signal for defect detection will improve the utility of the laser ultrasonic inspection technique to on-line inspection applications where no other non-destructive methods are currently available.

The long-term goal of this research is to assist in the development of a fast, accurate, and low-cost nondestructive inspection prototype for solder joints in integrated circuits (IC). The goal of the work described in this thesis is to develop a fully automated system to maintain the signal strength of the vibrometer that would reduce the testing time while maintaining or improving the quality of the defect detection results. The ability to perform the inspections in an automated manner is very important in order to demonstrate the ability of the defect detection system to be used for online inspection without the need of an operator. The system was able to find the maximum signal strength (at a single point on the surface of a flip chip) nearly five times faster than Polytec's commercial system with a search time of approximately 2.1 sec. When integrated into the nondestructive inspection prototype, the system described in this work was found to approximately reduce the data acquisition time per test location by four times, with a minimum data acquisition time of 8.5 sec and an average time of 15.4 sec, while maintaining the same level of quality of results obtained by a skilled operator when manually maintaining the signal strength of the vibrometer. Hardware was developed that retrofitted a vibrometer's focusing head at the end of a fiber optic cable to a motorized linear stage. This stage controlled the standoff distance between the focusing head and the IC's surface with a fixed focal length, which allowed the spot size of the laser to be adjusted while searching for a desired signal strength. Numerous tests were conducted to determine the search parameters, which led to a search time of approximately 2.1 sec. This time was found to be dependent on the surface finish of the IC being inspected. It was also found that to achieve a desired signal intensity strength, not only does the standoff height of the focusing head, which determines the laser spot size, need to be controlled, but also the exact location on which the laser is reflecting off the IC.

Flip Chip in Package (FCIP) has been developed to achieve the assembly process with area array interconnects. Particularly, a high I/O count coupled with finer pitch area array interconnects structured FCIP can be achieved using no-flow underfill assembly process. Using the assembly process, a high, stable yield assembly process recently reported with eutectic lead-tin solder interconnections, 150 µm pitch, and I/O counts in excess of 3000. The assembly process reported created a large number of voids among solder interconnects in FCIP. The voids formed among solder interconnections can propagate, grow, and produce defects such as solder joint cracking and solder bridging. Moreover, these voids can severely reduce reliability performance. Indeed, many studies were conducted to examine the void formation in FCIP. Based on the studies, flip chip geometric design, process conditions, and material formulation have been considered as the potential causes of void formation. However, the present research won't be able to identify the mechanism of void formation, causing a lot of voids in assembly process without consideration of chemical reaction in the assembly process with a fine-pitch, high I/O density FCIP. Therefore, this research will present process technology necessary to achieve high yields in FCIP assemblies using no-flow underfills and investigate the underlying problem of underfill void formation in these assemblies. The plausible causes of void formation will be investigated using experimental techniques. The techniques will identify the primary source of the void formation. Besides, theoretical models will be established to predict the number of voids and to explain the growth behavior of voids in the FCIP. The established theoretical models will be verified by experiments. These models will validate with respect to the relationship between process parameters to achieve a high yield and to minimize voids in FCIP assemblies using no-flow underfill materials regarding process as well as material stand points. Eventually, this research provides design guideline achieving a high, stable yield and void-free assembly process.

Thesis (Ph. D.)--University of Texas at Austin, 2007. / Vita. Includes bibliographical references.

Thesis (Ph.D.)--Auburn University, 2007. / Abstract. Vita. Includes bibliographic references (ℓ. 175-)

Thesis (M.S.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department of Mechanical Engineering, 2008. / Includes bibliographical references.

Thesis (M.S.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department of Systems Science and Industrial Engineering, 2007. / Includes bibliographical references.