Characterizing hidden solder joint shapes is essential for electronics reliability. Active thermography is a methodology to identify hidden defects inside an object by means of surface abnormal thermal response after applying a heat flux. This research focused on understanding, modeling, and predicting hidden solder joint shapes. An experimental model based on active thermography was used to understand how the solder joint shapes affect the surface thermal response (grand average cooling rate or GACR) of electronic multi cover PCB assemblies. Next, a numerical model simulated the active thermography technique, investigated technique limitations and extended technique applicability to characterize hidden solder joint shapes. Finally, a prediction model determined the optimum active thermography conditions to achieve an adequate hidden solder joint shape characterization. The experimental model determined that solder joint shape plays a higher role for visible than for hidden solder joints in the GACR; however, a MANOVA analysis proved that hidden solder joint shapes are significantly different when describe by the GACR. An artificial neural networks classifier proved that the distances between experimental solder joint shapes GACR must be larger than 0.12 to achieve 85% of accuracy classifying. The numerical model achieved minimum agreements of 95.27% and 86.64%, with the experimental temperatures and GACRs at the center of the PCB assembly top cover, respectively. The parametric analysis proved that solder joint shape discriminability is directly proportional to heat flux, but inversely proportional to covers number and heating time. In addition, the parametric analysis determined that active thermography is limited to five covers to discriminate among hidden solder joint shapes. A prediction model was developed based on the parametric numerical data to determine the appropriate amount of energy to discriminate among solder joint shapes for up to five covers. The degree of agreement between the prediction model and the experimental model was determined to be within a 90.6% for one and two covers. The prediction model is limited to only three solder joints, but these research principles can be applied to generate more realistic prediction models for large scale electronic assemblies like ball grid array assemblies having as much as 600 solder joints.

Flip-chip underfilling is a technology by which silica-filled epoxy resin is used to fill the micro-cavity between a silicon chip and a substrate, by dispensing the liquid encapsulant at elevated temperatures along the periphery of one or two sides of the chip and then allowing capillary action to draw the material into the gap. Since the chip, underfill material, and substrate solidify together as one unit, thermal stresses on solder joints during the temperature cycling (which are caused by a mismatch in the coefficients of thermal expansion between the silicon chip and the organic substrate) can be redistributed and transferred away from the fragile bump zone to a more strain-tolerant region. Modeling of the flow behaviour of a fluid in the underfill process is the key to this technology. One of the most important drawbacks in the existing models is inadequate treatment of non-Newtonian fluids in the underfill process in the development of both analytical models and numerical models. Another important drawback is the neglect of the presence of solder bumps in the existing analytical models. This thesis describes a study in which a proper viscosity constitutive equation, power-law model, is employed for describing the non-Newtonian fluid behaviour in flip-chip package. Based on this constitutive equation, two analytical models with closed-form solutions for predicting the fluid filling time and fluid flow front position with respect to time were derived. One model is for a setting with two parallel plates as an approximate to flip-chip package, while the other model is for a setting with two parallel plates within which an array of solder bumps are present. Furthermore, a numerical model using a general-purpose finite element package ANSYS was developed to predict the fluid flow map in two dimensions. The superiority of these models to the existing models (primarily those developed at Cornell University in 1997) is confirmed based on the results of the experiments conducted in this study. This thesis also presents a finding of the notion of critical clearance in the design of a flip-chip package through a careful simulation study using the models developed. The flip-chip package design should make the clearance between solder bumps larger than the critical clearance.

The directive of the European parliament and of the council on the Restriction of the use of certain Hazardous Substances (RoHS) in Electrical and Electronic Equipment (EEE) took effect in the European Union on July 1, 2006. Japan, California, China and Korea are all closed markets for exporters of components containing lead from July 1, 2007. Taiwan and Australia are working with similar directives. The RoHS directive is the reason why this thesis about the implementation of lead-free soldering in highly reliable applications is necessary. The European Lead Free soldering NETwork (ELFNET) status survey from 2005 shows that the majority of the companies are well informed, but 20% are still not active in lead-free soldering. The Swedish industry is for the most part prepared and 95% of the components are lead-free. The transition to lead-free soldering will have a major affect on logistics and administration, because the RoHS directive is 90% about administration and logistics problems. Only 10% is technical problems. The higher melting point in lead-free soldering affects every stage of the lead-free manufacturing, from assembly to testing and repair. The major concern for highly reliable applications are that there are not enough data to understand to what grade lead-free solders will perform differently from lead based solders. Five different types of reliability testing were studied in this thesis; vibration, mechanical shock, thermal shock, thermal cycling and combined environments. Whiskers, voids, brittle fractures and mixed assembly problems were also studied. Individual tests alone should not be used to make definite decisions on lead-free soldering reliability. The lower reliability for lead-free solders in some tests does not necessarily mean that lead-free solders not can be used in highly reliable applications like defence electronics. The most important conclusions from this thesis are: • Update or change the logistic system and mark/label according to available standards. • Secure a good board layout. • Secure a good process control. • Alternative surface board should be used. Tin-silver-copper (SAC) is the most reliable solder and Electroless Nickel/Immersion Gold (ENIG) is the most reliable surface finish. • Remember that the higher temperature affects every stage of the manufacturing. • No increased problems with whiskers or risk of high voiding levels. • Mixed assembly is a risk. Compatibility and contamination risks must be taken seriously. • Which environment will the applications be in? If it is not a highly vibrating and thermal cycling environment, lead-free soldering should be safe to use. / Europaparlamentets och rådets direktiv om begränsning av användningen av vissa farliga ämnen i elektriska och elektroniska produkter började gälla i Europeiska unionen 1 juli, 2006. Japan, Kalifornien, Kina och Korea är alla stängda marknader för exportörer av komponenter som innehåller bly från och med 1 juli, 2007. Taiwan och Australien arbetar med liknande direktiv. RoHS-direktivet är anledningen till varför detta examensarbete om implementeringen av blyfri lödning i högtillförlitliga applikationer är nödvändigt. En undersökning från 2005 av ELFNET visar att majoriteten av företagen är väl informerade, men 20% är fortfarande i aktiva med blyfri lödning. Den svenska industrin är till största delen väl förberedd och 95% av komponenterna är blyfria. Övergången till blyfri lödning kommer att ha stor effekt på logistik och administration, därför att 90% är administrations- och logistikproblem i RoHS-direktivet. Bara 10% är tekniska problem. Den högre smälttemperaturen i blyfri lödning påverkar varje steg av den blyfria tillverkningen, från montering till testning och reparation. Den stora oron för högtillförlitliga applikationer är att det inte finns tillräckligt med data för att förstå i vilken grad som blyfria lod kommer att bete sig annorlunda jämfört med blybaserade lod. Fem olika typer av tillförlitlighetstester har undersökts i detta examensarbete; vibration, mekanisk chock, termisk chock, termisk cykling och kombinerade tester. Whiskers, voids, sprödbrott och blandad montering studerades också. Individuella tester ska inte användas för att ta några definitiva beslut om blyfri lödnings tillförlitlighet. Den lägre tillförlitligheten för blyfria lod i en del tester behöver nödvändigtvis inte betyda att blyfria lod inte kan användas i högtillförlitliga applikationer som försvarselektronik. De viktigaste slutsatserna från detta examensarbete är: • Uppdatera eller byt logistiskt system och märk enligt tillgängliga standarder. • Säkerställ en bra kretskortsdesign. • Säkerställ en bra processkontroll. • Alternativa mönsterkort bör användas. SAC är det tillförlitligaste lodet och ENIG är den tillförlitligaste ytbehandlingen. • Kom ihåg att den ökade temperaturen påverkar varje steg i tillverkningen. • Inga ökade problem med whiskers eller stort antal voids. • Blandmontage är riskfyllt. Kompatibilitet och risker med kontaminering måste tas på allvar. • Vilken miljö kommer applikationen att befinna sig i? Är det inte en starkt vibrerande eller temperaturcyklisk miljö bör blyfri lödning vara säkert att använda.

Flip-chip underfilling is a technology by which silica-filled epoxy resin is used to fill the micro-cavity between a silicon chip and a substrate, by dispensing the liquid encapsulant at elevated temperatures along the periphery of one or two sides of the chip and then allowing capillary action to draw the material into the gap. Since the chip, underfill material, and substrate solidify together as one unit, thermal stresses on solder joints during the temperature cycling (which are caused by a mismatch in the coefficients of thermal expansion between the silicon chip and the organic substrate) can be redistributed and transferred away from the fragile bump zone to a more strain-tolerant region. Modeling of the flow behaviour of a fluid in the underfill process is the key to this technology. One of the most important drawbacks in the existing models is inadequate treatment of non-Newtonian fluids in the underfill process in the development of both analytical models and numerical models. Another important drawback is the neglect of the presence of solder bumps in the existing analytical models. This thesis describes a study in which a proper viscosity constitutive equation, power-law model, is employed for describing the non-Newtonian fluid behaviour in flip-chip package. Based on this constitutive equation, two analytical models with closed-form solutions for predicting the fluid filling time and fluid flow front position with respect to time were derived. One model is for a setting with two parallel plates as an approximate to flip-chip package, while the other model is for a setting with two parallel plates within which an array of solder bumps are present. Furthermore, a numerical model using a general-purpose finite element package ANSYS was developed to predict the fluid flow map in two dimensions. The superiority of these models to the existing models (primarily those developed at Cornell University in 1997) is confirmed based on the results of the experiments conducted in this study. This thesis also presents a finding of the notion of critical clearance in the design of a flip-chip package through a careful simulation study using the models developed. The flip-chip package design should make the clearance between solder bumps larger than the critical clearance.

ABSTRACT This thesis gathered the actual Burn-In (BI) data from one of the leading cooperation in the semiconductor industry, and analyzed the major factors¡¦ impact on BGA package solder ball deformation. The Taguchi Method was used for these analyses, and the commercial statistic software MiniTab14 was widely used on this thesis. The solder ball stress was analized by using the commercial FEM software Ansys 8.1. Some electrical characters (such as device power) can be only observed from Burn-In process, but not static acceleration tests. These effects were fully discussed in this thesis. The analyses got the result that the smaller solder ball pitch/solder ball diameter causes the more serious solder ball deformation under the specific socket vendor precondition. Burn-In time are also a significant factor for solder deformation. Basically the longer BI time cause the more serious solder deformation. The device power effect is not significant within the power sampling range of this thesis.

Two subjects are included in this thesis; one is to construct the Coffin-Manson equation of the unleaded SnAgCu solder according to the experimental results provided by the Metal Research Laboratory (MRL) of Industrial Technologies Research Institute (ITRI). The results of CSP thermal cycle fatigue and SOJ pull tests and the corresponding stress and strain distributions solved from FEM analyses have been used to derive the Coffin-Manson equation for the SnAgCu solder. The other subject is to investigate the effect of CTE mismatch on the fatigue life of solder balls in the opto-electronic packaging. The solidified shapes of the different solder balls after undergoing the re-flow process are predicted by employing the Surface Evolver package program. The FEA meshes of the solidified solder balls in opto-electronic packaging are built according to the output results of the Surface Evolver program. The maximum equivalent plastic shear strain range of the solder after under one thermal cycle process is calculated by employing the MARC finite element package. The fatigue lives of solder balls under different arrangements are estimated according to the proposed Coffin-Manson equation. The effect of solder ball parameters, i.e. solder volume, solder offset distance, solder DNP and solder material on the reliability of different solder balls has also been explored in this thesis.

Thesis (M.S.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department of Systems Science and Industrial Engineering, 2009. / Includes bibliographical references.

The thermoelectric effect was discovered well over a century ago, yet performance has not shown improvement until recent years. Prior work has shown that the thermoelectric effect can be enhanced by the use of microscale pieces of thermoelectric material. Conventional assembly techniques are inadequate to deal with parts of this size, making it necessary to find a suitable alternative before these devices can be made economically. Capillary self-assembly is a promising alternative to conventional techniques. This method employs the use of preparing substrates with areas of favorable surface tension to place and align parts. Still, many obstacles have to be overcome to adapt this process for use of constructing thermoelectric coolers. The goal of this work is to overcome these obstacles and assess the viability of self-assembly for fabricating these devices. In effort to make the method more effective a process for creating more uniform deposits of solder is also assessed. This work shows that microscale thermoelectric elements can be assembled into functional thermoelectric devices using self-assembly techniques through the assembly of coolers in experimental work.

The effects of intermetallic compound (IMC) formation on reliability of Pb-free Sn-based solders for flip chip and three-dimensional (3D) interconnects were studied. The dissertation is organized into four parts. In the first part, the effect of Sn grain orientation on electromigration (EM) reliability of Pb-free Sn-based flip chip solder joints was studied. The Sn grain microstructure in flip chip solder joints was characterized using the electron backscatter diffraction (EBSD) technique, and wa found to be closely related to the EM failure mechanims. The approach to grain structure optimization for improved EM reliability was also explored. In addition to the experimental work, a kinetic analysis was formulated to investigate the early EM degradation mechanism in Sn-based solder joints with Ni under-bump metallization (UMB). The aforementioned kinetic analysis, the intrinsic diffusion coefficients were not readily available in the literature. In the second part of the work, a Monte Carlo method known as simulated annealing was applied to estimate the unknown diffusion coefficients using a multi-parameter optimization method by fitting to experimental measurements. The intrinsic diffusion coefficients of Ni and Sn in Ni₃Sn₄ between 150 and 200°C, and those of Cu and Sn in Cu₃Sn and Cu₆Sn₅ between 120 and 200°C were estimatd. The activation energies for these diffusion coefficients were also determined. Together, this provides the diffusivity parameters to predict the intermetallic growth as a function of temperature. The third objective focused on the EM reliability of Sn-based microbump joints in 3D interconnects with through-silicon vias (TSVs). No EM-induced bump failure was observed, showing a robust EM reliability in microbumps. High temperature thermal annealing test was also performed on microbumps with three different metallizations in an effort to explore structural and process optimization. Finally, interfacial reaction induced stress in IMC microbumps was investigated. A numerial analysis was formulated to study the concurrent diffusion, phase transformation, and deformation in the process of IMC formation. Stress generation due to unbalanced diffusion rates and volumetric change upon phase transformation was considered. The coupled analysis was applied to investigate Ni₃Sn₄ growth in the Ni-Sn microbumping system. A simulation approach based on finite difference method with moving boundaries was employed to numerically solve stress evolution in Ni₃Sn₄. The equilibrium stress was also investigated using a modified model with a finite thickness of solder. Simulation predictions were found to be in good qualitative agreement with experimental observations. / text

The state of the art in artificial micro self assembly concepts are reviewed. The history of assembly is presented with a comparison to macro assembly, which has been widely studied, and micro self assembly. Criteria were developed and tested to show that macro assembly is more complex in ways that micro self assembly is not. Self assembly requirements for successful and complex self assembly, which evolved from the macro and micro comparison, are also established and tested. A method to assemble complex structures in the micro scale is proposed and demonstrated at the meso scale. The basic concepts of self assembly and a novel approach to complex multi layer self assembly is analyzed.